KR102067200B1 - 공진 클록 모드와 통상의 클록 모드 간의 전이 - Google Patents

공진 클록 모드와 통상의 클록 모드 간의 전이 Download PDF

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Publication number
KR102067200B1
KR102067200B1 KR1020157007590A KR20157007590A KR102067200B1 KR 102067200 B1 KR102067200 B1 KR 102067200B1 KR 1020157007590 A KR1020157007590 A KR 1020157007590A KR 20157007590 A KR20157007590 A KR 20157007590A KR 102067200 B1 KR102067200 B1 KR 102067200B1
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South Korea
Prior art keywords
switches
switch
inductor
clock
clock network
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Korean (ko)
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KR20150052118A (ko
Inventor
비스베쉬 에스. 사쓰
스리칸쓰 아레카푸디
찰리스 오양
카일 비오
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/53Generators characterised by the type of circuit or by the means used for producing pulses by the use of an energy-accumulating element discharged through the load by a switching device controlled by an external signal and not incorporating positive feedback
    • H03K3/57Generators characterised by the type of circuit or by the means used for producing pulses by the use of an energy-accumulating element discharged through the load by a switching device controlled by an external signal and not incorporating positive feedback the switching device being a semiconductor device
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Electronic Switches (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Coils Or Transformers For Communication (AREA)
KR1020157007590A 2012-08-31 2013-08-30 공진 클록 모드와 통상의 클록 모드 간의 전이 Active KR102067200B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261695702P 2012-08-31 2012-08-31
US61/695,702 2012-08-31
US13/963,300 US8941432B2 (en) 2012-08-31 2013-08-09 Transitioning between resonant clocking mode and conventional clocking mode
US13/963,300 2013-08-09
PCT/US2013/057614 WO2014036457A1 (en) 2012-08-31 2013-08-30 Transitioning between resonant clocking mode and conventional clocking mode

Publications (2)

Publication Number Publication Date
KR20150052118A KR20150052118A (ko) 2015-05-13
KR102067200B1 true KR102067200B1 (ko) 2020-01-17

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KR1020157007590A Active KR102067200B1 (ko) 2012-08-31 2013-08-30 공진 클록 모드와 통상의 클록 모드 간의 전이

Country Status (7)

Country Link
US (1) US8941432B2 (enExample)
EP (1) EP2891026B1 (enExample)
JP (1) JP6307506B2 (enExample)
KR (1) KR102067200B1 (enExample)
CN (1) CN104583892B (enExample)
IN (1) IN2015DN02273A (enExample)
WO (1) WO2014036457A1 (enExample)

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US9429982B2 (en) * 2014-09-27 2016-08-30 Qualcomm Incorporated Configurable last level clock driver for improved energy efficiency of a resonant clock
US9612614B2 (en) 2015-07-31 2017-04-04 International Business Machines Corporation Pulse-drive resonant clock with on-the-fly mode change
US9634654B2 (en) 2015-08-07 2017-04-25 International Business Machines Corporation Sequenced pulse-width adjustment in a resonant clocking circuit
US9568548B1 (en) 2015-10-14 2017-02-14 International Business Machines Corporation Measurement of signal delays in microprocessor integrated circuits with sub-picosecond accuracy using frequency stepping
DE112019004164T5 (de) * 2018-08-21 2021-06-02 Sony Semiconductor Solutions Corporation Halbleiterschaltungsvorrichtung und system, ausgestattet mit halbleiterschaltungsvorrichtung
JP2021002542A (ja) * 2019-06-19 2021-01-07 ソニーセミコンダクタソリューションズ株式会社 アバランシェフォトダイオードセンサ及び測距装置
US11444619B2 (en) * 2020-09-07 2022-09-13 Changxin Memory Technologies, Inc. Driving circuit

Citations (1)

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Publication number Priority date Publication date Assignee Title
JP2012161039A (ja) * 2011-02-02 2012-08-23 Renesas Electronics Corp クロックバッファ回路及びこれを用いたクロック分配回路

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AU5382494A (en) 1994-01-18 1995-08-03 Premlex Pty. Ltd. A switching circuit
US6025738A (en) 1997-08-22 2000-02-15 International Business Machines Corporation Gain enhanced split drive buffer
US6088250A (en) 1998-05-29 2000-07-11 The Aerospace Corporation Power converters for multiple input power supplies
US6205571B1 (en) 1998-12-29 2001-03-20 International Business Machines Corporation X-Y grid tree tuning method
US6310499B1 (en) 2000-07-17 2001-10-30 Hewlett-Packard Company Methods and apparatus for adjusting the deadtime between non-overlapping clock signals
AU2002323170A1 (en) * 2002-08-14 2004-03-03 Ovonyx, Inc. Adhesive material for programmable device
US6975525B2 (en) * 2002-11-14 2005-12-13 Fyre Storm, Inc. Method of controlling the operation of a power converter having first and second series connected transistors
US7015765B2 (en) 2003-01-13 2006-03-21 The Trustees Of Columbia In The City Of New York Resonant clock distribution for very large scale integrated circuits
US7082580B2 (en) 2003-02-10 2006-07-25 Lsi Logic Corporation Energy recycling in clock distribution networks using on-chip inductors
TWI261158B (en) 2003-09-08 2006-09-01 Via Tech Inc Method and related apparatus for outputting clock through data path
US6882182B1 (en) 2003-09-23 2005-04-19 Xilinx, Inc. Tunable clock distribution system for reducing power dissipation
US7237217B2 (en) 2003-11-24 2007-06-26 International Business Machines Corporation Resonant tree driven clock distribution grid
JP4127399B2 (ja) * 2004-03-31 2008-07-30 松下電器産業株式会社 スイッチング電源制御用半導体装置
US7516350B2 (en) 2004-09-09 2009-04-07 International Business Machines Corporation Dynamic frequency scaling sequence for multi-gigahertz microprocessors
JP4212569B2 (ja) * 2005-04-01 2009-01-21 株式会社デンソー スイッチング装置
JP2007034839A (ja) * 2005-07-28 2007-02-08 Matsushita Electric Ind Co Ltd 集積回路の動作周波数制御方法
US7956664B2 (en) 2006-12-01 2011-06-07 The Regents Of The University Of Michigan Clock distribution network architecture with clock skew management
US7973565B2 (en) 2007-05-23 2011-07-05 Cyclos Semiconductor, Inc. Resonant clock and interconnect architecture for digital devices with multiple clock networks
JP2010178053A (ja) * 2009-01-29 2010-08-12 Hiroshima Univ 中央演算処理装置
US8593183B2 (en) 2009-10-12 2013-11-26 Cyclos Semiconductor, Inc. Architecture for controlling clock characteristics
US8427252B2 (en) * 2011-05-31 2013-04-23 Qualcomm Incorporated Oscillators with low power mode of operation
US8719748B2 (en) 2011-06-29 2014-05-06 The Regents Of The University Of California Distributed resonant clock grid synthesis
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Patent Citations (1)

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Publication number Priority date Publication date Assignee Title
JP2012161039A (ja) * 2011-02-02 2012-08-23 Renesas Electronics Corp クロックバッファ回路及びこれを用いたクロック分配回路

Also Published As

Publication number Publication date
EP2891026A1 (en) 2015-07-08
EP2891026B1 (en) 2016-06-22
JP6307506B2 (ja) 2018-04-04
JP2015534671A (ja) 2015-12-03
US8941432B2 (en) 2015-01-27
US20140062566A1 (en) 2014-03-06
IN2015DN02273A (enExample) 2015-08-21
KR20150052118A (ko) 2015-05-13
CN104583892A (zh) 2015-04-29
WO2014036457A1 (en) 2014-03-06
CN104583892B (zh) 2018-03-23

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