JP6307506B2 - 共振クロッキングモードと通常のクロッキングモードとの間の遷移 - Google Patents

共振クロッキングモードと通常のクロッキングモードとの間の遷移 Download PDF

Info

Publication number
JP6307506B2
JP6307506B2 JP2015530110A JP2015530110A JP6307506B2 JP 6307506 B2 JP6307506 B2 JP 6307506B2 JP 2015530110 A JP2015530110 A JP 2015530110A JP 2015530110 A JP2015530110 A JP 2015530110A JP 6307506 B2 JP6307506 B2 JP 6307506B2
Authority
JP
Japan
Prior art keywords
inductor
switches
switch
clock
clock network
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2015530110A
Other languages
English (en)
Japanese (ja)
Other versions
JP2015534671A (ja
Inventor
エス． サテ ヴィスヴェイシュ
エス． サテ ヴィスヴェイシュ
アレカプディ スリカンス
アレカプディ スリカンス
オウヤン チャールズ
オウヤン チャールズ
ヴィヨー カイル
ヴィヨー カイル
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2015534671A publication Critical patent/JP2015534671A/ja
Application granted granted Critical
Publication of JP6307506B2 publication Critical patent/JP6307506B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/53—Generators characterised by the type of circuit or by the means used for producing pulses by the use of an energy-accumulating element discharged through the load by a switching device controlled by an external signal and not incorporating positive feedback
    • H03K3/57—Generators characterised by the type of circuit or by the means used for producing pulses by the use of an energy-accumulating element discharged through the load by a switching device controlled by an external signal and not incorporating positive feedback the switching device being a semiconductor device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Electronic Switches (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Coils Or Transformers For Communication (AREA)
JP2015530110A 2012-08-31 2013-08-30 共振クロッキングモードと通常のクロッキングモードとの間の遷移 Active JP6307506B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261695702P 2012-08-31 2012-08-31
US61/695,702 2012-08-31
US13/963,300 US8941432B2 (en) 2012-08-31 2013-08-09 Transitioning between resonant clocking mode and conventional clocking mode
US13/963,300 2013-08-09
PCT/US2013/057614 WO2014036457A1 (en) 2012-08-31 2013-08-30 Transitioning between resonant clocking mode and conventional clocking mode

Publications (2)

Publication Number Publication Date
JP2015534671A JP2015534671A (ja) 2015-12-03
JP6307506B2 true JP6307506B2 (ja) 2018-04-04

Family

ID=49213103

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015530110A Active JP6307506B2 (ja) 2012-08-31 2013-08-30 共振クロッキングモードと通常のクロッキングモードとの間の遷移

Country Status (7)

Country Link
US (1) US8941432B2 (enExample)
EP (1) EP2891026B1 (enExample)
JP (1) JP6307506B2 (enExample)
KR (1) KR102067200B1 (enExample)
CN (1) CN104583892B (enExample)
IN (1) IN2015DN02273A (enExample)
WO (1) WO2014036457A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9429982B2 (en) * 2014-09-27 2016-08-30 Qualcomm Incorporated Configurable last level clock driver for improved energy efficiency of a resonant clock
US9612614B2 (en) 2015-07-31 2017-04-04 International Business Machines Corporation Pulse-drive resonant clock with on-the-fly mode change
US9634654B2 (en) 2015-08-07 2017-04-25 International Business Machines Corporation Sequenced pulse-width adjustment in a resonant clocking circuit
US9568548B1 (en) 2015-10-14 2017-02-14 International Business Machines Corporation Measurement of signal delays in microprocessor integrated circuits with sub-picosecond accuracy using frequency stepping
DE112019004164T5 (de) * 2018-08-21 2021-06-02 Sony Semiconductor Solutions Corporation Halbleiterschaltungsvorrichtung und system, ausgestattet mit halbleiterschaltungsvorrichtung
JP2021002542A (ja) * 2019-06-19 2021-01-07 ソニーセミコンダクタソリューションズ株式会社 アバランシェフォトダイオードセンサ及び測距装置
US11444619B2 (en) * 2020-09-07 2022-09-13 Changxin Memory Technologies, Inc. Driving circuit

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU5382494A (en) 1994-01-18 1995-08-03 Premlex Pty. Ltd. A switching circuit
US6025738A (en) 1997-08-22 2000-02-15 International Business Machines Corporation Gain enhanced split drive buffer
US6088250A (en) 1998-05-29 2000-07-11 The Aerospace Corporation Power converters for multiple input power supplies
US6205571B1 (en) 1998-12-29 2001-03-20 International Business Machines Corporation X-Y grid tree tuning method
US6310499B1 (en) 2000-07-17 2001-10-30 Hewlett-Packard Company Methods and apparatus for adjusting the deadtime between non-overlapping clock signals
AU2002323170A1 (en) * 2002-08-14 2004-03-03 Ovonyx, Inc. Adhesive material for programmable device
US6975525B2 (en) * 2002-11-14 2005-12-13 Fyre Storm, Inc. Method of controlling the operation of a power converter having first and second series connected transistors
US7015765B2 (en) 2003-01-13 2006-03-21 The Trustees Of Columbia In The City Of New York Resonant clock distribution for very large scale integrated circuits
US7082580B2 (en) 2003-02-10 2006-07-25 Lsi Logic Corporation Energy recycling in clock distribution networks using on-chip inductors
TWI261158B (en) 2003-09-08 2006-09-01 Via Tech Inc Method and related apparatus for outputting clock through data path
US6882182B1 (en) 2003-09-23 2005-04-19 Xilinx, Inc. Tunable clock distribution system for reducing power dissipation
US7237217B2 (en) 2003-11-24 2007-06-26 International Business Machines Corporation Resonant tree driven clock distribution grid
JP4127399B2 (ja) * 2004-03-31 2008-07-30 松下電器産業株式会社 スイッチング電源制御用半導体装置
US7516350B2 (en) 2004-09-09 2009-04-07 International Business Machines Corporation Dynamic frequency scaling sequence for multi-gigahertz microprocessors
JP4212569B2 (ja) * 2005-04-01 2009-01-21 株式会社デンソー スイッチング装置
JP2007034839A (ja) * 2005-07-28 2007-02-08 Matsushita Electric Ind Co Ltd 集積回路の動作周波数制御方法
US7956664B2 (en) 2006-12-01 2011-06-07 The Regents Of The University Of Michigan Clock distribution network architecture with clock skew management
US7973565B2 (en) 2007-05-23 2011-07-05 Cyclos Semiconductor, Inc. Resonant clock and interconnect architecture for digital devices with multiple clock networks
JP2010178053A (ja) * 2009-01-29 2010-08-12 Hiroshima Univ 中央演算処理装置
US8593183B2 (en) 2009-10-12 2013-11-26 Cyclos Semiconductor, Inc. Architecture for controlling clock characteristics
JP2012161039A (ja) * 2011-02-02 2012-08-23 Renesas Electronics Corp クロックバッファ回路及びこれを用いたクロック分配回路
US8427252B2 (en) * 2011-05-31 2013-04-23 Qualcomm Incorporated Oscillators with low power mode of operation
US8719748B2 (en) 2011-06-29 2014-05-06 The Regents Of The University Of California Distributed resonant clock grid synthesis
US8576000B2 (en) 2011-08-25 2013-11-05 International Business Machines Corporation 3D chip stack skew reduction with resonant clock and inductive coupling

Also Published As

Publication number Publication date
EP2891026A1 (en) 2015-07-08
EP2891026B1 (en) 2016-06-22
JP2015534671A (ja) 2015-12-03
US8941432B2 (en) 2015-01-27
US20140062566A1 (en) 2014-03-06
IN2015DN02273A (enExample) 2015-08-21
KR20150052118A (ko) 2015-05-13
CN104583892A (zh) 2015-04-29
KR102067200B1 (ko) 2020-01-17
WO2014036457A1 (en) 2014-03-06
CN104583892B (zh) 2018-03-23

Similar Documents

Publication Publication Date Title
JP6307506B2 (ja) 共振クロッキングモードと通常のクロッキングモードとの間の遷移
Teh et al. Conditional data mapping flip-flops for low-power and high-performance systems
US8854100B2 (en) Clock driver for frequency-scalable systems
US7930674B2 (en) Modifying integrated circuit designs to achieve multiple operating frequency targets
KR20120095393A (ko) 공진 클록 분배 네트워크에서의 주파수 스케일링된 동작을 위한 아키텍처
US20230306174A1 (en) Reduced-power dynamic data circuits with wide-band energy recovery
US9612614B2 (en) Pulse-drive resonant clock with on-the-fly mode change
US8975936B2 (en) Constraining clock skew in a resonant clocked system
US8791726B2 (en) Controlled resonant power transfer
US10833664B2 (en) Supply tracking delay element in multiple power domain designs
ur Rahman et al. Quasi-resonant clocking: Continuous voltage-frequency scalable resonant clocking system for dynamic voltage-frequency scaling systems
US10263519B2 (en) Resonant virtual supply booster for synchronous digital circuits having a predictable evaluate time
Akl et al. An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transition
JP6063047B2 (ja) より効率的なクロッキングを提供するための高インピーダンス電圧源を用いたスイッチのインピーダンス制御
CN105048998A (zh) 冗余时钟转变容限锁存电路
US10389356B2 (en) Resonant virtual supply booster for synchronous logic circuits and other circuits with use of on-chip integrated magnetic inductor
US20070216449A1 (en) Reduction of the time for executing an externally commanded transfer of data in an integrated device
JP2011227576A (ja) ノイズ解析装置及びノイズ解析方法

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20160803

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20170525

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170606

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170901

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170919

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20171214

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180206

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20180306

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20180312

R150 Certificate of patent or registration of utility model

Ref document number: 6307506

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250