KR102045236B1 - 팬-아웃 반도체 패키지 - Google Patents

팬-아웃 반도체 패키지 Download PDF

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Publication number
KR102045236B1
KR102045236B1 KR1020160107687A KR20160107687A KR102045236B1 KR 102045236 B1 KR102045236 B1 KR 102045236B1 KR 1020160107687 A KR1020160107687 A KR 1020160107687A KR 20160107687 A KR20160107687 A KR 20160107687A KR 102045236 B1 KR102045236 B1 KR 102045236B1
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KR
South Korea
Prior art keywords
layer
disposed
semiconductor chip
fan
connection member
Prior art date
Application number
KR1020160107687A
Other languages
English (en)
Korean (ko)
Other versions
KR20170138906A (ko
Inventor
김정수
변대정
이두환
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to US15/368,025 priority Critical patent/US9859222B1/en
Priority to TW105140305A priority patent/TWI662661B/zh
Priority to JP2016240422A priority patent/JP6443893B2/ja
Publication of KR20170138906A publication Critical patent/KR20170138906A/ko
Application granted granted Critical
Publication of KR102045236B1 publication Critical patent/KR102045236B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020160107687A 2016-06-08 2016-08-24 팬-아웃 반도체 패키지 KR102045236B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US15/368,025 US9859222B1 (en) 2016-06-08 2016-12-02 Fan-out semiconductor package
TW105140305A TWI662661B (zh) 2016-06-08 2016-12-07 扇出型半導體封裝
JP2016240422A JP6443893B2 (ja) 2016-06-08 2016-12-12 ファン−アウト半導体パッケージ

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20160070900 2016-06-08
KR1020160070900 2016-06-08

Publications (2)

Publication Number Publication Date
KR20170138906A KR20170138906A (ko) 2017-12-18
KR102045236B1 true KR102045236B1 (ko) 2019-12-02

Family

ID=60923158

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020160107687A KR102045236B1 (ko) 2016-06-08 2016-08-24 팬-아웃 반도체 패키지

Country Status (2)

Country Link
KR (1) KR102045236B1 (zh)
TW (1) TWI662661B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190121560A (ko) * 2018-04-18 2019-10-28 삼성전기주식회사 팬-아웃 반도체 패키지
KR102465535B1 (ko) 2018-11-26 2022-11-11 삼성전자주식회사 팬-아웃 반도체 패키지
KR102632367B1 (ko) * 2018-12-04 2024-02-02 삼성전기주식회사 반도체 패키지
CN114446927B (zh) * 2020-10-30 2024-10-18 瑞昱半导体股份有限公司 电感器装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050161823A1 (en) * 2004-01-27 2005-07-28 Casio Computer Co., Ltd. Semiconductor device
JP2011114079A (ja) * 2009-11-25 2011-06-09 Renesas Electronics Corp 半導体装置、半導体パッケージ、及び半導体装置の製造方法
US20110254156A1 (en) * 2007-12-03 2011-10-20 Stats Chippac, Ltd. Semiconductor Device and Method of Wafer Level Package Integration
JP2012039090A (ja) * 2010-07-15 2012-02-23 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100606654B1 (ko) * 2005-08-01 2006-08-01 삼성전자주식회사 전자파 장해 저감용 페라이트 차폐 구조를 구비하는 반도체패키지 및 그 제조 방법
US9842798B2 (en) * 2012-03-23 2017-12-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a PoP device with embedded vertical interconnect units

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050161823A1 (en) * 2004-01-27 2005-07-28 Casio Computer Co., Ltd. Semiconductor device
US20110254156A1 (en) * 2007-12-03 2011-10-20 Stats Chippac, Ltd. Semiconductor Device and Method of Wafer Level Package Integration
JP2011114079A (ja) * 2009-11-25 2011-06-09 Renesas Electronics Corp 半導体装置、半導体パッケージ、及び半導体装置の製造方法
JP2012039090A (ja) * 2010-07-15 2012-02-23 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法

Also Published As

Publication number Publication date
TW201743413A (zh) 2017-12-16
TWI662661B (zh) 2019-06-11
KR20170138906A (ko) 2017-12-18

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