KR101981135B1 - Method of manufacturing the circuit board - Google Patents

Abstract

The present invention relates to a method and apparatus for selectively transferring a circuit pattern to a surface-modified surface by selectively transferring a circuit pattern onto an optical image-processable material capable of selectively modifying the surface and then selectively exposing the surface of the PID material to ultraviolet Layer to form a copper foil trace having a fine pattern on the order of several micrometers.

Description

[0001] METHOD OF MANUFACTURING THE CIRCUIT BOARD [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board manufacturing method and more particularly to a circuit board manufacturing method and a circuit board manufacturing method for manufacturing a circuit board having a fine pattern circuit board (PCB), more specifically, a circuit line width of about 5 micrometer Technology.

Background Art [0002] With the recent demand for high integration and high density of electronic devices, miniaturization of electronic components is accelerating. Accordingly, there is a demand for a method for manufacturing a copper-clad circuit having fine pitches of several micrometers in a circuit board, particularly a package substrate or a wafer-level package substrate, on which electronic components such as semiconductor chips or modules are mounted.

For this purpose, we have developed an ETS (Embedded Trace Substrate) method that embeds a copper semi-additive process (SAP), a modified semi-additive process (MSAP) And so on.

Prior arts are disclosed in the following prior art documents: Korean Patent Publication Nos. 10-2017-0032946, 10-2017-0029035, 1,580,472, 10-2017-0041161, 10-2017-0031271.

FIG. 1 and FIG. 2 are cross-sectional views of a substrate on which a circuit of a fine pattern is formed according to the related art. 1 is a cross-sectional view of a substrate on which a circuit pattern is formed by the ETS method according to the prior art. Referring to FIG. 1, it can be seen that the copper foil traces 11 are buried in the insulating layer 12.

Referring to FIG. 1 again, the conventional technology has a structure in which the adhesive layers 10b and 10d are interposed between the middle insulating layer 10c and the copper foils 10a and 10e so that the copper foils 10a and 10e can be easily peeled off. a dry film is closely contacted with a dry film to transfer a circuit pattern and an image process is carried out to produce a plating mask in which a circuit pattern is transferred. Then, the copper foils 10a and 10e of the decolorizable core are seeded for electrolytic copper plating The copper foil trace 11 is formed by electrolytic copper plating so as to act as a seed layer. Subsequently, the surface of the copper foil trace 11 is subjected to a Cz surface treatment or a flat bond treatment for securing the adhesion with the insulating layer 14 to be laminated.

2 is a cross-sectional view of a circuit board manufactured by applying a semi-additive process (SAP) according to the prior art.

2, circuits 21a and 21c are formed in an inner layer using a starting material such as a copper clad laminate (CCL), a buildup material such as a prepreg PREPREG is laminated, an SAP method is applied To form an outer layer circuit, in order to conduct electrolytic copper plating on the outer layer, a seed layer 22 is selectively formed on the surface of the laminated insulating layer 24, followed by electrolytic copper plating.

However, in order to use the SAP method of FIG. 2 as a method for forming a circuit of a level of ~ 5 micrometers (탆), it is necessary to use an expensive method such as sputtering in a step of selectively forming an electroless plated layer . Furthermore, even if a fine circuit pattern of several micrometers level is formed, the surface of the copper foil circuit must be subjected to a Cz surface treatment or a flat bond treatment in order to process a protective film such as a solder resist. In this process, There arises a problem that the design rule is damaged.

Also, in the case of the prior art shown in Fig. 1, the Cz surface treatment must be performed on the copper foil trace 11 in order to strengthen the adhesion before the insulating material 14 such as a prepreg is laminated. There arises a problem that the design rule regarding the line width and the interval can not be maintained.

In addition, in the prior art of FIG. 2, after the electrolytic copper plating is performed, a process such as a half etching or a flash etching is required to remove the seed layer 22 which has been coated on the bottom. In this process, There is a problem that the surface is damaged. In addition, since the seed layer is not coated on the sidewall of the insulating layer and the copper plating does not grow from the sidewall interface, the problem of pattern lift may occur due to insufficient adhesion.

1. Korean Patent Publication No. 10-2017-0032946. 2. Korean Patent Publication No. 10-2017-0029035. 3. Korean Patent Registration No. 10-2015-01580472. 4. Korean Patent Publication No. 10-2017-0041161. 5. Korean Patent Publication No. 10-2017-0031271.

A first object of the present invention is to provide a method of manufacturing a circuit pattern of a fine pattern capable of realizing a copper foil circuit having a line width and an interval of several micrometers (~ 5 mu m).

A second object of the present invention is to provide a method for manufacturing a circuit board which can selectively form an electroless plated layer without depending on an expensive method such as a sputtering method in coating a seed layer for selective electrolytic copper plating on a surface have.

A third object of the present invention is to provide a circuit board manufacturing method capable of preventing the pattern lift shape by forming a seed layer on the front surface side of the plated layer to which the circuit pattern is transferred as well as on the side wall surface, It is in providing the construction method.

A fourth object of the present invention is to provide a circuit board manufacturing method that does not require an additional etching process to remove the exposed seed layer after electroplating.

In order to achieve the first and fourth objects of the present invention, the present invention provides a photo imageable dielectric (hereinafter, referred to as PID material) capable of selectively changing a material property, After the pattern is transferred, the surface of the PID material on the bottom is selectively exposed to ultraviolet rays (UV) to selectively form a seed layer only on the surface-modified surface, and then the electrolytic copper plating and the ETS method are applied to perform a sputtering process or a subsequent etching process The copper trace of fine pattern of several micrometer level is produced.

The present invention is advantageous in that it is not necessary to use an expensive process because it is not necessary to form a seed layer by a sputtering method for selective electrolytic copper plating. The present invention has the advantage of simultaneously performing an image process and a lamination process for pattern transfer using a PID material.

In addition, in the present invention, copper plating is formed on not only the front surface but also the side surface of the plated layer (PID material) formed by the fine pitch width and spacing, so that the adhesion is excellent and the pattern lift problem, which is often caused in fine pitch circuits, is solved do. Further, since the present invention can omit the subsequent etch process, it is possible to avoid etch damage caused during the etching process.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a substrate on which a circuit pattern is formed by an ETS method according to the prior art. FIG.
2 is a sectional view of a circuit wiring board manufactured by applying a semi-additive process (SAP) according to the prior art
3 is a diagrammatic representation of a state in which the PID material according to the present invention is irradiated with ultraviolet rays and the reaction proceeds on the surface.
4A to 4F are views illustrating a process in which electroless copper plating proceeds by modifying the surface of a PID material by ultraviolet rays according to the present invention.
5A to 5K are views showing a method of forming a circuit of a fine pattern according to the present invention.

Hereinafter, a circuit board manufacturing method according to the present invention will be described in detail with reference to FIGS. 3 to 5.

The present invention can use a detachable core used in a conventional ETS process as a starting material. The present invention uses a photo imageable dielectric (hereinafter referred to as PID material) instead of using a conventional dry film in an image processing step for circuit pattern transfer. .

The PID material according to the present invention is capable of surface modification when ultraviolet (UV) is exposed to the surface. The PID material according to the present invention can selectively use high-resolution and low-resolution materials. The PID material according to the present invention can be used as a photosensitive material in a series of image processes for transferring circuit patterns such as photos, exposure, development, etc., and is an organic coupling dielectric of carbon and oxygen.

In the case of a conventional dry film conventionally used, when a circuit pattern is used as a photo mask for transferring to a substrate, the dry film used is usually peeled off from the substrate. However, the PID material Is used not only as a photosensitive material for transferring a high resolution circuit pattern but also as a dielectric material for lamination such as a prepreg.

In addition, the PID material according to the present invention is characterized in that, when exposed to ultraviolet light (UV), the surface of a site illuminated with ultraviolet light is modified, and electroless copper plating proceeds only at the surface- do.

Referring to FIG. 3, the surface modification mechanism of the PID material according to the present invention will be described. FIG. 3 is a diagram showing a state in which the PID material according to the present invention is irradiated with ultraviolet light and the reaction proceeds on the surface. According to a preferred embodiment of the present invention, ultraviolet rays having a wavelength of 184.9 nanometers (nm) and a wavelength of 253.7 nanometers (nm) are incident on organic bonding materials of carbon, hydrogen, and oxygen. When oxygen in the atmosphere (O ₂ ) reacts with ultraviolet light of 184.9 nm wavelength, the oxygen molecule is decomposed into two triple atomic oxygen atoms as shown in the following chemical formula (1).

Then, as shown in Formula 2, the oxygen molecule reacts with the triple oxygen atom to form ozone (O ₃ ) having excellent surface oxidizing ability. Ozone (O ₃ ), which has excellent surface oxidizing power, modifies the surface of the PID material.

In addition, if ultraviolet rays of 253.7 nm wavelength are irradiated to ozone (O ₃ ) molecules, oxygen radicals are decomposed into O ( ¹ D) and oxygen molecules. Oxygen radicals are also excellent in surface oxidizing ability, thereby modifying the surface of PID materials . Where O ( ³ P) is the ground state triplet atomic oxygeon and O ( ¹ D) is the single atomic oxygeon, the oxygen radical.

4A to 4F are views illustrating a process of modifying the surface of a PID material by ultraviolet rays to proceed with electroless copper plating according to the present invention. Referring to FIG. 4A, a mask is placed on the surface of the PID material according to the present invention, and the surface is selectively exposed to UV by irradiating UV light. The PID surface exposed to ultraviolet rays is surface modified by ozone (O ₃ ) molecules and O ( ¹ D) oxygen radicals to form a carboxyl group (C - O - O - H) or a hydroxyl group (hydroxyl). As a result, the surface modified with a carboxyl group or a hydroxyl group has considerably improved wetting property.

Referring to FIG. 4B, when the NaOH treatment is performed, the hydrogen of the carboxyl group is replaced with sodium ion (Na) to be converted into a C - O - O - Na (sodium acetate) structure. C - O - O - Na (sodium acetate) has better palladium (Pa) adsorption power than the carboxyl group (C - O - O - H). Referring to FIG. 4C, palladium catalyst treatment is conducted using palladium chloride (PdCl ₂ ) or palladium sulfate (PdSO ₄ ) solution to induce Na - Pd bond. Referring to FIG. 4D, since Cl or SO ₄ is adhered, it is removed by treatment with a reducing agent.

Referring to FIG. 4D, Pd which has been weakly adsorbed is removed by ultrasonic treatment. Finally, referring to FIG. 4E, palladium is adsorbed on the electroless copper plating solution, copper is precipitated on the palladium, and finally the electroless copper plating layer is formed only on the portion where the surface is modified by selective exposure to UV.

Hereinafter, a method of implementing a circuit of a fine pattern according to the present invention will be described with reference to FIGS. 5A to 5K. FIG. Referring to FIG. 5A, a PID material 20 according to the present invention is laminated to the decoratable core 10, and a series of image processes such as photography, exposure, and development are performed according to a predetermined circuit pattern, 20).

The detachable core 10 is covered with copper foils 10a and 10e on both surfaces of the central insulating layer 10c and an adhesive layer 10b and 10d is formed between the insulating layer 10c and the copper foils 10a and 10e Is a starting material of a structure capable of peeling off the adhesive layers 10b and 10d by separating the structure on the copper foils 10a and 10e to be manufactured in the subsequent process from the central insulator 10c.

Referring to FIG. 5B, the mask 300 is placed on the transferred PID material 20 to illuminate ultraviolet rays. At this time, the mask is fabricated such that the front surface of the PID material 20 on which the pattern has already been transferred is shielded and the side surface of the pattern in which the upper and lower steps are formed is exposed.

In this case, the front surface of the PID material 20 is not exposed to UV so that the surface is not modified, but the side surface of the PID material 20 is exposed to UV so that the surface is selectively modified. Then, electroless copper plating is performed by the method described above with reference to Figs. 4A to 4F.

That is, following the UV exposure step, NaOH treatment is performed to form a carboxyl group having good hydrophilicity on the surface, and palladium catalyzed treatment is performed using palladium chloride (PdCl ₂ ) or palladium sulfate (PdSO ₄ ) solution to induce Na - Pd bond . Subsequently, Cl or SO ₄ ions attached to the palladium are removed by treatment with a reducing agent, and palladium which is weakly adsorbed to the carbon atoms is removed through ultrasonic treatment. Then, the electroless copper plating layer 30 is formed only in the area where the surface is finally modified by being immersed in the electroless copper plating solution. 5C, copper (Cu) is not formed on the PID pattern shape and copper (Cu) is filled only on the side surfaces between the PID materials 20, so that the copper plating layer 40 are formed.

Referring to FIG. 5D, a plating deviation is generated, and if necessary, the surface of the substrate can be uniformly polished by CMP (chemical mechanical polishing) polishing or NC milling. Next, referring to FIG. 5E, a PID material 40 is further laminated and a series of image processes such as photography, development, and etching are performed. At this time, the PID material of the numeral 40 can use a low resolution PID material having a lower resolution than the PID material of the numeral 20.

Referring to FIG. 5F, electroless copper plating 60 is performed on the entire surface of the PID material 50 through Permaganate Treatment. Referring to FIG. 5G, the dry film 70 is closely contacted and a series of image processes such as photo, development, etching, and the like are performed to transfer the pattern onto the dry film 70.

Referring to FIG. 5G, electroplating is performed using the dry film 70 as a plating mask, and copper (Cu) is filled on the exposed surface of the electroless plated layer 60 to form a copper plating layer 80.

Referring to FIG. 5H, the dry film 70 is peeled off and the electroless plated layer 60 is removed by hot etching or quick etching. The circuit can then be fabricated using conventional SAP or MSAP processes.

Referring to FIG. 5i, a build-up material 90 such as a low-resolution PID material, ABF, may be used to follow the SAP (Semi-additive Process) process. Referring to FIG. 5K instead of the process of FIG. 5J, a modified semi-additive process (MSAP) process may be performed by using the same material as that of the conventional RCC or by laminating the prepreg 100 and the copper foil 110.

The foregoing has somewhat improved the features and technical advantages of the present invention in order to better understand the claims of the invention described below. Additional features and advantages that constitute the claims of the present invention will be described in detail below. It should be appreciated by those skilled in the art that the disclosed concepts and specific embodiments of the invention can be used immediately as a basis for designing or modifying other structures to accomplish the invention and similar purposes.

The inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures to accomplish the same purpose of the present invention. It will be apparent to those skilled in the art that various modifications, substitutions and alterations can be made hereto without departing from the spirit or scope of the invention as defined in the appended claims.

The present invention is applicable to wafer level package products. The present invention is advantageous in that it is not necessary to use an expensive process because it is not necessary to form a seed layer by a sputtering method for selective electrolytic copper plating. The present invention has the advantage of simultaneously performing an image process and a lamination process for pattern transfer using a PID material.

Since the present invention forms a copper plating on not only the front surface but also the side surface of the plated layer (PID material) formed by the width and the interval of the fine pitch, the adhesion is excellent and the problem of pattern lift, which is often caused in fine pitch circuits, is originally solved. Further, since the present invention can omit the subsequent etch process, it is possible to avoid etch damage caused during the etching process.

Claims (5)

A method for manufacturing a circuit board,
(a) depositing a first PID material on a first copper foil, placing a first photomask, exposing and developing the first copper mask, and transferring a circuit pattern of the first photomask to the first PID material;
(b) modifying the surface of the first PID material exposed to ultraviolet rays to hydrophilicity by irradiating ultraviolet light by placing a first photomask on the first PID material;
(c) forming a seed layer only on the surface-modified region and the exposed copper foil through NaOH treatment, palladium catalyst treatment, reducing agent treatment, ultrasonic treatment, electroless plating solution treatment, and the like; And
(d) forming a copper plating trace by transferring a circuit pattern of the first photomask by performing electrolytic copper plating to form a copper plating layer on the seed layer;
Wherein the first PID material is a PID material characterized in that the carbon bond is converted into a carboxyl group or a hydroxyl group to be hydrophilic when exposed to ultraviolet rays. The method for manufacturing a circuit board according to claim 1, wherein the first copper foil is an outer layer copper foil of the decoratable core. delete The method of claim 1, further comprising planarizing the surface in a CMP or NC milling manner in addition to the step (d). 2. The method of claim 1, wherein, following step (d)
(e) coating a second PID material, placing a second photomask, exposing and developing, and transferring a circuit pattern of the second photomask to the second PID material; And
(f) forming an electroless copper plating layer on the surface through permanganate treatment, forming a plating mask, performing copper plating, and then performing a half etching process to form a copper foil circuit of the outer layer
Wherein the method comprises the steps of:

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