JP2007150171A - Manufacturing method for wiring board - Google Patents

Manufacturing method for wiring board Download PDF

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JP2007150171A
JP2007150171A JP2005345565A JP2005345565A JP2007150171A JP 2007150171 A JP2007150171 A JP 2007150171A JP 2005345565 A JP2005345565 A JP 2005345565A JP 2005345565 A JP2005345565 A JP 2005345565A JP 2007150171 A JP2007150171 A JP 2007150171A
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wiring board
adhesive layer
layer
adhesive
wiring
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Masaharu Yasuda
正治 安田
Hiroichi Yamada
博一 山田
Naoki Miyoshi
直樹 三好
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Kyocera SLC Technologies Corp
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Kyocera SLC Technologies Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for wiring board that can efficiently manufacture a thin wiring board with high density. <P>SOLUTION: The manufacturing method for wiring board includes the stages of preparing a base substrate 1, which has a flat main surface; forming an adhesive layer 2 whose adhesive strength is lost or decreased by irradiation with ultraviolet rays on the main surface of the base substrate 1; forming a laminate 10 for wiring board which comprises conductor layers 3, 5a, 5b, 5c, and 5d and insulating layers 4a, 6a, 6b, 6c, and 4b, by alternately laminating pluralities of conductor layers 3, 5a, 5b, 5c, and 5d and insulating layers 4a, 6a, 6b, 6c, and 4b on the adhesive layer 2; irradiating the adhesive layer 2 with ultraviolet rays to lose or decrease the adhesive strength of the adhesive layer 2; and peeling the laminate 10 off the adhesive layer 2 whose adhesive strength is lost or reduced. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体素子等の電子部品を搭載するために用いられる配線基板の製造方法に関するものである。   The present invention relates to a method for manufacturing a wiring board used for mounting electronic components such as semiconductor elements.

従来、半導体素子等の電子部品を搭載するために用いられる高密度多層配線基板として、厚みが0.2〜2.0mm程度のガラス−樹脂板の両面に銅箔から成る配線導体を有するコア基板の前記両面にそれぞれの厚みが10〜100μm程度の樹脂から成る絶縁層とめっき膜から成る配線導体とを交互に積層して成るビルドアップ配線基板が知られている。このようなビルドアップ配線基板は、例えば次に述べる方法により製作される。   Conventionally, a core substrate having wiring conductors made of copper foil on both surfaces of a glass-resin plate having a thickness of about 0.2 to 2.0 mm as a high-density multilayer wiring substrate used for mounting electronic components such as semiconductor elements There is known a build-up wiring board in which insulating layers made of a resin having a thickness of about 10 to 100 μm and wiring conductors made of a plating film are alternately laminated on the both surfaces. Such a build-up wiring board is manufactured, for example, by the method described below.

まず、ガラスクロスにエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させた絶縁シートを準備する。次にこの絶縁シートの両面に銅箔を貼着するとともに絶縁シート中の熱硬化性樹脂を熱硬化させて両面銅張り板を得る。次にこの両面銅張り板にその上下面を貫通するスルーホールを穿孔するとともに前記スルーホール内壁にめっき膜を被着させて上下面の銅箔をスルーホール内のめっき膜で電気的に接続する。次にスルーホール内を樹脂で充填した後、上下面の銅箔を所定パターンにエッチングすることにより、ガラス−樹脂板の両面に銅箔から成る配線導体を有するコア基板を得る。   First, an insulating sheet in which a glass cloth is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin is prepared. Next, copper foil is stuck on both sides of the insulating sheet, and the thermosetting resin in the insulating sheet is thermoset to obtain a double-sided copper-clad plate. Next, a through-hole penetrating the upper and lower surfaces of the double-sided copper-clad plate is drilled, and a plating film is deposited on the inner wall of the through-hole to electrically connect the upper and lower copper foils with the plating film in the through-hole. . Next, after filling the through hole with resin, the upper and lower copper foils are etched into a predetermined pattern to obtain a core substrate having wiring conductors made of copper foil on both surfaces of the glass-resin plate.

次に、このコア基板の上下面にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂に無機絶縁性フィラーを分散させた樹脂フィルムを貼着するとともに樹脂フィルム中の熱硬化性樹脂を熱硬化させて絶縁層を形成する。次に前記絶縁層にレーザ加工によりビアホールを穿孔するとともにビアホール内を含む絶縁層の表面にセミアディティブ法によりめっき膜から成る配線導体を上下面同時に形成する。そしてさらに、次層の絶縁層や配線導体の形成を複数回繰り返すことによりガラス−樹脂板の両面に銅箔から成る配線導体を有するコア基板の両面に樹脂から成る絶縁層とめっき膜から成る配線導体とを交互に積層して成るビルドアップ配線基板が製作される。   Next, a resin film in which an inorganic insulating filler is dispersed in a thermosetting resin such as epoxy resin or bismaleimide triazine resin is attached to the upper and lower surfaces of the core substrate, and the thermosetting resin in the resin film is thermoset. To form an insulating layer. Next, via holes are drilled in the insulating layer by laser processing, and wiring conductors made of plating films are simultaneously formed on the surface of the insulating layer including the inside of the via holes by a semi-additive method. In addition, by repeating the formation of the next insulating layer and the wiring conductor a plurality of times, the wiring made of the insulating layer and the plating film made of resin on both sides of the core substrate having the wiring conductor made of copper foil on both sides of the glass-resin plate A build-up wiring board formed by alternately laminating conductors is manufactured.

しかしながら、このようなビルドアップ配線基板は、コア基板の両面に樹脂から成る絶縁層とめっき膜から成る配線導体とを交互に積層することから、これらの絶縁層と配線導体とを順次多層化することにより高密度配線が可能であるものの、コア基板として厚みが0.2〜2.0mm程度のガラス−樹脂板を使用することから、配線基板の全体厚みを薄くすることが困難であるという問題点があった。   However, in such a build-up wiring board, since insulating layers made of a resin and wiring conductors made of a plating film are alternately laminated on both surfaces of the core board, the insulating layers and the wiring conductors are sequentially multilayered. Although high-density wiring is possible by using a glass-resin plate having a thickness of about 0.2 to 2.0 mm as the core substrate, it is difficult to reduce the overall thickness of the wiring substrate. There was a point.

そこで、特許文献1には、金属板の一面側に配線導体と絶縁層とを、半導体素子搭載面側から外部接続端子装着面側に向けて順次多層に形成した後、前記金属板をエッチング除去することにより半導体装置用の多層基板を製造する方法が提案されている。この特許文献1に示された方法によれば、半導体素子搭載面が平坦であり、且つ薄型の半導体装置用の多層基板を提供できるとしている。しかしながら、この方法によると、比較的厚みを必要とする金属板をエッチング除去することが必要であり、そのエッチングに長時間を要する。また、金属板をエッチング除去することが必要であることから、金属板の両面に基板を形成することができず、そのため生産効率が低いという解決すべき問題点があった。
特許第3635219号公報
Therefore, in Patent Document 1, a wiring conductor and an insulating layer are sequentially formed on one surface side of a metal plate from the semiconductor element mounting surface side to the external connection terminal mounting surface side, and then the metal plate is etched away. Thus, a method of manufacturing a multilayer substrate for a semiconductor device has been proposed. According to the method disclosed in Patent Document 1, a semiconductor device mounting surface is flat and a thin multilayer substrate for a semiconductor device can be provided. However, according to this method, it is necessary to etch away a metal plate that requires a relatively large thickness, and the etching takes a long time. Further, since it is necessary to remove the metal plate by etching, it is not possible to form the substrate on both surfaces of the metal plate, and there is a problem to be solved that the production efficiency is low.
Japanese Patent No. 3635219

本発明の課題は、薄型で高密度な配線基板を効率よく製造することが可能な配線基板の製造方法を提供することにある。   The subject of this invention is providing the manufacturing method of the wiring board which can manufacture a thin and high-density wiring board efficiently.

本発明の配線基板の製造方法は、平坦な主面を有する支持基板を準備する工程と、前記支持基板の前記主面上に、紫外線の照射により接着力が消失または低下する接着剤層を被着する工程と、前記接着剤層上に導体層と絶縁層とを交互に複数積層して前記導体層と前記絶縁層とから成る配線基板用の積層体を形成する工程と、前記接着剤層に紫外線を照射して該接着剤層の接着力を消失または低下させる工程と、前記積層体を接着力が消失また低下した前記接着剤層より剥離する工程とを具備することを特徴とするものである。   The method for manufacturing a wiring board according to the present invention includes a step of preparing a support substrate having a flat main surface, and an adhesive layer on which the adhesive force disappears or decreases due to ultraviolet irradiation on the main surface of the support substrate. A step of attaching, a step of alternately laminating a plurality of conductor layers and insulating layers on the adhesive layer to form a laminate for the wiring board comprising the conductor layer and the insulating layer, and the adhesive layer And irradiating the substrate with ultraviolet rays to lose or reduce the adhesive strength of the adhesive layer, and peeling the laminate from the adhesive layer with lost or reduced adhesive strength. It is.

本発明の配線基板の製造方法によれば、支持基板の主面上に紫外線の照射により接着力が消失または低下する接着剤層を被着させた後、該接着剤層上に配線導体層と絶縁層とを交互に複数層積層して前記配線導体層と前記絶縁層とから成る配線基板用の積層体を形成し、しかる後、前記接着剤層に紫外線を照射してその接着力を消失または低下させた後、該接着剤層から前記積層体を剥離することから、紫外線の照射のみで短時間かつ簡単に配線基板用の積層体を分離でき、それにより薄型で高密度な配線基板を効率よく製造することができる。また、支持基板の両主面にそれぞれ前記接着剤層と前記積層体とを形成した後、支持基板の横方向から前記接着剤層に紫外線を照射して該接着剤層の接着力を消失または低下させた後、両主面の積層体を分離することが可能であり、この場合、前記積層体の生産効率を約2倍とすることができる。   According to the method for manufacturing a wiring board of the present invention, an adhesive layer whose adhesive strength is lost or reduced by irradiation of ultraviolet rays is deposited on the main surface of the support substrate, and then the wiring conductor layer and the adhesive layer are formed on the adhesive layer. A plurality of insulating layers are alternately laminated to form a laminated body for a wiring board composed of the wiring conductor layer and the insulating layer, and then the adhesive layer loses its adhesive strength by irradiating the adhesive layer with ultraviolet rays. Alternatively, after being lowered, the laminate is peeled off from the adhesive layer, so that the laminate for a wiring board can be easily separated in a short time only by irradiation with ultraviolet rays, thereby forming a thin and high-density wiring board. It can be manufactured efficiently. Further, after forming the adhesive layer and the laminate on both main surfaces of the support substrate, respectively, the adhesive layer is irradiated with ultraviolet rays from the lateral direction of the support substrate to lose the adhesive force of the adhesive layer or After the reduction, it is possible to separate the laminates on both main surfaces, and in this case, the production efficiency of the laminate can be doubled.

次に、本発明における配線基板の製造方法の一例について、図面を参照して詳細に説明する。図1〜図4は、本発明の配線基板の製造方法を説明するための工程毎の概略図である。これらのうち、図1および図2は、支持基板の主面上に接着剤層を被着し、その上に絶縁層と配線導体とを交互に積層して配線基板用の積層体を形成する工程を示す概略図であり、図3は、支持基板上の接着剤層から配線基板用の積層体を剥離する工程を示す概略図であり、図4は剥離した配線基板用の積層体に更に加工を施して形成した配線基板を示す概略断面図である。   Next, an example of a method for manufacturing a wiring board in the present invention will be described in detail with reference to the drawings. 1 to 4 are schematic views for each process for explaining a method of manufacturing a wiring board according to the present invention. Among these, in FIGS. 1 and 2, an adhesive layer is deposited on the main surface of the support substrate, and insulating layers and wiring conductors are alternately stacked thereon to form a laminate for the wiring substrate. FIG. 3 is a schematic diagram showing a process, and FIG. 3 is a schematic diagram showing a process of peeling a laminate for a wiring board from an adhesive layer on a support substrate. FIG. It is a schematic sectional drawing which shows the wiring board formed by giving a process.

まず、図1(a)に示すように、平坦な主面を有する支持基板1を準備する。支持基板1は、紫外線を透過可能ガラスやセラミックス、硬質樹脂等の硬質透光性材料から成る厚みが5〜10mm程度で1辺の長さが300〜1000mm程度の略四角平板であり、その主面上に後述する配線基板用の積層体10を仮支持するための仮支持体として機能する。   First, as shown in FIG. 1A, a support substrate 1 having a flat main surface is prepared. The support substrate 1 is a substantially rectangular flat plate having a thickness of about 5 to 10 mm and a side length of about 300 to 1000 mm made of a hard light-transmitting material such as glass, ceramics, or hard resin that can transmit ultraviolet rays. It functions as a temporary support for temporarily supporting a laminate 10 for a wiring board to be described later on the surface.

次に、図1(b)に示すように、支持基板1の一方の主面に紫外線の照射によりその接着力が消失または低下する接着剤層2を被着する。接着剤層2は、アクリル系粘着ポリマー(例えば、アクリル酸2−エチルヘキシルおよびアクリル酸)、紫外線硬化型オリゴマー(例えばウレタンアクリエートオリゴマー)、光開始剤(例えば1−ヒドロキシシクロヘキシルフェニルケトンなどを含有させた接着性樹脂材料から成り、前記接着性樹脂材料のペーストを支持基板1の主面に塗布した後乾燥させる、または前記接着性樹脂材料のフィルムを支持基板1の主面に貼着することにより被着される。そしてこの接着剤層2は、紫外線が照射されると、光開始剤から紫外線硬化型オリゴマーへのラジカル反応が開始する。このラジカルがオリゴマーに作用し、紫外線硬化型オリゴマーが重合する。この結果接着力が消失または低下する。   Next, as shown in FIG. 1 (b), an adhesive layer 2 whose adhesive strength disappears or decreases when irradiated with ultraviolet rays is applied to one main surface of the support substrate 1. The adhesive layer 2 contains an acrylic adhesive polymer (for example, 2-ethylhexyl acrylate and acrylic acid), an ultraviolet curable oligomer (for example, urethane acrylate oligomer), a photoinitiator (for example, 1-hydroxycyclohexyl phenyl ketone), and the like. The adhesive resin material paste is applied to the main surface of the support substrate 1 and then dried, or the film of the adhesive resin material is adhered to the main surface of the support substrate 1. When the adhesive layer 2 is irradiated with ultraviolet rays, a radical reaction from the photoinitiator to the ultraviolet curable oligomer starts, which acts on the oligomer, and the ultraviolet curable oligomer is polymerized. As a result, the adhesive strength disappears or decreases.

次に、図1(c)に示すように、接着剤層2の表面に補助導体層3を積層する。補助導体層3は、例えば厚みが3〜20μm程度の金属箔から成り、後述する配線基板用の積層体10を接着剤層2から剥離する際にその剥離を容易とするための境界層として機能する。なお、補助導体層3の片面に接着剤層2を予め被着させておき、その接着剤層2を支持基板1の主面に貼着することにより接着剤層2と補助導体層3とを支持基板1の主面に同時に積層してもよい。   Next, as shown in FIG. 1C, the auxiliary conductor layer 3 is laminated on the surface of the adhesive layer 2. The auxiliary conductor layer 3 is made of, for example, a metal foil having a thickness of about 3 to 20 μm, and functions as a boundary layer for facilitating the peeling when the laminate 10 for a wiring board described later is peeled from the adhesive layer 2. To do. In addition, the adhesive layer 2 is previously applied to one side of the auxiliary conductor layer 3, and the adhesive layer 2 and the auxiliary conductor layer 3 are bonded by attaching the adhesive layer 2 to the main surface of the support substrate 1. You may laminate | stack on the main surface of the support substrate 1 simultaneously.

次に、図1(d)に示すように、補助導体層3上にソルダーレジスト層用の第1の絶縁層4aを積層する。第1の絶縁層4aは、例えばアクリル変性エポキシ樹脂にシリカやタルク等の無機物粉末フィラーを30〜70質量%程度分散させた電気絶縁材料から成り、アクリル変性エポキシ樹脂等の感光性樹脂と光重合開始剤等とからなる混合物にシリカやタルク等の無機絶縁性フィラーを含有させた感光性樹脂ペーストを、スクリーン印刷やロールコート法により10〜30μm程度の厚みに塗布し、しかる後、フォトリソグラフィー技術を採用して所定のパターンに露光・現像した後、それを紫外線硬化および熱硬化させることにより形成される。なお、第1の絶縁層4aには、本例の製造方法によって得られる配線基板における半導体素子接続パッドを形成するための開口部Aを形成しておく。   Next, as shown in FIG. 1D, the first insulating layer 4 a for the solder resist layer is laminated on the auxiliary conductor layer 3. The first insulating layer 4a is made of, for example, an electrically insulating material in which an inorganic powder filler such as silica or talc is dispersed in an acrylic modified epoxy resin by about 30 to 70% by mass, and is photopolymerized with a photosensitive resin such as an acrylic modified epoxy resin. A photosensitive resin paste containing an inorganic insulating filler such as silica or talc in a mixture composed of an initiator and the like is applied to a thickness of about 10 to 30 μm by screen printing or a roll coating method, and then photolithography technology After being exposed to light and developed in a predetermined pattern using UV, it is formed by ultraviolet curing and heat curing. Note that an opening A for forming a semiconductor element connection pad in the wiring substrate obtained by the manufacturing method of this example is formed in the first insulating layer 4a.

次に、図2(a)に示すように、第1の絶縁層4aの表面および開口部A内に第1の配線導体層5aを所定のパターンに形成する。第1の配線導体層5aは、例えば無電解銅めっき膜および電解銅めっき膜から成り、周知のセミアディティブ法によって形成される。具体的には、先ず、第1の絶縁層4aの表面を必要に応じて粗化し、次にその表面に無電解銅めっき膜を0.1〜2.0μm程度の厚みに被着させる。次に前記無電解銅めっき膜の表面に第1の配線導体層5aに対応した開口部を有するめっきレジスト層を形成する。なお、前記めっきレジスト層は、感光性の樹脂フィルムを前記無電解銅めっき膜上に貼着するとともにその樹脂フィルムにフォトリソグラフィー技術を採用して露光・現像処理を施すことにより前記開口部を有するように形成される。次に、めっきレジスト層の開口部内に露出する前記無電解銅めっき膜上に電解銅めっき膜を5〜30μm程度の厚みに被着させる。次に、めっきレジスト層を剥離する。最後に、前記無電解銅めっき膜および電解銅めっき膜の露出部を電解銅めっき膜間の無電解銅めっき膜が消失するまで全体的にエッチングして第1の配線導体層5aを形成する。   Next, as shown in FIG. 2A, a first wiring conductor layer 5a is formed in a predetermined pattern on the surface of the first insulating layer 4a and in the opening A. The first wiring conductor layer 5a is made of, for example, an electroless copper plating film and an electrolytic copper plating film, and is formed by a known semi-additive method. Specifically, first, the surface of the first insulating layer 4a is roughened as necessary, and then an electroless copper plating film is deposited on the surface to a thickness of about 0.1 to 2.0 μm. Next, a plating resist layer having an opening corresponding to the first wiring conductor layer 5a is formed on the surface of the electroless copper plating film. The plating resist layer has the opening by sticking a photosensitive resin film on the electroless copper plating film and subjecting the resin film to exposure / development processing using a photolithography technique. Formed as follows. Next, the electrolytic copper plating film is deposited to a thickness of about 5 to 30 μm on the electroless copper plating film exposed in the opening of the plating resist layer. Next, the plating resist layer is peeled off. Finally, the first wiring conductor layer 5a is formed by etching the electroless copper plating film and the exposed portions of the electrolytic copper plating film as a whole until the electroless copper plating film between the electrolytic copper plating films disappears.

次に、図2(b)に示すように、第1の絶縁層4aおよび第1の配線導体層5aの上に配線導体層間絶縁用の第2の絶縁層6aを形成する。第2の絶縁層6aは、例えばエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂に無機絶縁性フィラーを分散させた電気絶縁材料から成り、エポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂の未硬化物に無機絶縁性フィラーを分散させた厚みが10〜100μm程度の樹脂フィルムを第1の絶縁層4aおよび第1の配線導体層5a上に貼着するとともにその樹脂フィルム中の熱硬化性樹脂を熱硬化させることにより形成される。なお、第2の絶縁層6aには、第1の配線導体層5aの一部を露出させるビア用の開口部Vを形成しておく。開口部Vは、レーザ加工により形成する。または第2の樹脂層6a用のフィルムに感光性を持たせておき、それにフォトリソグラフィー技術を採用して露光・現像処理を施すことにより形成する。   Next, as shown in FIG. 2B, a second insulating layer 6a for wiring conductor interlayer insulation is formed on the first insulating layer 4a and the first wiring conductor layer 5a. The second insulating layer 6a is made of an electrically insulating material in which an inorganic insulating filler is dispersed in a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin, and the thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. A resin film having a thickness of about 10 to 100 μm, in which an inorganic insulating filler is dispersed in an uncured material, is pasted on the first insulating layer 4a and the first wiring conductor layer 5a, and thermosetting in the resin film is performed. It is formed by thermosetting a functional resin. A via opening V for exposing a part of the first wiring conductor layer 5a is formed in the second insulating layer 6a. The opening V is formed by laser processing. Alternatively, the film for the second resin layer 6a is provided with photosensitivity, and is formed by applying exposure / development processing using a photolithography technique.

引き続き、図2(c)に示すように、第2の絶縁層6a上に第2の配線導体層5bを、その上に第3の絶縁層6bを、さらにその上に第4の配線導体層5c、第4の絶縁層6c、第5の配線導体層5d、第5の絶縁層4bを順次形成して配線基板用の積層体10を形成する。なお、第2〜第5の配線導体層5b〜5dは、第1の配線導体層5aと同様の無電解銅めっき膜および電解銅めっき膜から成り、第1の配線導体層5aと同様のセミアディティブ法によって形成される。また、第3および第4の絶縁層6b、6cは、第2の絶縁層6aと同様の電気絶縁材料から成り、第2の絶縁層6aと同様の方法により形成される。さらに、第5の絶縁層4bは、第1の絶縁層4aと同様の電気絶縁材料から成り、第1の絶縁層4aと同様の方法により形成される。   Subsequently, as shown in FIG. 2C, the second wiring conductor layer 5b is formed on the second insulating layer 6a, the third insulating layer 6b is formed thereon, and the fourth wiring conductor layer is formed thereon. 5c, the fourth insulating layer 6c, the fifth wiring conductor layer 5d, and the fifth insulating layer 4b are sequentially formed to form the multilayer body 10 for the wiring board. The second to fifth wiring conductor layers 5b to 5d are composed of an electroless copper plating film and an electrolytic copper plating film similar to the first wiring conductor layer 5a, and are similar to the first wiring conductor layer 5a. It is formed by the additive method. The third and fourth insulating layers 6b and 6c are made of the same electrical insulating material as the second insulating layer 6a and are formed by the same method as the second insulating layer 6a. Furthermore, the fifth insulating layer 4b is made of the same electrical insulating material as that of the first insulating layer 4a, and is formed by the same method as that for the first insulating layer 4a.

次に、図3(a)に示すように、支持基板1を透して接着剤層2に紫外線を照射し、接着剤層2の接着力を消失または低下させる。   Next, as shown in FIG. 3A, the adhesive layer 2 is irradiated with ultraviolet rays through the support substrate 1, and the adhesive strength of the adhesive layer 2 is lost or reduced.

次に、図3(b)に示すように、配線基板用の積層体10を接着力が消失また低下した接着剤層2から剥離する。このとき、接着剤層2は紫外線の照射によりその接着力が消失または低下しているので、配線基板用の積層体10を接着剤層2から短時間の間に容易に剥離することができる。   Next, as shown in FIG. 3B, the laminate 10 for a wiring board is peeled off from the adhesive layer 2 whose adhesive strength has been lost or reduced. At this time, since the adhesive strength of the adhesive layer 2 disappears or decreases due to the irradiation of ultraviolet rays, the laminate 10 for a wiring board can be easily peeled from the adhesive layer 2 in a short time.

次に図4に示すように、配線基板用の積層体10から補助導体層3をエッチング除去することにより配線基板20が完成する。なお、このとき、補助導体層3はその厚みが3〜20μm程度と薄いので、短時間でエッチング除去することができる。   Next, as shown in FIG. 4, the auxiliary conductor layer 3 is removed by etching from the laminate 10 for the wiring board, thereby completing the wiring board 20. At this time, since the auxiliary conductor layer 3 is as thin as about 3 to 20 μm, it can be removed by etching in a short time.

なお、上述の例では支持基板1の一方の主面に配線基板用の積層体10を形成した場合について説明したが、図5に示すように、支持基板1の両方の主面に配線基板用の積層体10を形成してもよい。この場合、支持基板1の一方の主面のみに積層体10を形成する場合と比較して積層体10を形成する効率を約2倍に高めることができる。なお、この場合、支持基板1の側面から紫外線を照射することにより接着剤層2の接着力を消失または低下させる。   In the above-described example, the case where the laminated body 10 for the wiring board is formed on one main surface of the support substrate 1 has been described. However, as shown in FIG. The laminated body 10 may be formed. In this case, compared with the case where the laminated body 10 is formed only on one main surface of the support substrate 1, the efficiency of forming the laminated body 10 can be increased approximately twice. In this case, the adhesive force of the adhesive layer 2 is lost or reduced by irradiating ultraviolet rays from the side surface of the support substrate 1.

かくして本発明の配線基板の製造方法によれば、薄型で高密度な配線基板を効率よく製造することができる。なお、本発明は、上述の実施の形態例に限定されるものではなく、の本発明の要旨を逸脱しない範囲であれば、種々の変更が可能であることは言うまでもない。   Thus, according to the method for manufacturing a wiring board of the present invention, a thin and high-density wiring board can be efficiently manufactured. Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention.

本発明の配線基板の製造方法を説明するための概略断面図である。It is a schematic sectional drawing for demonstrating the manufacturing method of the wiring board of this invention. 本発明の配線基板の製造方法を説明するための概略断面図である。It is a schematic sectional drawing for demonstrating the manufacturing method of the wiring board of this invention. 本発明の配線基板の製造方法を説明するための概略断面図である。It is a schematic sectional drawing for demonstrating the manufacturing method of the wiring board of this invention. 本発明の配線基板の製造方法を説明するための概略断面図である。It is a schematic sectional drawing for demonstrating the manufacturing method of the wiring board of this invention. 本発明の配線基板の製造方法を説明するための概略断面図である。It is a schematic sectional drawing for demonstrating the manufacturing method of the wiring board of this invention.

符号の説明Explanation of symbols

1 支持基板
2 接着剤層
3,5a,5b,5c,5d 導体層
4a,4b,6a,6b,6c 絶縁層
10 配線基板用の積層体
20 配線基板
DESCRIPTION OF SYMBOLS 1 Support substrate 2 Adhesive layer 3, 5a, 5b, 5c, 5d Conductive layer 4a, 4b, 6a, 6b, 6c Insulating layer 10 Laminate for wiring boards 20 Wiring board

Claims (1)

平坦な主面を有する支持基板を準備する工程と、前記支持基板の前記主面上に、紫外線の照射により接着力が消失または低下する接着剤層を被着する工程と、前記接着剤層上に導体層と絶縁層とを交互に複数積層して前記導体層と前記絶縁層とから成る配線基板用の積層体を形成する工程と、前記接着剤層に紫外線を照射して該接着剤層の接着力を消失または低下させる工程と、前記積層体を接着力が消失また低下した前記接着剤層より剥離する工程とを具備することを特徴とする配線基板の製造方法。
A step of preparing a support substrate having a flat main surface, a step of depositing an adhesive layer on which the adhesive force disappears or decreases due to irradiation of ultraviolet rays on the main surface of the support substrate, and on the adhesive layer A plurality of conductor layers and insulating layers alternately laminated to form a laminate for a wiring board comprising the conductor layers and the insulating layers, and the adhesive layer is irradiated with ultraviolet rays. A method of manufacturing a wiring board comprising: a step of eliminating or reducing the adhesive strength of the substrate; and a step of peeling the laminate from the adhesive layer where the adhesive strength has been lost or reduced.
JP2005345565A 2005-11-30 2005-11-30 Manufacturing method for wiring board Pending JP2007150171A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009021545A (en) * 2007-07-10 2009-01-29 Samsung Electro Mech Co Ltd Manufacturing method of printed-circuit board
JP2009088469A (en) * 2007-09-28 2009-04-23 Samsung Electro Mech Co Ltd Printed circuit board and manufacturing method of same
JP2010034466A (en) * 2008-07-31 2010-02-12 Kyocer Slc Technologies Corp Method of manufacturing wiring board
JP2011022529A (en) * 2009-07-21 2011-02-03 Mejiro Precision:Kk Light source device and exposure device
JP2016111275A (en) * 2014-12-09 2016-06-20 凸版印刷株式会社 Wiring board and laminate device
JP2016111303A (en) * 2014-12-10 2016-06-20 凸版印刷株式会社 Wiring board, semiconductor device and semiconductor device manufacturing method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009021545A (en) * 2007-07-10 2009-01-29 Samsung Electro Mech Co Ltd Manufacturing method of printed-circuit board
JP2009088469A (en) * 2007-09-28 2009-04-23 Samsung Electro Mech Co Ltd Printed circuit board and manufacturing method of same
JP2010034466A (en) * 2008-07-31 2010-02-12 Kyocer Slc Technologies Corp Method of manufacturing wiring board
JP2011022529A (en) * 2009-07-21 2011-02-03 Mejiro Precision:Kk Light source device and exposure device
JP2016111275A (en) * 2014-12-09 2016-06-20 凸版印刷株式会社 Wiring board and laminate device
JP2016111303A (en) * 2014-12-10 2016-06-20 凸版印刷株式会社 Wiring board, semiconductor device and semiconductor device manufacturing method

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