JP2004265967A - Multilayer printed wiring board, its manufacturing method and semiconductor device - Google Patents

Multilayer printed wiring board, its manufacturing method and semiconductor device Download PDF

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Publication number
JP2004265967A
JP2004265967A JP2003052445A JP2003052445A JP2004265967A JP 2004265967 A JP2004265967 A JP 2004265967A JP 2003052445 A JP2003052445 A JP 2003052445A JP 2003052445 A JP2003052445 A JP 2003052445A JP 2004265967 A JP2004265967 A JP 2004265967A
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Prior art keywords
layer
plating
insulating resin
resist pattern
wiring layer
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JP2003052445A
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JP4066848B2 (en
Inventor
Toshihide Ito
利秀 伊藤
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Kyocera Circuit Solutions Inc
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NEC Toppan Circuit Solutions Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a printed wiring board capable of forming a detailed wiring layer, a multilayer printed wiring board in which warp is hard to be generated, and to provide a semiconductor device. <P>SOLUTION: The multilayer printed wiring board 100 is constituted of a build up layer 20 wherein a second wiring layer 22a and a field via 31 are formed on one surface of a first wiring layer 21a through an insulated resin layer 11, and a build-up layer 30 wherein a third wiring layer 23a and a conformal via 32 are formed on the other surface. The first wiring layer 21a is electrically connected with the second wiring layer 22a by the field via 31. The first wiring layer 21a is electrically connected with the third wiring layer 23a by the conformal via 32. Further, three-layer printed wiring board structure is constituted as symmetrical structure wherein the build-up layer 10 and the build-up layer 20 are formed symmetrically to the first wiring layer 21a. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、第１配線層の両面に絶縁層を介して複数の配線層が形成された多層プリント配線板及びその製造方法並びに半導体装置に関する。
【０００２】
【従来の技術】
近年、半導体実装技術の発展により半導体装置を実装する実装するプリント配線板においては、高密度、高精度の配線層を有する多層プリント配線板が要求されている。高密度、高精度の配線層を形成するために、プリント配線板は多層化され、配線層の線幅も小さくなり、配線層間の接続に用いられるビアホールはより小さい穴径とすることが求められている。そして、ビアホール用孔の孔加工も、位置ずれを極力小さくするように高い精度の加工が求められている。そのような、要求を満足するために、配線層と絶縁層を交互に形成して多層配線層を形成して多層プリント配線板を作製する、所謂ビルドアップ法が実用化されている。
【０００３】
ビルドアップ法にて多層プリント配線板を作製する従来技術（例えば、特許文献１参照）の一例を図７（ａ）〜（ｆ）に示す。
以下、図７（ａ）〜（ｆ）を参照して、ビルドアップ法による多層プリント配線板の製造方法について説明する。
まず、絶縁基材１１１の両面に銅箔１２１及び１２２を積層した両面銅張り積層板７１０を準備する（図７（ａ）参照）。
次に、両面銅張り積層板７１０の銅箔１２２をエッチング法にてパターニング処理を行って第１配線層１２２ａを形成し、絶縁基材１１１の所定位置をレーザー加工等により孔明け加工し、ビア用孔１４１を形成する（図７（ｂ）参照）。
【０００４】
次に、両面に感光性ドライフィルムをラミネートして感光層を形成し、第１配線層１２２ａ側の感光層をパターン露光、現像等の一連のパターニング処理を、銅箔１２１側の感光層は全面露光を行って、めっきレジストパターン１５１及び保護マスク層１５２を形成する。さらに、めっきレジストパターン１５１側の絶縁基材１１１及びビア用孔１４１表面のデスミア、触媒核付与処理及び無電解銅めっきを行って、めっき下地導電層を形成し、該めっき下地導電層をカソードにして電解銅めっきを行い、コンフォーマルビア１３１を形成する（図７（ｃ）参照）。
【０００５】
次に、両面に感光性ドライフィルムをラミネートして感光層を形成し、銅箔１２１側の感光層をパターン露光、現像等の一連のパターニング処理を、第１配線層１２２ａ側の感光層は全面露光を行って、レジストパターン１５３及び保護マスク層１５４を形成する。さらに、レジストパターン１５３をマスクにして銅箔１２１をエッチング処理する（図７（ｄ）参照）。
【０００６】
次に、レジストパターン１５３及び保護マスク層１５４を剥離処理し、絶縁基材１１１の一方の面に配線層１２１ａ、他方の面に配線層１２２ａを形成してコア基板７２０を作製する（図７（ｅ）参照）。
さらに、コア基板７２０の両面にビルドアップ層７３０及び７４０を形成し、４層プリント配線板７００を得る（図７（ｆ）参照）。
【０００７】
また、ビルドアップ法にて多層プリント配線板を作製する従来技術（例えば、特許文献２参照）の別の一例を図８（ａ）〜（ｄ）に示す。
以下、図８（ａ）〜（ｄ）を参照して、ビルドアップ法による多層プリント配線板の製造方法について説明する。
まず、絶縁基材１１４の両面に銅箔１２５及び１２６を積層した両面銅張り積層板８１０を準備する（図８（ａ）参照）。
次に、両面銅張り積層板６１０の銅箔１２６側の所定位置をレーザー加工等により孔明け加工し、ビア用孔１４２を形成する（図８（ｂ）参照）。
【０００８】
次に、銅箔１２５及び銅箔１２６をサブトラクティブ法にてパターニング処理して配線層１２５ａ及び配線層１２６ａ形成する。さらに、セミアディテブ法にて配線層１２６ａ上に配線層１２７を、ビア用孔１４２にビアホール１３４を形成してコア基板８２０を作製する（図８（ｃ）参照）。
【０００９】
次に、コア基板８２０の配線層１２７側に絶縁層１１５を介して、サブトラクティブ法にて配線層１２８を形成する。さらに、セミアディテブ法にて配線層１２９及びビアホール１３５を形成してビルドアップ層８３０を形成し、コア基板８２０及びビルドアップ層８３０からなる３層プリント配線板６００を得る（図８（ｄ）参照）。
【００１０】
【特許文献１】
特開２００１−９４２５２号公報
【特許文献２】
特開平０９−４６０４２号公報
【００１１】
【発明が解決しようとする課題】
上記従来技術を用いたビルドアップ法による多層プリント配線板の製造法では、サブトラクティブ法を用いているので、微細配線層の形成が難しい。
また、特許文献１の技術を用いて作製した多層プリント配線板は、絶縁基材に対して非対称構造になっているので反りを生じ易いと言う問題を有する。
【００１２】
本発明は上記問題点に鑑み考案されたもので、微細配線層の形成が可能な多層プリント配線板の製造方法及び反りを生じ難い多層プリント配線板並びに半導体装置を提供することを目的とする。
【００１３】
【課題を解決するための手段】
本発明に於いて上記課題を達成するために、まず請求項１においては、第１配線層の両面に絶縁樹脂層を介して複数の配線層が形成されていることを特徴とする多層プリント配線板としたものである。
【００１４】
また、請求項２においては、前記第１配線層と前記配線層及び前記配線層間は前記絶縁樹脂層を介してコンフォーマルビアもしくはフィルドビアにて電気的に接続されていることを特徴とする請求項１に記載の多層プリント配線板としたものである。
【００１５】
また、請求項３においては、請求項１または２に記載の多層プリント配線板は対称構造になっていることを特徴とする多層プリント配線板としたものである。
【００１６】
請求項１乃至３のいずれか一項に記載の多層プリント配線板上に半導体を搭載したことを特徴とする半導体装置としたものである
【００１７】
以下の工程を少なくとも備えることを特徴とする請求項１乃至３のいずれか一項に記載の多層プリント配線板の製造方法としたものである。
（ａ）絶縁樹脂層１１及び銅箔２１からなる片面銅箔付樹脂シート１０を準備する工程。
（ｂ）片面銅箔付樹脂シート１０の絶縁樹脂層１１の所定位置にビア用孔４１を形成し、デスミア、めっき触媒付与及び無電解銅めっきを行って、めっき下地導電層を形成する工程。
（ｃ）銅箔２１上に支持体シート６１を貼着した後めっき下地導電層上に感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってめっきレジストパターン５１を形成する工程。
（ｄ）めっき下地導電層をカソードにして電解銅めっきを行って所定厚の導体層２２及びフィルドビア３１を形成する工程。
（ｅ）レジストパターン５１を剥離処理し、めっきレジストパターン５１下部にあっためっき下地導電層をフラッシュエッチングにて除去し、第２配線層２２ａ及びフィルドビア３１を形成し、支持体シート６１を除去する工程。
（ｆ）第２配線層２２ａ側に支持体シート６２を貼着した後銅箔２１上に感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってレジストパターン５２を形成する工程。
（ｇ）レジストパターン５２をマスクにして銅箔２１をエッチング処理し、レジストパターン５２を剥離処理して、第１配線層２１ａを形成する工程。
（ｈ）第１配線層２１ａ側に所定厚の絶縁樹脂層１２を形成し、絶縁樹脂層１２の所定位置にレーザー加工等によりビア用孔４２を形成し、デスミア、めっき触媒付与及び無電解銅めっきを行って、めっき下地導電層を形成する工程。
（ｉ）絶縁樹脂層１２側に感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってめっきレジストパターン５３を形成する工程。
（ｊ）めっき下地導電層をカソードにして電解銅めっきを行い、所定厚の導体層２３及びコンフォーマルビア３２を形成する工程。
（ｋ）レジストパターン５３を剥離処理し、めっきレジストパターン５３下部にあっためっき下地導電層をフラッシュエッチングにて除去し、第３配線層２３ａ及びコンフォーマルビア３２を形成し、支持体シート６２を除去する工程。
（ｌ）上記絶縁樹脂層、配線層及びコンフォーマルビアもしくはフィルドビア形成工程を必要回数繰り返す工程。
【００１８】
以下の工程を少なくとも備えることを特徴とする請求項１乃至３のいずれか一項に記載の多層プリント配線板の製造方法としたものである。
（ａ）絶縁樹脂層１１及び銅箔２１からなる片面銅箔付樹脂シート１０を準備する工程。
（ｂ）絶縁樹脂層１１の所定位置にビア用孔４１を形成し、デスミア、めっき触媒付与及び無電解銅めっきを行って、めっき下地導電層を形成する工程。
（ｃ）銅箔２１上に支持体シート６１を貼着した後めっき下地導電層上に感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってめっきレジストパターン５１を形成する工程。
（ｄ）めっき下地導電層をカソードにして電解銅めっきを行い、所定厚の導体層２２及びフィルドビア３１を形成する工程。
（ｅ）めっきレジストパターン５１を剥離処理し、めっきレジストパターン５１下部にあっためっき下地導電層をフラッシュエッチングにて除去し、第２配線層２２ａ及びフィルドビア３１を形成し、支持体シート６１を除去する工程。
（ｆ）第２配線層２２ａ側に支持体シート６２を貼着した後銅箔２１上に感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってレジストパターン５２を形成する工程。
（ｇ）レジストパターン５２をマスクにして銅箔２１をエッチング処理し、レジストパターン５２を除去して第１配線層２１ａを形成し、支持体シート６２を除去する工程。
（ｈ）第１配線層２１ａ及び第２配線層２２ａ側にそれぞれ所定厚の絶縁樹脂層１３及び絶縁樹脂層１４を形成し、絶縁樹脂層１３及び絶縁樹脂層１４の所定位置にレーザー加工等によりそれぞれビア用孔４３及びビア用孔４４を形成し、デスミア、めっき触媒付与及び無電解銅めっきを行って、めっき下地導電層をそれぞれ形成する工程。
（ｉ）絶縁樹脂層１３及び絶縁樹脂層１４側にそれぞれ感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってめっきレジストパターン５４及びめっきレジストパターン５５を形成する工程。
（ｊ）めっき下地導電層をカソードにして電解銅めっきを行い、所定厚の導体層２４及びコンフォーマルビア３３、導体層２５及びフィルドビア３４をそれぞれ形成する工程。
（ｋ）めっきレジストパターン５４及５５を剥離処理し、めっきレジストパターン５４及び５５下部にあっためっき下地導電層をフラッシュエッチングにて除去し、第３配線層２４ａ及びコンフォーマルビア３３、第４配線層２５ａ及びフィルドビア３４を形成する工程。
（ｌ）上記絶縁樹脂層、配線層及びコンフォーマルビアもしくはフィルドビア形成工程を必要回数繰り返す工程。
【００１９】
前記支持体シートがポリエステルフィルム、ポリイミドフィルム、アミドフィルム、ポリプロピレンフィルムのいずれかで形成されていることを特徴とする請求項５または６に記載の多層プリント配線板の製造方法としたものである。
【００２０】
【発明の実施の形態】
以下本発明の実施の形態につき説明する。
本発明の多層プリント配線板の一実施例を図１（ａ）、（ｂ）及び（ｃ）に示す。また、本発明の多層プリント配線板に半導体を搭載した半導体装置の一実施例を図２（ａ）〜（ｄ）に示す。
本発明の多層プリント配線板１００は、図１（ａ）に示すように、第１配線層２１ａの一方の面に絶縁樹脂層１１を介して第２配線層２２ａ及びフィルドビア３１が形成されたビルドアップ層２０と、他方の面に第３配線層２３ａ及びコンフォーマルビア３２が形成されたビルドアップ層３０とで構成されており、第１配線層２１ａと第２配線層２２ａとはフィルドビア３１で、また第１配線層２１ａと第３配線層２３ａとはコンフォーマルビア３２で、それぞれ電気的に接続されている。第１配線層２１ａに対してビルドアップ層２０及びビルドアップ層３０が対称に形成された対称構造の３層プリント配線板構造になっている。
【００２１】
本発明の多層プリント配線板１００ａは、図１（ｂ）に示すように、第１配線層２１ａの一方の面に絶縁樹脂層１１を介して第２配線層２２ａ、コンフォーマルビアランド２２ｂ及びコンフォーマルビア３１ａが形成されたビルドアップ層２０ａと、他方の面に第３配線層２３ａ及びコンフォーマルビア３２が形成されたビルドアップ層３０とで構成されており、第１配線層２１ａと第２配線層２２ａとはコンフォーマルビア３１ａで、また第１配線層２１ａと第３配線層２３ａとはコンフォーマルビア３２で、それぞれ電気的に接続されている。さらに、第１配線層２１ａに対してビルドアップ層２０ａ及びビルドアップ層３０が対称に形成された対称構造の３層プリント配線板構造になっている。
【００２２】
また、本発明の多層プリント配線板２００は、図１（ｃ）に示すように、絶縁樹脂層１１の両面に第１配線層２１ａ、第２配線層２２ａ及びフィルドビア３１が形成された両面配線板４０と、両面配線板４０の一方の面に絶縁樹脂層１３を介して第３配線層２４ａ及びコンフォーマルビア３３が形成されたビルドアップ層５０と、他方の面に絶縁層１４を介して第４配線層２５ａ、ランド２５ｂ及びフィルドビア３４が形成されたビルドアップ層６０とで構成されており、第１配線層２１ａと第２配線層２２ａとはフィルドビア３１で、第１配線層２１ａと第３配線層２４ａとはコンフォーマルビア３３で、第２配線層２２ａと第４配線層２５ａとはフィルドビア３４で、それぞれ電気的に接続されている。さらに、絶縁樹脂層１１に対してビルドアップ層５０及びビルドアップ層６０が対称に形成された対称構造の４層プリント配線板構造になっている。
【００２３】
上記本発明の多層プリント配線板１００、１００ａ及び２００は、コア基板のないビルドアップ多層プリント配線板の構造とすることで、コア基板のＢＶＨ（ブラインドビアホール）による配線制約を取り除くことができるとともに、高密度化と薄型化が図れる。
具体的には、配線層のパターン設計自由度が増すとともに、配線層の収容性が向上し、薄型化及び微細配線層の形成が可能になり、高密度化が図れる。
また、対称構造のビルドアップ多層プリント配線板となっているため、薄型化しても配線板の反りが生じ難い。
【００２４】
以下、本発明の半導体装置について説明する。
本発明の半導体装置３００は、図２（ａ）に示すように、本発明の多層プリント配線板１００上のフィルドビアと半導体８０のパッド７１が接合されて半導体８０が搭載されており、半導体８０と多層プリント配線板１００の絶縁樹脂層との間にはアンダーフィル８１樹脂を流し込んだ構造としている。
また、本発明の半導体装置４００は、図２（ｂ）に示すように、本発明の多層プリント配線板１００ａ上のコンフォーマルビアランドと半導体８０のパッド７１が接合されて半導体８０が搭載されており、半導体８０と多層プリント配線板１００ａの絶縁樹脂層との間にはアンダーフィル８１樹脂を流し込んだ構造としている。
【００２５】
本発明の半導体装置５００は、図２（ｃ）に示すように、本発明の多層プリント配線板２００上のフィルドビアまたランドと半導体８０のパッド７１が半田９１を介して接合されて半導体８０が搭載されており、半導体８０と多層プリント配線板２００の絶縁樹脂層との間にはアンダーフィル８１樹脂を流し込んだ構造としている。
また、本発明の半導体装置６００は、図２（ｄ）に示すように、本発明の多層プリント配線板２００上のフィルドビア３４またはランド２５ｂと半導体８０のパッド７１がバンプ９２を介して接合されて半導体８０が搭載されており、半導体８０と多層プリント配線板２００の絶縁樹脂層との間にはアンダーフィル８１樹脂を流し込んだ構造としている。
【００２６】
以下本発明に係る多層プリント配線板の製造方法について説明する
図３（ａ）〜（ｆ）及び図４（ｇ）〜（ｋ）は、請求項５に係わる多層プリント配線板の製造方法の一実施例を工程順に示す模式構成断面図である。
まず、銅箔２１上に、樹脂溶液を塗布するか、プリプレーグを積層して半硬化状態の絶縁樹脂層１１を形成した片面銅箔付樹脂シート１０を準備する（図３（ａ）参照）。
ここで、銅箔２１は、１２〜１８μｍ厚のものが、絶縁層樹脂層１１は、５０〜１００μｍ厚のものが、それぞれ使用される。さらに、片面銅箔付樹脂シート１０に硫酸８０〜１６０ｇ／Ｌと３５ｗｔ％過酸化水素９０〜１５０ｇ／Ｌを組成とする酸化性液を１５〜６０秒間スプレーすることにより、銅箔２１をマクロエッチングして、５〜１０μｍ厚の銅箔にする。これは、エッチング法で微細配線層を形成するための銅箔薄型化の一処方例である。
【００２７】
次に、片面銅箔付樹脂シート１０の絶縁樹脂層１１の所定位置をレーザ加工してビア用孔４１を形成し、デスミア、めっき触媒付与及び無電解銅めっきを行って、めっき下地層（特に、図示せず）を形成する（図３（ｂ）参照）。
ここで、レーザ加工のレーザーとしては、炭酸ガスレーザ、エキシマレーザ、ＹＡＧレーザ等が利用でき、例えば、炭酸ガスレーザを使用した場合スポット径（直径）０．１２５ｍｍのレーザビームを５〜２０ｍＪで１〜３パルス照射するのが好適である。
デスミア処方としては、例えば、ＭＬＢ２１１：シプレイ・ファーイースト（株）製を２０ｖｏｌ％、キューポジットＺが１０ｖｏｌ％からなる膨潤浴に６０〜８５℃で１〜５分間浸漬した後、ＭＬＢ２１３Ａ（シプレイ・ファーイースト（株）製）が１０ｖｏｌ％とＭＬＢ２１３Ｂ（シプレイ・ファーイースト（株）製）が１５ｖｏｌ％とからなるエッチング浴に５５〜７５℃で２〜１０分間浸漬処理し、ＭＬＢ２１６−２（シプレイ・ファーイースト（株）製）が２０ｖｏｌ％からなる中和浴に３５〜５５℃で２〜１０分間浸漬することにより、絶縁樹脂層１１表面及びビア用孔４１のデスミア処理を行う。
【００２８】
また、めっき触媒付与及びめっき下地導電層の形成処方としては、例えば、上記基板をプレディップＣＰ−３０２３（シプレイ・ファーイースト（株）製）浴に２５℃で６０秒間浸漬後、同社製キャタリスト同ＣＰ−３３１６浴に２５℃で１８０秒間、同社製アクセラレーター（ＮＲ−２ＡとＮＲ−２Ｂを各々１０ｖｏｌ％と３ｖｏｌ％で混合した水溶液）に２５℃で３００秒間順次浸漬して、絶縁樹脂層１１表面及びビア用孔４１にパラジウム触媒を付与した後無電解銅めっきを行ってめっき下地導電層（特に、図示せず）を形成する。
【００２９】
次に、銅箔２１上に支持体シート６１を貼着した後、感光性ドライフィルムを８０〜１２０℃の熱ロールで絶縁樹脂層１１上に貼着し、離型シートを剥離して絶縁樹脂層１１上に感光層を形成し、超高圧水銀ランプで５０〜２００ｍＪ／ｃｍ２の紫外線を照射してパターン露光した後、０．５〜２ｗｔ％炭酸ナトリウム水溶液をスプレー現像し、乾燥硬化してめっきレジストパターン５１を形成する（図３（ｃ）参照）。
ここで、支持体シート６１は上記処理基板の補強及び処理工程での銅箔２１の保護を行うためのもので、ポリエステルフィルム、ポリイミドフィルム、アミドフィルム、ポリプロピレンフィルム、ポリサルホンフィルム、ポリフェニルサルホンフィルム、ポリエーテルサルホンフィルム、ポフェニレンサルファイドフィルム、ポフェニレンエーテルフィルム、ポリエーテルエーテルケトンフィルム、ポフェニレンテレフタルアミドフィルムの中から工程処理条件等に合わせて適宜選択して使用する。
【００３０】
次に、めっきレジストパターン５１が形成された配線基板を硫酸銅めっき浴中に浸漬し、めっき下地導電層をカソードにして電解銅めっきを行い、絶縁樹脂層１１上に１０〜１５μｍ厚の導体層２２及びビア用孔４１にフィルドビア３１を形成する（図３（ｄ）参照）。
ここで、電解銅めっき条件としては、例えば、硫酸銅７０〜１００ｇ／Ｌ、硫酸１５０〜２５０ｇ／Ｌ、塩酸５０〜１００ｐｐｍの組成から成る硫酸銅めっき浴を用いて、電流密度１．５〜２．５Ａ／ｄｍ２の条件で２０〜５０分電解銅めっきを行って上記１０〜１５μｍ厚の銅からなる導体層を形成する。
また、ビア用孔４１にはフィルドビアを形成したが特に限定されるものではなく、フィルドビア、コンフォーマルビアを適宜選択して用いれば良い。
【００３１】
次に、０．５〜２ｗｔ％水酸化ナトリウム水溶液をスプレーして、めっきレジストパターン５１を剥離処理し、めっきレジストパターン５１下部にあっためっき下地導電層をフラッシュエッチングで除去し、支持体シート６１を除去して第２配線層２２ａを形成し、銅箔２１上に絶縁樹脂層１１を介して第２配線層２２ａ及びフィルドビア３１が形成されたビルドアップ層２０を形成する（図３（ｅ）参照）。
【００３２】
次に、第２配線層２２ａ側に支持体シート６２を貼着した後感光性のドライフィルムを８０〜１２０℃の熱ロールで絶縁樹脂層１１上に貼着し、離型シートを剥離して、絶縁樹脂層１１上に感光層を形成し、超高圧水銀ランプで５０〜２００ｍＪ／ｃｍ２の紫外線を照射してパターン露光した後、０．５〜２ｗｔ％炭酸ナトリウム水溶液をスプレー現像し、乾燥硬化してレジストパターン５２を形成する（図３（ｆ）参照）。
ここで、支持体シート６２は上記処理基板の補強及び処理工程での銅箔２１の保護を行うためのもので、ポリエステルフィルム、ポリイミドフィルム、アミドフィルム、ポリプロピレンフィルム、ポリサルホンフィルム、ポリフェニルサルホンフィルム、ポリエーテルサルホンフィルム、ポフェニレンサルファイドフィルム、ポフェニレンエーテルフィルム、ポリエーテルエーテルケトンフィルム、ポフェニレンテレフタルアミドフィルムの中から工程処理条件等に合わせて適宜選択して使用する。
【００３３】
次に、レジストパターン５２をマスクにして塩化第二銅２００〜４００ｇ／ｌ、塩酸１００〜１５０ｇ／ｌからなるエッチング液をスプレーして銅箔２１をエッチング除去し、レジストパターン５２を０．５〜２．０ｗｔ％の水酸化ナトリウム水溶液で剥離除去して、第１配線層２１ａを形成する（図４（ｇ）参照）。
【００３４】
次に、第１配線層２１ａ上に樹脂溶液を塗布するか、もしくはプリプレーグシート等を貼着するかの方法で、絶縁樹脂層１２を形成し、絶縁樹脂層１２の所定の位置にレーザー加工等によりビア用孔４２を形成し、上記図３（ｂ）と同じ処方で、デスミア、めっき触媒付与及び無電解銅めっきを行ってめっき下地導電層（特に、図示せず）形成する（図４（ｈ）参照）。
【００３５】
次に、感光性のドライフィルムを８０〜１２０℃の熱ロールで絶縁樹脂層１２上に貼着し、離型シートを剥離して絶縁樹脂層１２上に感光層を形成し、超高圧水銀ランプで５０〜２００ｍＪ／ｃｍ２の紫外線を照射してパターン露光した後、０．５〜２ｗｔ％炭酸ナトリウム水溶液をスプレー現像し、乾燥硬化してめっきレジストパターン５３を形成する（図４（ｉ）参照）。
【００３６】
次に、めっきレジストパターン５３が形成された配線基板を硫酸銅めっき浴中に浸漬し、めっき下地導電層をカソードにして電解銅めっきを行い、絶縁樹脂層１１上に１０〜１５μｍ厚の導体層２３及びビア用孔４２にコンフォーマルビア３２を形成する（図４（ｊ）参照）。
ここで、電解銅めっき条件としては、上記図３（ｄ）の工程に用いた条件と同じ処方で良い。
また、ビア用孔４２にはコンフォーマルビアを形成したが特に限定されるものではなく、コンフォーマルビア、フィルドビアを適宜選択して用いれば良い。
【００３７】
次に、めっきレジストパターン５３を０．５〜２．０ｗｔ％水酸化ナトリウム水溶液で剥離除去し、めっきレジストパターン５３下部にあっためっき下地導電層をフラッシュエッチングで除去して第３配線層２３ａを形成し、支持体シート６２を除去して、第１配線層２１ａの一方の面に絶縁樹脂層１１を介して第２配線層２２ａ及びフィルドビア３１が形成されたビルドアップ層２０、他方の面に絶縁樹脂層１２を介して第３配線層２３ａ及びコンフォーマルビア３２が形成されたビルドアップ層３０からなる３層プリント配線板１００を得る（図４（ｋ）参照）。
さらに、必要に応じて上記絶縁樹脂層、配線層及びコンフォーマルビアもしくはフィルドビア形成工程を必要回数繰り返すことにより、所望の多層プリント配線板を得ることができる。
【００３８】
図５（ａ）〜（ｆ）及び図６（ｇ）〜（ｋ）は、請求項６に係わる多層プリント配線板の製造方法の一実施例を工程順に示す模式構成断面図である。
まず、図５（ａ）〜（ｆ）の工程は、上記図３（ａ）〜（ｆ）と同様の工程で処理し、第１配線層２１ａ、第２配線層２２ａ、ランド２２ｃ及びフィルドビア３２を形成し、絶縁樹脂層１１の両面に第１配線層２１ａと第２配線層２２ａランド２２ｂ及びフィルドビア３２が形成された両面配線板４０を得る（図６（ｇ）参照）。
【００３９】
次に、両面配線板４０の両面にプリプレーグシートを積層して絶縁樹脂層１３及び絶縁樹脂層１４を形成し、絶縁樹脂層１３及び絶縁樹脂層１４の所定の位置にレーザー加工等によりビア用孔４３及びビア用孔４４を形成し、デスミア、めっき触媒付与及び無電解銅めっきを行ってめっき下地導電層（特に、図示せず）形成する（図６（ｈ）参照）。
ここで、デスミア、めっき触媒付与及び無電解銅めっき条件としては、上記図３（ｂ）の工程に用いた条件と同じ処方で良い。
【００４０】
次に、感光性ドライフィルムを８０〜１２０℃の熱ロールで絶縁樹脂層１３及び絶縁樹脂層１４上に貼着し、離型シートを剥離して絶縁樹脂層１３及び絶縁樹脂層１４上に感光層を形成し、超高圧水銀ランプで５０〜２００ｍＪ／ｃｍ２の紫外線を両面照射してパターン露光した後、０．５〜２ｗｔ％炭酸ナトリウム水溶液をスプレー現像し、乾燥硬化してめっきレジストパターン５４及びめっきレジストパターン５５をそれぞれ形成する（図６（ｉ）参照）。
【００４１】
次に、めっきレジストパターン５４及びめっきレジストパターン５５が形成された配線基板を硫酸銅めっき浴中に浸漬し、めっき下地導電層をカソードにして電解銅めっきを行い、絶縁樹脂層１３上に１０〜１５μｍ厚の導体層２４及びビア用孔４３にコンフォーマルビア３３を、絶縁樹脂層１４上に１０〜１５μｍ厚の導体層２５及びビア用孔４４にフィルドビア３４をそれぞれ形成する（図６（ｊ）参照）。
ここで、電解銅めっき条件としては、上記図３（ｄ）の工程に用いた条件と同じ処方で良い。
【００４２】
次に、めっきレジストパターン５４及びめっきレジストパターン５５を０．５〜２．０ｗｔ％水酸化ナトリウム水溶液で剥離除去し、めっきレジストパターン５４及びめっきレジストパターン５５下部にあっためっき下地導電層をフラッシュエッチングで除去して、第３配線層２４ａ、第４配線層２５ａ及びランド２５ｂを形成し、両面配線板４０の一方の面に絶縁樹脂層１３を介して第３配線層２４ａ及びコンフォーマルビア３３が形成されたビルドアップ層５０、他方の面に絶縁樹脂層１３を介して第４配線層２５ａ及びフィルドビア３４が形成されたビルドアップ層５０をそれぞれ形成し、４層プリント配線板２００を得る（図６（ｋ）参照）。
さらに、必要に応じて上記絶縁樹脂層、配線層及びコンフォーマルビアもしくはフィルドビア形成工程を必要回数繰り返すことにより、所望の多層プリント配線板を得ることができる。
【００４３】
【発明の効果】
上記したように、本発明の多層プリント配線板は、コア基板のないビルドアップ多層プリント配線板の構造とすることで、配線層のパターン設計自由度が増すとともに、配線層の収容性が向上し、薄型化及び微細配線層の形成が可能になり、高密度化が図れる。
また、対称構造のビルドアップ多層プリント配線板となっているため、薄型化しても配線板の反りが生じ難い。
また、本発明の多層プリント配線板の製造方法では、セミアディティブ法を用いて配線層を形成しているので、微細パターンの配線層を容易に得ることができる。
また、支持体シートを用いているので、多層プリント配線板の製造工程中での保護層を兼ねた処理基板の補強を容易に実施でき、特に、薄型化した配線板を製造する場合には変形防止効果が発揮される。
【図面の簡単な説明】
【図１】（ａ）〜（ｃ）は、本発明の多層プリント配線板の一実施例を示す模式構成断面図である。
【図２】（ａ）〜（ｄ）は、本発明の半導体装置の一実施例を示す模式構成断面図である。
【図３】（ａ）及び（ｆ）は、本発明の請求項５に係る多層プリント配線板の製造法における工程の一部を模式的に示す断面図である。
【図４】（ｇ）及び（ｋ）は、本発明の請求項５に係る多層プリント配線板の製造法における工程の一部を模式的に示す断面図である。
【図５】（ａ）及び（ｆ）は、本発明の請求項６に係る多層プリント配線板の製造法における工程の一部を模式的に示す断面図である。
【図６】（ｇ）及び（ｋ）は、本発明の請求項６に係る多層プリント配線板の製造法における工程の一部を模式的に示す断面図である。
【図７】（ａ）及び（ｆ）は、従来の多層プリント配線板の製造法の工程一例を模式的に示す断面図である。
【図８】（ａ）及び（ｄ）は、従来の多層プリント配線板の製造法の工程一例を模式的に示す断面図である。
【符号の説明】
１０……片面銅箔付樹脂シート
１１、１２、１３、１４、１１１、１１４……絶縁樹脂層
２０、２０ａ、３０、５０、６０、７３０、７４０、８３０……ビルドアップ層
２１、１２１、１２２、１２５、１２６……銅箔
２１ａ……第１配線層
２２、２３、２４、２５……導体層
２２ａ……第２配線層
２２ｂ……コンフォーマルビアランド
２２ｃ、２５ｂ……ランド
２３ａ、２４ａ……第３配線層
２５ａ……第４配線層
３１、３４……フィルドビア
３１ａ、３２、３３、１３１、１３４、１３５……コンフォーマルビア
４０……両面配線板
４１、４２、４３、４４、１４１、１４２……ビア用孔
５１、５３、５４、５５、１５１……めっきレジストパターン
５２、１５３……レジストパターン
６１、６２……支持体シート
７１……パッド
８０……半導体
８１……アンダーフィル
９１……半田
９２……バンプ
１００、１００ａ、２００、７００、８００……多層プリント配線板
１２１ａ、１２２ａ、１２５ａ、１２６ａ、１２７、１２８、１２９……配線層
１５２、１５４……保護マスク層
３００、４００、５００、６００……半導体装置
７１０、８１０……両面銅貼り積層板
７２０、８２０……コア基板[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multilayer printed wiring board having a plurality of wiring layers formed on both surfaces of a first wiring layer via insulating layers, a method for manufacturing the same, and a semiconductor device.
[0002]
[Prior art]
In recent years, a multilayer printed wiring board having a high-density and high-precision wiring layer has been required for a printed wiring board on which a semiconductor device is mounted due to the development of semiconductor mounting technology. In order to form high-density, high-precision wiring layers, printed wiring boards are multilayered, the line width of the wiring layers is also reduced, and via holes used for connection between wiring layers are required to have smaller hole diameters. ing. In addition, high-precision processing is also required for the processing of via-holes so as to minimize displacement. In order to satisfy such requirements, a so-called build-up method has been put to practical use, in which wiring layers and insulating layers are alternately formed to form a multilayer wiring layer to produce a multilayer printed wiring board.
[0003]
FIGS. 7A to 7F show an example of a conventional technique for producing a multilayer printed wiring board by a build-up method (for example, see Patent Document 1).
Hereinafter, a method for manufacturing a multilayer printed wiring board by a build-up method will be described with reference to FIGS.
First, a double-sided copper-clad laminate 710 in which copper foils 121 and 122 are laminated on both surfaces of an insulating base material 111 is prepared (see FIG. 7A).
Next, the copper foil 122 of the double-sided copper-clad laminate 710 is subjected to a patterning process by an etching method to form a first wiring layer 122a. A hole 141 is formed (see FIG. 7B).
[0004]
Next, a photosensitive layer is formed by laminating a photosensitive dry film on both sides, and a series of patterning processes such as pattern exposure and development are performed on the photosensitive layer on the first wiring layer 122a side. Exposure is performed to form a plating resist pattern 151 and a protective mask layer 152. Further, the surface of the insulating base material 111 and the via hole 141 on the side of the plating resist pattern 151 is subjected to desmearing, catalyst nucleation treatment, and electroless copper plating to form a plating base conductive layer, and the plating base conductive layer is used as a cathode. To form a conformal via 131 (see FIG. 7C).
[0005]
Next, a photosensitive dry film is laminated on both sides to form a photosensitive layer, and the photosensitive layer on the copper foil 121 side is subjected to a series of patterning processes such as pattern exposure and development, and the photosensitive layer on the first wiring layer 122a side is entirely exposed. Exposure is performed to form a resist pattern 153 and a protective mask layer 154. Further, the copper foil 121 is etched using the resist pattern 153 as a mask (see FIG. 7D).
[0006]
Next, the resist pattern 153 and the protective mask layer 154 are subjected to a peeling treatment, and a wiring layer 121a is formed on one surface of the insulating base material 111 and a wiring layer 122a is formed on the other surface, thereby manufacturing a core substrate 720 (FIG. e)).
Further, build-up layers 730 and 740 are formed on both surfaces of the core substrate 720 to obtain a four-layer printed wiring board 700 (see FIG. 7F).
[0007]
FIGS. 8A to 8D show another example of a conventional technique for manufacturing a multilayer printed wiring board by a build-up method (for example, see Patent Document 2).
Hereinafter, a method of manufacturing a multilayer printed wiring board by a build-up method will be described with reference to FIGS.
First, a double-sided copper-clad laminate 810 in which copper foils 125 and 126 are laminated on both surfaces of an insulating base material 114 is prepared (see FIG. 8A).
Next, a predetermined position on the copper foil 126 side of the double-sided copper-clad laminate 610 is drilled by laser processing or the like to form a via hole 142 (see FIG. 8B).
[0008]
Next, the copper foil 125 and the copper foil 126 are patterned by a subtractive method to form a wiring layer 125a and a wiring layer 126a. Further, a core layer 820 is formed by forming a wiring layer 127 on the wiring layer 126a and a via hole 134 in the via hole 142 by a semi-additive method (see FIG. 8C).
[0009]
Next, the wiring layer 128 is formed on the wiring layer 127 side of the core substrate 820 via the insulating layer 115 by a subtractive method. Further, a wiring layer 129 and a via hole 135 are formed by a semi-additive method to form a build-up layer 830, and a three-layer printed wiring board 600 including the core substrate 820 and the build-up layer 830 is obtained (see FIG. 8D). .
[0010]
[Patent Document 1]
JP 2001-94252 A
[Patent Document 2]
JP 09-46042 A
[0011]
[Problems to be solved by the invention]
In the method of manufacturing a multilayer printed wiring board by a build-up method using the above-described conventional technique, it is difficult to form a fine wiring layer because a subtractive method is used.
Further, the multilayer printed wiring board manufactured using the technique of Patent Document 1 has an asymmetric structure with respect to the insulating base material, and thus has a problem that warpage easily occurs.
[0012]
The present invention has been devised in view of the above problems, and has as its object to provide a method of manufacturing a multilayer printed wiring board on which a fine wiring layer can be formed, a multilayer printed wiring board that is unlikely to warp, and a semiconductor device.
[0013]
[Means for Solving the Problems]
In order to achieve the above object in the present invention, first, according to claim 1, a plurality of wiring layers are formed on both surfaces of a first wiring layer via an insulating resin layer. It is a plate.
[0014]
According to a second aspect of the present invention, the first wiring layer is electrically connected to the wiring layer and the wiring layer by a conformal via or a filled via via the insulating resin layer. A multilayer printed wiring board as described in 1 above.
[0015]
According to a third aspect of the present invention, the multilayer printed wiring board according to the first or second aspect is a multilayer printed wiring board having a symmetric structure.
[0016]
A semiconductor device comprising a semiconductor mounted on the multilayer printed wiring board according to any one of claims 1 to 3.
[0017]
The method for manufacturing a multilayer printed wiring board according to any one of claims 1 to 3, comprising at least the following steps.
(A) A step of preparing a resin sheet 10 with a single-sided copper foil composed of an insulating resin layer 11 and a copper foil 21.
(B) A step of forming a via hole 41 at a predetermined position of the insulating resin layer 11 of the resin sheet 10 with a single-sided copper foil, performing desmearing, applying a plating catalyst, and electroless copper plating to form a plating underlying conductive layer.
(C) A step of forming a plating resist pattern 51 by adhering a support sheet 61 on the copper foil 21 and then forming a photosensitive layer on the conductive layer under plating and performing a series of patterning processes such as pattern exposure and development. .
(D) A step of forming a conductor layer 22 and a filled via 31 having a predetermined thickness by performing electrolytic copper plating using the plating underlying conductive layer as a cathode.
(E) The resist pattern 51 is peeled off, the underlying conductive layer under the plating resist pattern 51 is removed by flash etching, the second wiring layer 22a and the filled via 31 are formed, and the support sheet 61 is removed. Process.
(F) A step of forming a resist pattern 52 by forming a photosensitive layer on the copper foil 21 after attaching the support sheet 62 to the second wiring layer 22a side and performing a series of patterning processes such as pattern exposure and development. .
(G) a step of etching the copper foil 21 using the resist pattern 52 as a mask and removing the resist pattern 52 to form the first wiring layer 21a.
(H) An insulating resin layer 12 having a predetermined thickness is formed on the first wiring layer 21a side, a via hole 42 is formed at a predetermined position of the insulating resin layer 12 by laser processing or the like, and desmearing, plating catalyst application, and electroless copper A step of performing plating to form a conductive layer under the plating;
(I) a step of forming a photosensitive layer on the insulating resin layer 12 side and performing a series of patterning processes such as pattern exposure and development to form a plating resist pattern 53;
(J) A step of performing electrolytic copper plating using the plating underlying conductive layer as a cathode to form a conductor layer 23 and a conformal via 32 having a predetermined thickness.
(K) The resist pattern 53 is peeled off, the underlying conductive layer under the plating resist pattern 53 is removed by flash etching, the third wiring layer 23a and the conformal via 32 are formed, and the support sheet 62 is formed. Removing.
(L) a step of repeating the insulating resin layer, the wiring layer, and the conformal via or filled via forming step a required number of times;
[0018]
The method for manufacturing a multilayer printed wiring board according to any one of claims 1 to 3, comprising at least the following steps.
(A) A step of preparing a resin sheet 10 with a single-sided copper foil composed of an insulating resin layer 11 and a copper foil 21.
(B) A step of forming a via hole 41 at a predetermined position of the insulating resin layer 11 and performing desmearing, applying a plating catalyst, and electroless copper plating to form a plating underlying conductive layer.
(C) A step of forming a plating resist pattern 51 by adhering a support sheet 61 on the copper foil 21 and then forming a photosensitive layer on the conductive layer under plating and performing a series of patterning processes such as pattern exposure and development. .
(D) A step of forming a conductive layer 22 and a filled via 31 having a predetermined thickness by performing electrolytic copper plating using the plating base conductive layer as a cathode.
(E) The plating resist pattern 51 is peeled off, the underlying conductive layer under the plating resist pattern 51 is removed by flash etching, the second wiring layer 22a and the filled via 31 are formed, and the support sheet 61 is removed. Process.
(F) A step of forming a resist pattern 52 by forming a photosensitive layer on the copper foil 21 after attaching the support sheet 62 to the second wiring layer 22a side and performing a series of patterning processes such as pattern exposure and development. .
(G) A step of etching the copper foil 21 using the resist pattern 52 as a mask, removing the resist pattern 52, forming the first wiring layer 21a, and removing the support sheet 62.
(H) An insulating resin layer 13 and an insulating resin layer 14 having a predetermined thickness are formed on the first wiring layer 21a and the second wiring layer 22a, respectively, and predetermined positions of the insulating resin layer 13 and the insulating resin layer 14 are formed by laser processing or the like. A step of forming a via hole 43 and a via hole 44, respectively, performing desmear, applying a plating catalyst, and electroless copper plating to form a plating underlying conductive layer, respectively.
(I) A step of forming a photosensitive layer on the insulating resin layer 13 and the insulating resin layer 14, respectively, and forming a plating resist pattern 54 and a plating resist pattern 55 by performing a series of patterning processes such as pattern exposure and development.
(J) A step of forming a conductor layer 24 and conformal via 33, a conductor layer 25 and a filled via 34 having a predetermined thickness by performing electrolytic copper plating using the plating base conductive layer as a cathode.
(K) The plating resist patterns 54 and 55 are stripped, the underlying conductive layer under the plating resist patterns 54 and 55 is removed by flash etching, and the third wiring layer 24a, the conformal via 33, and the fourth wiring Forming a layer 25a and a filled via 34;
(L) a step of repeating the insulating resin layer, the wiring layer, and the conformal via or filled via forming step a required number of times;
[0019]
7. The method according to claim 5, wherein the support sheet is formed of any one of a polyester film, a polyimide film, an amide film, and a polypropylene film.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
One embodiment of the multilayer printed wiring board of the present invention is shown in FIGS. 1 (a), 1 (b) and 1 (c). FIGS. 2A to 2D show an embodiment of a semiconductor device in which a semiconductor is mounted on a multilayer printed wiring board according to the present invention.
As shown in FIG. 1A, a multilayer printed wiring board 100 according to the present invention has a build in which a second wiring layer 22a and a filled via 31 are formed on one surface of a first wiring layer 21a via an insulating resin layer 11. And a build-up layer 30 having a third wiring layer 23a and a conformal via 32 formed on the other surface. The first wiring layer 21a and the second wiring layer 22a are filled vias 31. The first wiring layer 21a and the third wiring layer 23a are electrically connected by conformal vias 32, respectively. It has a symmetrical three-layer printed wiring board structure in which the buildup layer 20 and the buildup layer 30 are formed symmetrically with respect to the first wiring layer 21a.
[0021]
As shown in FIG. 1B, the multilayer printed wiring board 100a of the present invention has a second wiring layer 22a, a conformal via land 22b and a It comprises a build-up layer 20a on which a formal via 31a is formed, and a build-up layer 30 on which the third wiring layer 23a and the conformal via 32 are formed on the other surface. The first wiring layer 21a and the second The wiring layer 22a is electrically connected with the conformal via 31a, and the first wiring layer 21a and the third wiring layer 23a are electrically connected with the conformal via 32, respectively. Further, the three-layer printed wiring board has a symmetric structure in which the buildup layer 20a and the buildup layer 30 are formed symmetrically with respect to the first wiring layer 21a.
[0022]
Further, as shown in FIG. 1C, the multilayer printed wiring board 200 of the present invention has a double-sided wiring board in which a first wiring layer 21a, a second wiring layer 22a, and a filled via 31 are formed on both surfaces of an insulating resin layer 11. 40, a build-up layer 50 in which the third wiring layer 24a and the conformal via 33 are formed on one surface of the double-sided wiring board 40 via the insulating resin layer 13, and a second layer via the insulating layer 14 on the other surface. The first wiring layer 21a and the second wiring layer 22a are filled vias 31, and the first wiring layer 21a and the third wiring layers 21a and the third wiring layer 22a are formed by a build-up layer 60 on which four wiring layers 25a, lands 25b and filled vias 34 are formed. The wiring layer 24a is electrically connected with the conformal via 33, and the second wiring layer 22a and the fourth wiring layer 25a are electrically connected with the filled via 34, respectively. Further, a four-layer printed wiring board having a symmetric structure in which the build-up layer 50 and the build-up layer 60 are formed symmetrically with respect to the insulating resin layer 11.
[0023]
The multilayer printed wiring boards 100, 100a, and 200 of the present invention have a structure of a build-up multilayer printed wiring board without a core substrate, thereby eliminating wiring restrictions due to a BVH (blind via hole) of the core substrate. High density and thinness can be achieved.
More specifically, the degree of freedom in pattern design of the wiring layer is increased, the accommodating property of the wiring layer is improved, the thickness can be reduced and the fine wiring layer can be formed, and the density can be increased.
In addition, since it is a build-up multilayer printed wiring board having a symmetric structure, the wiring board is unlikely to be warped even if it is made thin.
[0024]
Hereinafter, the semiconductor device of the present invention will be described.
As shown in FIG. 2A, the semiconductor device 300 of the present invention has a filled via on the multilayer printed wiring board 100 of the present invention and a pad 71 of the semiconductor 80, and the semiconductor 80 is mounted thereon. The underfill 81 resin is injected between the insulating resin layer of the multilayer printed wiring board 100 and the insulating resin layer.
Further, as shown in FIG. 2B, the semiconductor device 400 of the present invention has the conformal via lands on the multilayer printed wiring board 100a of the present invention and the pads 71 of the semiconductor 80 bonded to each other to mount the semiconductor 80. The underfill 81 is formed between the semiconductor 80 and the insulating resin layer of the multilayer printed wiring board 100a.
[0025]
In the semiconductor device 500 of the present invention, as shown in FIG. 2C, the filled vias or lands on the multilayer printed wiring board 200 of the present invention are connected to the pads 71 of the semiconductor 80 via the solder 91, and the semiconductor 80 is mounted. The structure is such that an underfill 81 resin is poured between the semiconductor 80 and the insulating resin layer of the multilayer printed wiring board 200.
Further, as shown in FIG. 2D, the semiconductor device 600 of the present invention is formed by joining the filled via 34 or the land 25b on the multilayer printed wiring board 200 of the present invention to the pad 71 of the semiconductor 80 via the bump 92. A semiconductor 80 is mounted, and an underfill 81 resin is poured between the semiconductor 80 and the insulating resin layer of the multilayer printed wiring board 200.
[0026]
Hereinafter, a method for manufacturing a multilayer printed wiring board according to the present invention will be described.
3 (a) to 3 (f) and 4 (g) to 4 (k) are schematic sectional views showing one embodiment of a method for manufacturing a multilayer printed wiring board according to claim 5 in the order of steps.
First, a resin sheet 10 with a single-sided copper foil is prepared by applying a resin solution or laminating a prepreg on the copper foil 21 to form a semi-cured insulating resin layer 11 (see FIG. 3A).
Here, a copper foil 21 having a thickness of 12 to 18 μm is used, and an insulating resin layer 11 having a thickness of 50 to 100 μm is used. Further, the copper foil 21 is macro-etched by spraying an oxidizing liquid having a composition of 80 to 160 g / L of sulfuric acid and 90 to 150 g / L of hydrogen peroxide on the single-sided copper foil resin sheet 10 for 15 to 60 seconds. Then, a copper foil having a thickness of 5 to 10 μm is obtained. This is an example of a recipe for thinning a copper foil for forming a fine wiring layer by an etching method.
[0027]
Next, a predetermined position of the insulating resin layer 11 of the resin sheet 10 with a single-sided copper foil is laser-processed to form a via hole 41, desmearing, plating catalyst application, and electroless copper plating are performed to form a plating base layer (particularly, , Not shown) (see FIG. 3B).
Here, as a laser for laser processing, a carbon dioxide gas laser, an excimer laser, a YAG laser, or the like can be used. For example, when a carbon dioxide gas laser is used, a laser beam having a spot diameter (diameter) of 0.125 mm is applied at 5 to 20 mJ at 1 to 3 mJ. It is preferable to perform pulse irradiation.
As a desmear formulation, for example, MLB211: manufactured by Shipley Far East Co., Ltd. is immersed in a swelling bath consisting of 20 vol% and 10 cup% Z at 60 to 85 ° C. for 1 to 5 minutes. Yeast Co., Ltd.) is immersed in an etching bath consisting of 10 vol% and MLB213B (manufactured by Shipley Fur East Co., Ltd.) at 15 vol% at 55 to 75 ° C. for 2 to 10 minutes, and MLB216-2 (Shipley Fur Co., Ltd.) The surface of the insulating resin layer 11 and the via holes 41 are desmeared by immersing in a 20 vol% neutralization bath of 35% to 55 ° C. for 2 to 10 minutes.
[0028]
In addition, as a prescription for applying a plating catalyst and forming a conductive layer under the plating, for example, after dipping the above substrate in a bath of Predip CP-3023 (manufactured by Shipley Far East Co., Ltd.) at 25 ° C. for 60 seconds, a catalyst manufactured by the company is used. In the same CP-3316 bath at 25 ° C. for 180 seconds, the film was sequentially immersed in an accelerator (an aqueous solution in which NR-2A and NR-2B were mixed at 10 vol% and 3 vol%, respectively) at 25 ° C. for 300 seconds at 25 ° C. to form an insulating resin layer. After applying a palladium catalyst to the surface 11 and the via hole 41, electroless copper plating is performed to form a conductive layer (especially not shown) under the plating.
[0029]
Next, after attaching the support sheet 61 on the copper foil 21, a photosensitive dry film is attached on the insulating resin layer 11 with a hot roll at 80 to 120 ° C., and the release sheet is peeled off to remove the insulating resin. A photosensitive layer is formed on the layer 11 and is irradiated with an ultra-high pressure mercury lamp at 50 to 200 mJ / cm. 2 After the pattern exposure by irradiating with ultraviolet light, a 0.5 to 2 wt% aqueous solution of sodium carbonate is spray-developed, dried and cured to form a plating resist pattern 51 (see FIG. 3C).
Here, the support sheet 61 is for reinforcing the processing substrate and protecting the copper foil 21 in the processing step, and is a polyester film, a polyimide film, an amide film, a polypropylene film, a polysulfone film, a polyphenylsulfone film. And polyether sulfone film, pophenylene sulfide film, pophenylene ether film, polyether ether ketone film, and pophenylene terephthalamide film.
[0030]
Next, the wiring board on which the plating resist pattern 51 is formed is immersed in a copper sulfate plating bath, electrolytic copper plating is performed using the plating underlying conductive layer as a cathode, and a 10-15 μm thick conductive layer is formed on the insulating resin layer 11. The filled via 31 is formed in the via hole 22 and the via hole 41 (see FIG. 3D).
Here, the electrolytic copper plating conditions are, for example, a copper sulfate plating bath having a composition of copper sulfate 70 to 100 g / L, sulfuric acid 150 to 250 g / L, hydrochloric acid 50 to 100 ppm, and a current density of 1.5 to 2 Electrolytic copper plating is performed for 20 to 50 minutes under the condition of 0.5 A / dm2 to form the above-described conductor layer made of copper having a thickness of 10 to 15 m.
Although a filled via is formed in the via hole 41, the present invention is not particularly limited to this, and a filled via or a conformal via may be appropriately selected and used.
[0031]
Next, the plating resist pattern 51 is stripped by spraying a 0.5 to 2 wt% aqueous solution of sodium hydroxide, and the underlying conductive layer under the plating resist pattern 51 is removed by flash etching. Is removed to form a second wiring layer 22a, and a build-up layer 20 in which the second wiring layer 22a and the filled via 31 are formed on the copper foil 21 via the insulating resin layer 11 is formed (FIG. 3E). reference).
[0032]
Next, after attaching the support sheet 62 to the second wiring layer 22a side, a photosensitive dry film is attached on the insulating resin layer 11 with a hot roll at 80 to 120 ° C., and the release sheet is peeled off. After forming a photosensitive layer on the insulating resin layer 11 and irradiating an ultraviolet ray of 50 to 200 mJ / cm 2 with an ultra-high pressure mercury lamp for pattern exposure, spray-developing an aqueous solution of 0.5 to 2 wt% sodium carbonate and drying and curing. Thus, a resist pattern 52 is formed (see FIG. 3F).
Here, the support sheet 62 is for reinforcing the processing substrate and protecting the copper foil 21 in the processing step, and is a polyester film, a polyimide film, an amide film, a polypropylene film, a polysulfone film, a polyphenylsulfone film. And polyether sulfone film, pophenylene sulfide film, pophenylene ether film, polyether ether ketone film, and pophenylene terephthalamide film.
[0033]
Next, using the resist pattern 52 as a mask, an etching solution consisting of 200 to 400 g / l of cupric chloride and 100 to 150 g / l of hydrochloric acid is sprayed to remove the copper foil 21 by etching. The first wiring layer 21a is formed by peeling and removing with a 2.0 wt% sodium hydroxide aqueous solution (see FIG. 4G).
[0034]
Next, the insulating resin layer 12 is formed by applying a resin solution on the first wiring layer 21a or attaching a prepreg sheet or the like, and laser processing is performed on a predetermined position of the insulating resin layer 12. A via hole 42 is formed by the method described above, and desmearing, application of a plating catalyst, and electroless copper plating are performed by the same prescription as in FIG. 3B to form a conductive layer (especially not shown) under the plating (FIG. 4). (H)).
[0035]
Next, a photosensitive dry film is stuck on the insulating resin layer 12 with a hot roll at 80 to 120 ° C., and the release sheet is peeled off to form a photosensitive layer on the insulating resin layer 12. After pattern exposure by irradiating ultraviolet rays of 50 to 200 mJ / cm <2>, a 0.5 to 2 wt% aqueous solution of sodium carbonate is spray-developed, dried and cured to form a plating resist pattern 53 (see FIG. 4 (i)). .
[0036]
Next, the wiring board on which the plating resist pattern 53 is formed is immersed in a copper sulfate plating bath, electrolytic copper plating is performed using the plating underlying conductive layer as a cathode, and a conductive layer having a thickness of 10 to 15 μm is formed on the insulating resin layer 11. The conformal via 32 is formed in the via hole 42 and the via hole 42 (see FIG. 4 (j)).
Here, the conditions for electrolytic copper plating may be the same as the conditions used in the step of FIG.
Further, a conformal via is formed in the via hole 42, but the present invention is not particularly limited to this, and a conformal via or a filled via may be appropriately selected and used.
[0037]
Next, the plating resist pattern 53 is peeled and removed with a 0.5 to 2.0 wt% aqueous solution of sodium hydroxide, and the underlying conductive layer under the plating resist pattern 53 is removed by flash etching to remove the third wiring layer 23a. Formed, the support sheet 62 is removed, the build-up layer 20 in which the second wiring layer 22a and the filled via 31 are formed on one surface of the first wiring layer 21a via the insulating resin layer 11, and the other surface is formed. The three-layer printed wiring board 100 including the build-up layer 30 on which the third wiring layer 23a and the conformal via 32 are formed via the insulating resin layer 12 is obtained (see FIG. 4K).
Further, if necessary, the steps of forming the insulating resin layer, the wiring layer, and the conformal via or filled via are repeated a required number of times, whereby a desired multilayer printed wiring board can be obtained.
[0038]
5 (a) to 5 (f) and 6 (g) to 6 (k) are schematic sectional views showing one embodiment of a method for manufacturing a multilayer printed wiring board according to claim 6 in the order of steps.
First, in the steps of FIGS. 5A to 5F, processing is performed in the same steps as in FIGS. 3A to 3F, and the first wiring layer 21a, the second wiring layer 22a, the lands 22c, and the filled vias 32 are formed. To form a double-sided wiring board 40 having a first wiring layer 21a, a second wiring layer 22a lands 22b, and a filled via 32 formed on both surfaces of the insulating resin layer 11 (see FIG. 6G).
[0039]
Next, a prepreg sheet is laminated on both sides of the double-sided wiring board 40 to form an insulating resin layer 13 and an insulating resin layer 14, and via holes are formed at predetermined positions of the insulating resin layer 13 and the insulating resin layer 14 by laser processing or the like. The hole 43 and the via hole 44 are formed, and a plating underlayer conductive layer (particularly not shown) is formed by performing desmear, plating catalyst application, and electroless copper plating (see FIG. 6H).
The desmear, plating catalyst application, and electroless copper plating conditions may be the same as the conditions used in the step of FIG. 3B.
[0040]
Next, a photosensitive dry film is stuck on the insulating resin layer 13 and the insulating resin layer 14 with a hot roll at 80 to 120 ° C., and the release sheet is peeled off to expose the photosensitive resin film on the insulating resin layer 13 and the insulating resin layer 14. Form a layer and use an ultra-high pressure mercury lamp for 50-200 mJ / cm 2 After pattern exposure by irradiating both sides with ultraviolet rays, a 0.5 to 2 wt% aqueous solution of sodium carbonate is spray-developed and dried and cured to form a plating resist pattern 54 and a plating resist pattern 55, respectively (see FIG. 6 (i)). ).
[0041]
Next, the plating resist pattern 54 and the wiring board on which the plating resist pattern 55 is formed are immersed in a copper sulfate plating bath, electrolytic copper plating is performed using the plating underlying conductive layer as a cathode, and 10 to 10 A conformal via 33 is formed in the conductor layer 24 and the via hole 43 having a thickness of 15 μm, and a filled via 34 is formed in the conductor layer 25 and the via hole 44 having a thickness of 10 to 15 μm on the insulating resin layer 14 (FIG. 6J). reference).
Here, the conditions for electrolytic copper plating may be the same as the conditions used in the step of FIG.
[0042]
Next, the plating resist pattern 54 and the plating resist pattern 55 are peeled and removed with a 0.5 to 2.0 wt% sodium hydroxide aqueous solution, and the plating underlying conductive layer under the plating resist pattern 54 and the plating resist pattern 55 is flash-etched. To form a third wiring layer 24a, a fourth wiring layer 25a, and a land 25b. The third wiring layer 24a and the conformal via 33 are formed on one surface of the double-sided wiring board 40 via the insulating resin layer 13. The formed build-up layer 50 and the build-up layer 50 on which the fourth wiring layer 25a and the filled via 34 are formed on the other surface via the insulating resin layer 13 are formed, respectively, to obtain a four-layer printed wiring board 200 (FIG. 6 (k)).
Further, if necessary, the steps of forming the insulating resin layer, the wiring layer, and the conformal via or filled via are repeated a required number of times, whereby a desired multilayer printed wiring board can be obtained.
[0043]
【The invention's effect】
As described above, the multilayer printed wiring board of the present invention has a structure of a build-up multilayer printed wiring board without a core substrate, thereby increasing the degree of freedom in pattern design of the wiring layer and improving the accommodation of the wiring layer. In addition, the thickness can be reduced and the fine wiring layer can be formed, and the density can be increased.
In addition, since it is a build-up multilayer printed wiring board having a symmetric structure, the wiring board is unlikely to be warped even if it is made thin.
In the method for manufacturing a multilayer printed wiring board according to the present invention, since the wiring layer is formed using the semi-additive method, a wiring layer having a fine pattern can be easily obtained.
In addition, since the support sheet is used, it is possible to easily reinforce the processing substrate also serving as a protective layer during the manufacturing process of the multilayer printed wiring board. The prevention effect is exhibited.
[Brief description of the drawings]
FIGS. 1A to 1C are schematic sectional views showing one embodiment of a multilayer printed wiring board according to the present invention.
FIGS. 2A to 2D are schematic sectional views showing one embodiment of the semiconductor device of the present invention.
3 (a) and 3 (f) are cross-sectional views schematically showing some of the steps in the method for manufacturing a multilayer printed wiring board according to claim 5 of the present invention.
4 (g) and 4 (k) are cross-sectional views schematically showing some of the steps in the method for manufacturing a multilayer printed wiring board according to claim 5 of the present invention.
FIGS. 5A and 5F are cross-sectional views schematically showing some of the steps in the method for manufacturing a multilayer printed wiring board according to claim 6 of the present invention.
6 (g) and 6 (k) are cross-sectional views schematically showing some of the steps in the method for manufacturing a multilayer printed wiring board according to claim 6 of the present invention.
FIGS. 7A and 7F are cross-sectional views schematically showing an example of steps of a conventional method for manufacturing a multilayer printed wiring board.
FIGS. 8A and 8D are cross-sectional views schematically showing an example of steps of a conventional method for manufacturing a multilayer printed wiring board.
[Explanation of symbols]
10 ... Resin sheet with copper foil on one side
11, 12, 13, 14, 111, 114 ... Insulating resin layer
20, 20a, 30, 50, 60, 730, 740, 830... Build-up layer
21, 121, 122, 125, 126 ... copper foil
21a... First wiring layer
22, 23, 24, 25 ... conductor layer
22a... Second wiring layer
22b ... Conformal Vialand
22c, 25b ... land
23a, 24a... Third wiring layer
25a... Fourth wiring layer
31, 34 ... filled via
31a, 32, 33, 131, 134, 135 ... conformal via
40 Double-sided wiring board
41, 42, 43, 44, 141, 142 ... Via holes
51, 53, 54, 55, 151 ... Plating resist pattern
52, 153 resist pattern
61, 62 ... Support sheet
71 ... Pad
80 ... Semiconductor
81 …… Underfill
91 …… Solder
92 ...... Bump
100, 100a, 200, 700, 800 ... multilayer printed wiring board
121a, 122a, 125a, 126a, 127, 128, 129 ... wiring layer
152, 154: Protective mask layer
300, 400, 500, 600 ... semiconductor device
710, 810: double-sided copper-clad laminate
720, 820 ... core substrate

Claims (7)

第１配線層の両面に絶縁樹脂層を介して複数の配線層が形成されていることを特徴とする多層プリント配線板。A multilayer printed wiring board, wherein a plurality of wiring layers are formed on both surfaces of a first wiring layer via an insulating resin layer. 前記第１配線層と前記配線層及び前記配線層間は前記絶縁樹脂層を介してコンフォーマルビアもしくはフィルドビアにて電気的に接続されていることを特徴とする請求項１に記載の多層プリント配線板。The multilayer printed wiring board according to claim 1, wherein the first wiring layer, the wiring layer, and the wiring layer are electrically connected to each other by a conformal via or a filled via via the insulating resin layer. . 請求項１または２に記載の多層プリント配線板は対称構造になっていることを特徴とする多層プリント配線板。3. The multilayer printed wiring board according to claim 1, wherein the multilayer printed wiring board has a symmetric structure. 請求項１乃至３のいずれか一項に記載の多層プリント配線板上に半導体を搭載したことを特徴とする半導体装置A semiconductor device comprising a semiconductor mounted on the multilayer printed wiring board according to claim 1. 以下の工程を少なくとも備えることを特徴とする請求項１乃至３のいずれか一項に記載の多層プリント配線板の製造方法。
（ａ）絶縁樹脂層（１１）及び銅箔（２１）からなる片面銅箔付樹脂シート（１０）を準備する工程。
（ｂ）片面銅箔付樹脂シート（１０）の絶縁樹脂層（１１）の所定位置にビア用孔（４１）を形成し、デスミア、めっき触媒付与及び無電解銅めっきを行って、めっき下地導電層を形成する工程。
（ｃ）銅箔（２１）上に支持体シート（６１）を貼着した後めっき下地導電層上に感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってめっきレジストパターン（５１）を形成する工程。
（ｄ）めっき下地導電層をカソードにして電解銅めっきを行って所定厚の導体層（２２）及びフィルドビア（３１）を形成する工程。
（ｅ）レジストパターン（５１）を剥離処理し、めっきレジストパターン（５１）下部にあっためっき下地導電層をフラッシュエッチングにて除去し、第２配線層（２２ａ）及びフィルドビア（３１）を形成し、支持体シート（６１）を除去する工程。
（ｆ）第２配線層（２２ａ）側に支持体シート（６２）を貼着した後銅箔（２１）上に感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってレジストパターン（５２）を形成する工程。
（ｇ）レジストパターン（５２）をマスクにして銅箔（２１）をエッチング処理し、レジストパターン（５２）を剥離処理して、第１配線層（２１ａ）を形成する工程。
（ｈ）第１配線層（２１ａ）側に所定厚の絶縁樹脂層（１２）を形成し、絶縁樹脂層（１２）の所定位置にレーザー加工等によりビア用孔（４２）を形成し、デスミア、めっき触媒付与及び無電解銅めっきを行って、めっき下地導電層を形成する工程。
（ｉ）絶縁樹脂層（１２）側に感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってめっきレジストパターン（５３）を形成する工程。
（ｊ）めっき下地導電層をカソードにして電解銅めっきを行い、所定厚の導体層（２３）及びコンフォーマルビア（３２）を形成する工程。
（ｋ）レジストパターン（５３）を剥離処理し、めっきレジストパターン（５３）下部にあっためっき下地導電層をフラッシュエッチングにて除去し、第３配線層（２３ａ）及びコンフォーマルビア（３２）を形成し、支持体シート（６２）を除去する工程。
（ｌ）上記絶縁樹脂層、配線層及びコンフォーマルビアもしくはフィルドビア形成工程を必要回数繰り返す工程。The method for manufacturing a multilayer printed wiring board according to any one of claims 1 to 3, further comprising at least the following steps.
(A) a step of preparing a resin sheet (10) with a single-sided copper foil comprising an insulating resin layer (11) and a copper foil (21);
(B) A via hole (41) is formed at a predetermined position of the insulating resin layer (11) of the resin sheet (10) with a single-sided copper foil, and desmearing, plating catalyst application and electroless copper plating are performed, and plating base conductive is formed. Forming a layer;
(C) After affixing the support sheet (61) on the copper foil (21), a photosensitive layer is formed on the plating underlying conductive layer, and a series of patterning processes such as pattern exposure and development are performed to perform plating resist pattern ( Step 51).
(D) A step of forming a conductor layer (22) and a filled via (31) having a predetermined thickness by performing electrolytic copper plating using the plating underlying conductive layer as a cathode.
(E) The resist pattern (51) is peeled off, and the underlying conductive layer under the plating resist pattern (51) is removed by flash etching to form a second wiring layer (22a) and a filled via (31). Removing the support sheet (61).
(F) After attaching the support sheet (62) to the second wiring layer (22a) side, a photosensitive layer is formed on the copper foil (21), and a series of patterning processes such as pattern exposure and development are performed to form a resist. Forming a pattern (52);
(G) a step of etching the copper foil (21) using the resist pattern (52) as a mask and removing the resist pattern (52) to form a first wiring layer (21a);
(H) An insulating resin layer (12) having a predetermined thickness is formed on the first wiring layer (21a) side, and a via hole (42) is formed at a predetermined position of the insulating resin layer (12) by laser processing or the like. Forming a plating base conductive layer by applying a plating catalyst and performing electroless copper plating.
(I) forming a photosensitive layer on the insulating resin layer (12) side and performing a series of patterning processes such as pattern exposure and development to form a plating resist pattern (53);
(J) a step of forming a conductive layer (23) and a conformal via (32) having a predetermined thickness by performing electrolytic copper plating using the plating base conductive layer as a cathode;
(K) The resist pattern (53) is peeled off, the underlying plating conductive layer under the plating resist pattern (53) is removed by flash etching, and the third wiring layer (23a) and the conformal via (32) are removed. Forming and removing the support sheet (62).
(L) a step of repeating the insulating resin layer, the wiring layer, and the conformal via or filled via forming step a required number of times; 以下の工程を少なくとも備えることを特徴とする請求項１乃至３のいずれか一項に記載の多層プリント配線板の製造方法。
（ａ）絶縁樹脂層（１１）及び銅箔（２１）からなる片面銅箔付樹脂シート（１０）を準備する工程。
（ｂ）絶縁樹脂層（１１）の所定位置にビア用孔（４１）を形成し、デスミア、めっき触媒付与及び無電解銅めっきを行って、めっき下地導電層を形成する工程。
（ｃ）銅箔（２１）上に支持体シート（６１）を貼着した後めっき下地導電層上に感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってめっきレジストパターン（５１）を形成する工程。
（ｄ）めっき下地導電層をカソードにして電解銅めっきを行い、所定厚の導体層（２２）及びフィルドビア（３１）を形成する工程。
（ｅ）めっきレジストパターン（５１）を剥離処理し、めっきレジストパターン（５１）下部にあっためっき下地導電層をフラッシュエッチングにて除去し、第２配線層（２２ａ）及びフィルドビア（３１）を形成し、支持体シート（６１）を除去する工程。
（ｆ）第２配線層（２２ａ）側に支持体シート（６２）を貼着した後銅箔（２１）上に感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってレジストパターン（５２）を形成する工程。
（ｇ）レジストパターン（５２）をマスクにして銅箔（２１）をエッチング処理し、レジストパターン（５２）を除去して第１配線層（２１ａ）を形成し、支持体シート（６２）を除去する工程。
（ｈ）第１配線層（２１ａ）及び第２配線層（２２ａ）側にそれぞれ所定厚の絶縁樹脂層（１３）及び絶縁樹脂層（１４）を形成し、絶縁樹脂層（１３）及び絶縁樹脂層（１４）の所定位置にレーザー加工等によりそれぞれビア用孔（４３）及びビア用孔（４４）を形成し、デスミア、めっき触媒付与及び無電解銅めっきを行って、めっき下地導電層をそれぞれ形成する工程。
（ｉ）絶縁樹脂層（１３）及び絶縁樹脂層（１４）側にそれぞれ感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってめっきレジストパターン（５４）及びめっきレジストパターン（５５）を形成する工程。
（ｊ）めっき下地導電層をカソードにして電解銅めっきを行い、所定厚の導体層（２４）及びコンフォーマルビア（３３）、導体層（２５）及びフィルドビア（３４）をそれぞれ形成する工程。
（ｋ）めっきレジストパターン（５４）及（５５）を剥離処理し、めっきレジストパターン（５４）及び（５５）下部にあっためっき下地導電層をフラッシュエッチングにて除去し、第３配線層（２４ａ）及びコンフォーマルビア（３３）、第４配線層（２５ａ）及びフィルドビア（３４）を形成する工程。
（ｌ）上記絶縁樹脂層、配線層及びコンフォーマルビアもしくはフィルドビア形成工程を必要回数繰り返す工程。The method for manufacturing a multilayer printed wiring board according to any one of claims 1 to 3, further comprising at least the following steps.
(A) a step of preparing a resin sheet (10) with a single-sided copper foil comprising an insulating resin layer (11) and a copper foil (21);
(B) A step of forming a via hole (41) at a predetermined position of the insulating resin layer (11), performing desmearing, applying a plating catalyst, and performing electroless copper plating to form a plating underlying conductive layer.
(C) After affixing the support sheet (61) on the copper foil (21), a photosensitive layer is formed on the plating underlying conductive layer, and a series of patterning processes such as pattern exposure and development are performed to perform plating resist pattern ( Step 51).
(D) A step of forming a conductor layer (22) and a filled via (31) having a predetermined thickness by performing electrolytic copper plating using the plating base conductive layer as a cathode.
(E) The plating resist pattern (51) is peeled off, and the underlying conductive layer under the plating resist pattern (51) is removed by flash etching to form a second wiring layer (22a) and a filled via (31). And removing the support sheet (61).
(F) After attaching the support sheet (62) to the second wiring layer (22a) side, a photosensitive layer is formed on the copper foil (21), and a series of patterning processes such as pattern exposure and development are performed to form a resist. Forming a pattern (52);
(G) The copper foil (21) is etched using the resist pattern (52) as a mask, the resist pattern (52) is removed to form a first wiring layer (21a), and the support sheet (62) is removed. Process.
(H) forming an insulating resin layer (13) and an insulating resin layer (14) having a predetermined thickness on the first wiring layer (21a) and the second wiring layer (22a) side, respectively; Via holes (43) and via holes (44) are respectively formed at predetermined positions of the layer (14) by laser processing or the like, and desmearing, plating catalyst application, and electroless copper plating are performed to form a plating underlying conductive layer, respectively. Forming step.
(I) A photosensitive layer is formed on each of the insulating resin layer (13) and the insulating resin layer (14), and a series of patterning processes such as pattern exposure and development are performed to perform a plating resist pattern (54) and a plating resist pattern (55). ).
(J) a step of performing electrolytic copper plating using the plating base conductive layer as a cathode to form a conductor layer (24) and a conformal via (33), a conductor layer (25), and a filled via (34) each having a predetermined thickness.
(K) The plating resist patterns (54) and (55) are peeled off, the underlying plating conductive layer under the plating resist patterns (54) and (55) is removed by flash etching, and the third wiring layer (24a) is removed. And forming a conformal via (33), a fourth wiring layer (25a), and a filled via (34).
(L) a step of repeating the insulating resin layer, the wiring layer, and the conformal via or filled via forming step a required number of times; 前記支持体シートがポリエステルフィルム、ポリイミドフィルム、アミドフィルム、ポリプロピレンフィルムのいずれかで形成されていることを特徴とする請求項５または６に記載の多層プリント配線板の製造方法。The method for manufacturing a multilayer printed wiring board according to claim 5, wherein the support sheet is formed of any one of a polyester film, a polyimide film, an amide film, and a polypropylene film.
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