JP2007149731A - Wiring board, semiconductor device, and process for producing wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board in which warpage can be suppressed and reliability of electrical connection can be enhanced, and to provide a semiconductor device and a process for producing a wiring board. <P>SOLUTION: The wiring board includes a wiring pattern 21 provided on laminated insulation layers 18, 26, 32 and 38 and connected electrically with semiconductor chips 14 and 15, and a reinforcing metal layer 27 provided between the insulation layers 26 and 32 wherein the insulation layer 26 is provided with a first via 28 touching the metal layer 27 and connected electrically with the wiring pattern 21 arranged below the metal layer 27, and the insulation layer 32 is provided with a second via 33 touching the metal layer 27 and connected electrically with the wiring pattern 21 arranged above the metal layer 27. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a wiring board, a semiconductor device, and a manufacturing method of the wiring board, and in particular, a wiring board including a metal layer that reinforces the strength of the wiring board between laminated insulating layers, a semiconductor device, and the manufacturing of the wiring board. Regarding the method.

  The semiconductor device is configured to include a wiring board and a semiconductor chip that is electrically connected to the wiring board, and is electrically connected to a mounting board such as a mother board.

  In recent years, with the miniaturization of electronic devices, there is a demand for miniaturization of semiconductor devices mounted on electronic devices. As a wiring board capable of reducing the size of a semiconductor device, there is a coreless board that is thinned by removing a core base material from the configuration.

  However, the coreless substrate is weaker than the core substrate provided with the core base material, and is likely to warp. In order to solve such a problem, there is a coreless substrate in which a metal layer as a reinforcing material is provided between laminated insulating layers (see FIG. 1).

  FIG. 1 is a cross-sectional view of a conventional coreless substrate. In FIG. 1, W1 represents the opening diameter of the upper end of the opening 218 (hereinafter referred to as “opening diameter W1”), and W2 represents the opening diameter of the lower end of the opening 218 (hereinafter referred to as “opening diameter W2”). ing.

  Referring to FIG. 1, the coreless substrate 200 includes insulating layers 201 to 204, pads 206, external connection terminals 207, wirings 208 and 214, vias 209, 212, and 215, a metal layer 211, and connection pads. 216.

  The pad 206 is provided on the lower surface side of the insulating layer 201. The external connection terminal 207 is provided on the pad 206. The external connection terminal 207 is a terminal for electrically connecting the coreless substrate 200 to a mounting substrate such as a motherboard. The wiring 208 is provided over the insulating layer 201 and is electrically connected to the via 209. The via 209 is provided in the insulating layer 201 located between the pad 206 and the wiring 208, and electrically connects the pad 206 and the wiring 208.

  The insulating layer 202 is provided on the insulating layer 201 so as to cover the wiring 208. The metal layer 211 is for reinforcing the strength of the coreless substrate 200 and is provided on the insulating layer 202. The metal layer 211 is plate-shaped and has a function of suppressing warpage of the coreless substrate 200. The metal layer 211 is formed by attaching a metal foil (for example, Cu foil) on the insulating layer 202.

  The insulating layer 203 is provided on the insulating layer 202 so as to cover the metal layer 211. The opening 218 is formed so as to penetrate the insulating layers 202 and 203 located on the wiring 208. The opening 218 exposes the wiring 208. The opening 218 is for arranging the via 212. The opening 218 is formed by laser processing.

  The via 212 is provided in the opening 218. The via 212 is for electrically connecting the wiring 208 disposed below the metal layer 211 and the wiring 214 disposed above the metal layer 211. The via 212 is formed by depositing and growing a conductive metal in the opening 218 by electrolytic plating.

  The wiring 214 is provided over the insulating layer 203. The wiring 214 is electrically connected to the via 212. The insulating layer 204 is provided on the insulating layer 203 so as to cover the wiring 214. The via 215 is provided in the insulating layer 204 located on the wiring 214. The via 215 is electrically connected to the wiring 214.

  The connection pad 216 is provided on the insulating layer 204 corresponding to the position where the via 215 is formed. The connection pad 216 is a pad for connecting a semiconductor chip (not shown) (see, for example, Patent Document 1).

As described above, by providing the metal layer 211 between the stacked insulating layers 202 and 203, warping of the coreless substrate 200 can be suppressed.
JP-A-2005-72061

  However, in the conventional coreless substrate 200, the opening 218 in which the via 212 is disposed is formed so as to penetrate the two insulating layers 202 and 203 by laser processing. For this reason, the depth of the opening part 218 becomes deep and the opening diameter W2 of the lower end of the opening part 218 will become small. As a result, the contact area between the via 212 and the wiring 208 is reduced, so that the electrical connection between the wiring 208 disposed below the metal layer 211 and the wiring 214 disposed above the metal layer 211 is performed. There was a problem that the connection reliability deteriorated.

  For example, as one means for increasing the opening diameter W2 at the lower end of the opening 218, it is conceivable to increase the opening diameter W1 at the upper end of the opening 218. In this case, it is necessary to increase the size of the wiring 214 as well. Therefore, the coreless substrate 200 is increased in size and the semiconductor device cannot be reduced in size.

  Therefore, the present invention has been made in view of the above-described problems, and an object of the present invention is to reduce the warpage of the wiring board and improve the electrical connection reliability, a semiconductor device, And a method of manufacturing a wiring board.

  According to one aspect of the present invention, a wiring comprising a laminated insulating layer, a wiring pattern provided in the laminated insulating layer, and a reinforcing metal layer provided between the laminated insulating layers. A first via that is a substrate and is in contact with the metal layer and electrically connected to the wiring pattern disposed below the metal layer on the insulating layer located immediately below the metal layer. And a second via that is in contact with the metal layer and electrically connected to the wiring pattern disposed above the metal layer is provided in the insulating layer located immediately above the metal layer. Is provided.

  According to the present invention, the insulating layer located immediately below the metal layer is provided with the first via that is in contact with the metal layer and electrically connected to the wiring pattern disposed below the metal layer. By providing a second via in contact with the metal layer and electrically connected to the wiring pattern disposed above the metal layer in the insulating layer located immediately above the first and second layers having a shallow depth The wiring pattern disposed above the metal layer and the wiring pattern disposed below the metal layer are electrically connected via the second via. As a result, a sufficient contact area between the wiring pattern and the metal layer and the first and second vias can be ensured. Therefore, the wiring pattern disposed above the metal layer and the lower part of the metal layer It is possible to improve the reliability of electrical connection with the wiring pattern arranged on the board.

  According to another aspect of the present invention, a wiring having a laminated insulating layer, a wiring pattern provided in the laminated insulating layer, and a reinforcing metal layer provided between the laminated insulating layers. A semiconductor device comprising a substrate and a semiconductor chip disposed on the wiring substrate and electrically connected to the wiring pattern, wherein the metal layer is formed on the insulating layer located immediately below the metal layer. A first via which is electrically connected to the wiring pattern disposed below the metal layer and is in contact with the metal layer on the insulating layer located immediately above the metal layer In addition, a semiconductor device is provided in which a second via electrically connected to the wiring pattern disposed above the metal layer is provided.

  According to the present invention, the insulating layer located immediately below the metal layer is provided with the first via that is in contact with the metal layer and electrically connected to the wiring pattern disposed below the metal layer. By providing a second via in contact with the metal layer and electrically connected to the wiring pattern disposed above the metal layer in the insulating layer located immediately above the first and second layers having a shallow depth The wiring pattern disposed above the metal layer and the wiring pattern disposed below the metal layer are electrically connected via the second via. As a result, a sufficient contact area between the wiring pattern and the metal layer and the first and second vias can be ensured. Therefore, the wiring pattern disposed above the metal layer and the lower part of the metal layer It is possible to improve the reliability of electrical connection with the wiring pattern arranged on the board.

  According to another aspect of the present invention, a wiring pattern provided in a laminated insulating layer, a reinforcing metal layer provided between the laminated insulating layers, and the insulation located immediately below the metal layer A first via provided in a layer and electrically connected to the metal layer and the wiring pattern disposed below the metal layer; and provided in the insulating layer located immediately above the metal layer; A method of manufacturing a wiring board comprising a second via electrically connected to the wiring pattern disposed above the metal layer and the metal layer, wherein the first via and the metal layer are formed by electrolytic plating. There is provided a method for manufacturing a wiring board including a first via and metal layer forming step formed simultaneously.

  According to the present invention, the first via and the metal layer are simultaneously formed using the electrolytic plating method, whereby the manufacturing process can be simplified and the manufacturing cost of the wiring board can be reduced.

  ADVANTAGE OF THE INVENTION According to this invention, while suppressing the curvature of a wiring board, electrical connection reliability can be improved.

  Next, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention.

  A semiconductor device 10 according to the first embodiment of the present invention will be described with reference to FIG. The semiconductor device 10 includes a wiring board 11, an external connection terminal 12, a first semiconductor chip 14, a second semiconductor chip 15, and a sealing resin 16.

  The wiring board 11 includes insulating layers 18, 26, 32, and 38, a pad 19, protective films 20 and 49, a wiring pattern 21, a reinforcing metal layer 27, a first via 28, and a second via. A via 33 and a diffusion prevention film 51 are provided.

  The insulating layers 18, 26, 32 and 38 are laminated in the order of the insulating layer 18, the insulating layer 26, the insulating layer 32, and the insulating layer 38. As the insulating layers 18, 26, 32, and 38, for example, epoxy resin, polyimide resin, or the like can be used. Moreover, the thickness of the insulating layers 18, 26, 32, and 38 can be set to, for example, 30 μm to 50 μm, respectively.

  The pad 19 is provided on the lower surface 18 </ b> B side of the insulating layer 18 while being exposed from the insulating layer 18. The surface 19A of the pad 19 exposed from the insulating layer 18 is substantially flush with the lower surface 18B of the insulating layer 18. The pad 19 is electrically connected to the external connection terminal 12 and the via 22. As the pad 19, a Ni / Pd / Au laminated film in which an Ni layer, a Pd layer, and an Au layer are sequentially laminated from the insulating layer 18 can be used.

  The protective film 20 is provided so as to cover the lower surface 18B of the insulating layer 18 with the pad 19 exposed. As the protective film 20, for example, a solder resist can be used. The thickness of the protective film 20 can be set to 20 μm, for example.

  The wiring pattern 21 is disposed above and below the metal layer 27. The wiring pattern 21 has vias 22, 39, 41 and wirings 24, 35, 36, 43, 46.

  The via 22 is provided so as to penetrate the insulating layer 18 located on the pad 19. The via 22 is electrically connected to the pad 19 and the wiring 24. The wiring 24 is provided on the upper surface 18A of the insulating layer 18. The wiring 24 is electrically connected to the via 22 and the first via 28. The via 22 and the wiring 24 are the wiring pattern 21 disposed below the metal layer 27.

  The wiring 35 is provided on the insulating layer 32. The wiring 35 is electrically connected to the second via 33 and the via 39. The wiring 36 is provided on the insulating layer 32 located inside the position where the wiring 35 is formed. The wiring 36 is electrically connected to the second via 33 and the via 41. The via 39 is provided so as to penetrate the insulating layer 38 located on the wiring 35. The via 39 is electrically connected to the wirings 35 and 43.

  The via 41 is provided so as to penetrate the insulating layer 38 located on the wiring 36. The via 41 is electrically connected to the wirings 36 and 46. The wiring 43 has a connection portion 44 and is provided on the insulating layer 38. The connection portion 44 is for electrically connecting the wire 63. The wiring 43 is electrically connected to the via 39 and the wire 63.

  The wiring 46 has a connection portion 47 and is provided on the insulating layer 38. The connection portion 47 is for flip-chip connection of the first semiconductor chip 14. The wiring 46 is electrically connected to the first semiconductor chip 14 and the via 41. The wirings 35, 36, 43, 46 and the vias 39, 41 are the wiring pattern 21 arranged above the metal layer 27.

  As the material of the wiring pattern 21 configured as described above, a conductive metal can be used. As the conductive metal, for example, Cu can be used. The thickness of the wirings 24, 35, 36, 43, and 46 can be set to 20 μm, for example.

  The reinforcing metal layer 27 has a thin plate shape and is provided on the insulating layer 26 located approximately in the middle of the stacked insulating layers 18, 26, 32, and 38. The metal layer 27 is a layer for suppressing warping of the wiring board 11. The metal layer 27 can be formed by, for example, an electrolytic plating method. As a material of the metal layer 27, for example, Cu, Ni, Co, Fe, Ni—Co alloy, Ni—Fe alloy, or the like can be used. The thickness of the metal layer 27 can be, for example, 10 μm to 30 μm.

  The first via 28 is provided so as to penetrate the insulating layer 26 (insulating layer located immediately below the metal layer 27) located between the wiring 24 and the metal layer 27. The first via 28 is in contact with the metal layer 27 and is electrically connected to the wiring 24 and the metal layer 27. The first via 28 electrically connects the wiring pattern 21 (specifically, the via 22 and the wiring 24) disposed below the metal layer 27 and the metal layer 27. The first via 28 electrically connects the wiring 208 disposed below the metal layer 211 and the wiring 214 disposed above the metal layer 211 shown in FIG. 1 (conventional example). This via is shallower than the via 212 in FIG. The depth of the first via 28 is approximately half that of the conventional via 212. As a material of the first via 28, for example, Cu, Ni, Co, Fe, Ni—Co alloy, Ni—Fe alloy or the like can be used. The first via 28 is formed by forming an opening (opening 26A shown in FIG. 13) in the insulating layer 26 by laser processing and filling this opening with a conductive metal. The conductive metal constituting the first via 28 can be formed by, for example, an electrolytic plating method.

  The second via 33 is provided so as to penetrate the insulating layer 32 (insulating layer positioned immediately above the metal layer 27) located between the metal layer 27 and the wirings 35 and 36. The second via 33 is in contact with the metal layer 27 and is electrically connected to the wirings 35 and 36 and the metal layer 27. The second via 33 is electrically connected between the metal layer 27 and the wiring pattern 21 (specifically, the wirings 35, 36, 43, 46 and vias 39, 41) disposed above the metal layer 27. Connected. The second via 33 is disposed so as to face the first via 28 with the metal layer 27 interposed therebetween.

  Thus, by arranging the second via 33 so as to oppose the first via 28, the wiring pattern 21 (specifically, the via 22 and the wiring 24) arranged below the metal layer 27 can be obtained. The connection distance between the wiring pattern 21 (specifically, the wirings 35, 36, 43, and 46 and the vias 39 and 41) disposed above the metal layer 27 can be shortened.

  The second via 33 electrically connects the wiring 208 disposed below the metal layer 211 and the wiring 214 disposed above the metal layer 211 shown in FIG. 1 (conventional example). This via is shallower than the via 212 in FIG. The depth of the second via 33 is approximately half that of the conventional via 212. As a material of the second via 33, for example, a conductive metal can be used, and as the conductive metal, for example, Cu can be used. The second via 33 is formed by forming an opening (opening 32A shown in FIG. 18) in the insulating layer 32 by laser processing and filling the opening with a conductive metal. The conductive metal constituting the second via 33 can be formed by, for example, an electrolytic plating method.

  As described above, the insulating layer 26 located immediately below the metal layer 27 is in contact with the metal layer 27 and is disposed below the metal layer 27 (specifically, the via 22 and the wiring 24). A first via 28 that is electrically connected is provided, and an insulating layer 32 positioned immediately above the metal layer 27 is in contact with the metal layer 27 and is arranged above the metal layer 27 (specifically, The first and second vias 28, 33 having a shallow depth are provided by providing the second via 33 electrically connected to the wirings 35, 36, 43, 46 and the vias 39, 41). Thus, the wiring pattern 21 disposed above the metal layer 27 and the wiring pattern 21 disposed below the metal layer 27 are electrically connected. As a result, a sufficient contact area between the wiring pattern 21 and the metal layer 27 and the first and second vias 28 and 33 can be ensured. Therefore, the wiring pattern disposed above the metal layer 27. The electrical connection reliability between the wiring pattern 21 disposed under the metal layer 27 and the metal layer 27 can be improved.

  In addition, by arranging the second via 33 so as to face the first via 28, the wiring pattern 21 disposed below the metal layer 27 and the wiring pattern 21 disposed above the metal layer 27 The connection distance between can be shortened.

  The protective film 49 is provided on the insulating layer 38 so as to cover the wirings 43 and 46 other than the connection portions 44 and 47. As the protective film 49, for example, a solder resist can be used. The thickness of the protective film 49 can be set to 20 μm, for example.

  The diffusion prevention film 51 is a film for preventing the diffusion of Cu contained in the wiring 43 and improving the connection reliability between the wire 63 and the wiring 43. As the diffusion preventing film 51, for example, a Ni / Au laminated layer in which a Ni layer and an Au layer are laminated in this order on the wiring 43 can be used.

  The external connection terminal 12 is provided on the surface 19 </ b> A of the pad 19. The external connection terminal 12 is a terminal for connecting the semiconductor device 10 to a mounting substrate such as a mother board. As the external connection terminal 12, for example, a solder ball can be used.

  The first semiconductor chip 14 is disposed on the wiring board 11. The first semiconductor chip 14 has a chip body 53, electrode pads 54, and stud bumps 56. The chip body 53 includes a semiconductor substrate (not shown), a semiconductor element (not shown), and a multilayer wiring structure (not shown). A semiconductor substrate (not shown) is provided on the upper surface 53A side of the chip body. As the semiconductor substrate (not shown), for example, a Si substrate, a Ga-As substrate, or the like can be used. The semiconductor element (not shown) is an element such as a transistor, and is provided on a semiconductor substrate (not shown).

  The electrode pad 54 is provided on the lower surface 53 </ b> B side of the chip body 53. The electrode pad 54 is electrically connected to a semiconductor element (not shown) via a multilayer wiring structure (not shown).

  The stud bump 56 is provided on the electrode pad 54. The stud bump 56 is electrically connected to the connection portion 47 of the wiring 46 via the solder 57. As a result, the first semiconductor chip 14 is electrically connected to the wiring pattern 21. The stud bump 56 is for flip-chip connection of the first semiconductor chip 14 to the connection portion 47. As the stud bump 56, for example, an Au stud bump can be used.

  An underfill resin 58 is filled between the first semiconductor chip 14 and the wiring substrate 11. The underfill resin 58 is a resin for improving the bonding strength between the first semiconductor chip 14 and the wiring substrate 11.

  The second semiconductor chip 15 is bonded onto the first semiconductor chip 14 with an adhesive 62. The second semiconductor chip 15 is a semiconductor chip having an outer shape smaller than that of the first semiconductor chip 14, and includes a chip body 59 and electrode pads 61. The chip body 59 has a semiconductor substrate (not shown), a semiconductor element (not shown), and a multilayer wiring structure (not shown). The semiconductor substrate (not shown) is provided on the lower surface 59B side of the chip body 59. As the semiconductor substrate (not shown), for example, a Si substrate, a Ga-As substrate, or the like can be used. The semiconductor element (not shown) is an element such as a transistor, and is provided on a semiconductor substrate (not shown).

  The electrode pad 61 is provided on the upper surface 59 </ b> A side of the chip body 59. The electrode pad 61 is electrically connected to a semiconductor element (not shown) via a multilayer wiring structure (not shown). The electrode pad 61 is electrically connected (wire bonding connection) to the wiring pattern 21 via the wire 63.

  One end of the wire 63 is connected to the electrode pad 61, and the other end is electrically connected to the diffusion prevention film 51. The sealing resin 16 is provided on the wiring substrate 11 and seals the first and second semiconductor chips 14 and 15 and the wire 63. For example, an epoxy resin can be used as the sealing resin 16.

  According to the semiconductor device of the present embodiment, the wiring pattern 21 (specifically, the insulating layer 26 positioned immediately below the metal layer 27 is in contact with the metal layer 27 and disposed below the metal layer 27). A first via 28 electrically connected to the via 22 and the wiring 24) is provided, and the insulating layer 32 positioned immediately above the metal layer 27 is in contact with the metal layer 27 and disposed above the metal layer 27. By providing the second via 33 that is electrically connected to the wiring pattern 21 (specifically, the wirings 35, 36, 43, and 46 and the vias 39 and 41), the first and second shallow depths are provided. The wiring pattern 21 disposed above the metal layer 27 and the wiring pattern 21 disposed below the metal layer 27 are electrically connected via the two vias 28 and 33. As a result, a sufficient contact area between the wiring pattern 21 and the metal layer 27 and the first and second vias 28 and 33 can be ensured. Therefore, the wiring pattern disposed above the metal layer 27. The electrical connection reliability between the wiring pattern 21 disposed under the metal layer 27 and the metal layer 27 can be improved.

  In addition, by arranging the second via 33 so as to face the first via 28, the wiring pattern 21 disposed below the metal layer 27 and the wiring pattern 21 disposed above the metal layer 27 The connection distance between can be shortened.

  3 to 28 are views showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention. 3 to 28, the same components as those of the semiconductor device 10 according to the first embodiment are denoted by the same reference numerals. 3 to 27, E indicates a region where the semiconductor device 10 is formed (hereinafter referred to as “semiconductor device formation region E”).

  A method for manufacturing the semiconductor device 10 according to the first embodiment will be described with reference to FIGS. 3 to 28, a case where a plurality of semiconductor devices 10 are manufactured on the support plate 71 will be described as an example.

  First, in the step shown in FIG. 3, the protective film 20 having the opening 20A is formed on the support plate 71 made of a conductive metal. The support plate 71 is a support plate capable of manufacturing a plurality of semiconductor devices 10. As the support plate 71, for example, a metal plate such as Cu or a metal foil can be used. The opening 20A corresponds to the position where the pad 19 is formed. The protective film 20 can be formed by, for example, a printing method. As the protective film 20, for example, a solder resist can be used. Moreover, the thickness of the protective film 20 can be 20 micrometers, for example.

  Specifically, for example, the protective film 20 is formed by applying a solder resist on the Cu plate by a printing method, and then exposing and developing the solder resist corresponding to the formation position of the opening 20A.

  Next, in the step shown in FIG. 4, a conductive metal 72 for adjusting the position of the pad 19 in the height direction is formed in the opening 20A. For example, Cu can be used as the conductive metal 72. Specifically, the conductive metal 72 is deposited and grown in the opening 20A by an electrolytic plating method using the support plate 71 as a power feeding layer.

  Next, as shown in FIG. 5, the pad 19 is formed on the conductive metal 72. As the pad 19, for example, a Ni / Pd / Au laminated film in which an Au layer, a Pd layer, and a Ni layer are sequentially laminated on the conductive metal 72 can be used. Specifically, an Au layer, a Pd layer, and a Ni layer are sequentially laminated on the conductive metal 72 by an electrolytic plating method to form the pad 19.

Next, in the step shown in FIG. 6, the insulating layer 18 is formed so as to cover the pad 19 and the protective film 20. The insulating layer 18 can be formed by, for example, a printing method or a lamination of resin films.
As the insulating layer 18, for example, an epoxy resin, a polyimide resin, or the like can be used. The thickness of the insulating layer 18 on the protective film 20 can be set to 30 μm to 50 μm, for example.

  Next, in a step shown in FIG. 7, an opening 18C that exposes the pad 19 is formed in the insulating layer 18 by laser processing. Next, in the step shown in FIG. 8, the seed layer 74 is formed so as to cover the opening 18 </ b> C and the upper surface 18 </ b> A of the insulating layer 18. The seed layer 74 can be formed by an electroless plating method, a sputtering method, a vacuum evaporation method, or the like. As a material of the seed layer 74, for example, Cu or Ni can be used.

  Next, in a process shown in FIG. 9, a resist film 75 having an opening 75A exposing the seed layer 74 is formed on the structure shown in FIG. The opening 75 </ b> A corresponds to the shape and formation position of the wiring 24.

  Next, in a step shown in FIG. 10, a conductive metal 77 is formed on the seed layer 74 exposed in the opening 75A of the resist film 75 by an electrolytic plating method using the seed layer 74 as a power feeding layer. As a result, the via 22 made of the seed layer 74 and the conductive metal 77 is formed in the opening 18 </ b> C, and the wiring 24 made of the seed layer 74 and the conductive metal 77 is formed on the insulating layer 18.

  At this stage, the plurality of wirings 24 are electrically connected to the adjacent wirings 24 by the seed layer 74 formed on the insulating layer 18. As the conductive metal 77, for example, Cu can be used. Further, the thickness of the wiring 24 can be set to 20 μm, for example.

  Next, in the step shown in FIG. 11, the resist film 75 is removed. Next, in the step shown in FIG. 12, the unnecessary seed layer 74 not covered with the conductive metal 77 is removed by etching. As a result, the plurality of wirings 24 are electrically separated from other adjacent wirings 24.

  Next, in a process shown in FIG. 13, an insulating layer 26 having an opening 26A exposing the upper surface of the wiring 24 is formed on the structure shown in FIG. The opening 26 </ b> A corresponds to the shape and formation position of the first via 28. The insulating layer 26 can be formed by, for example, a printing method or a lamination of resin films. As the insulating layer 26, for example, an epoxy resin, a polyimide resin, or the like can be used. The thickness of the insulating layer 26 on the insulating layer 18 can be set to 30 μm to 50 μm, for example.

  Next, in the step shown in FIG. 14, a seed layer 79 is formed so as to cover the opening 26 </ b> A and the upper surface of the insulating layer 26. The seed layer 79 can be formed by an electroless plating method, a sputtering method, a vacuum evaporation method, or the like. As a material of the seed layer 79, for example, Cu, Ni or the like can be used.

  Next, in a step shown in FIG. 15, a resist film 80 having an opening 80A exposing the seed layer 79 is formed on the structure shown in FIG. The opening 80 </ b> A corresponds to the shape and formation position of the metal layer 27.

  Next, in the step shown in FIG. 16, a conductive metal 82 is formed on the seed layer 79 exposed in the opening 80A of the resist film 80 by electrolytic plating using the seed layer 79 as a power feeding layer (first via and Metal layer forming step). As a result, the first via 28 made of the seed layer 79 and the conductive metal 82 and the metal layer 27 made of the seed layer 79 and the conductive metal 82 are simultaneously formed. As the conductive metal 82, for example, Cu, Ni, Co, Fe, Ni—Co alloy, Ni—Fe alloy, or the like can be used. Moreover, the thickness of the metal layer 27 can be 10 micrometers-30 micrometers, for example.

  Thus, since the manufacturing process is simplified by simultaneously forming the first via 28 and the metal layer 27 by electrolytic plating, the manufacturing cost of the semiconductor device 10 and the wiring substrate 11 can be reduced. it can.

  Further, by forming the metal layer 27 by the electrolytic plating method, the thickness of the metal layer 27 can be easily adjusted to a desired thickness.

  Next, in the step shown in FIG. 17, the resist film 80 is removed, and then the unnecessary seed layer 79 not covered with the conductive metal 82 is removed. Thereby, the metal layer 27 portion in contact with the first and second vias 28 and 33 is electrically separated from the other metal layer 27 portions.

  Next, in the step shown in FIG. 18, an insulating layer having an opening 32A exposing the metal layer 27 on the structure shown in FIG. 17 by the same method as the steps shown in FIGS. 32 is formed. The opening 32 </ b> A is for disposing the second via 33 and corresponds to the shape and formation position of the second via 33. The opening 32A is formed so as to face the first via 28 using, for example, laser processing.

  In this way, when the opening 32A in which the second via 33 is disposed is formed so as to face the first via 28, the laser penetrates the metal layer 27 when forming the opening 32A. However, it is possible to stop the bottom surface and the side wall of the opening 32 </ b> A within the first via 28. Thereby, the electrical connection between the first via 28 and the second via 33 is ensured, and the yield of the wiring board 11 can be improved.

  The insulating layer 32 can be formed by, for example, a printing method or a lamination of resin films. As the insulating layer 32, for example, an epoxy resin, a polyimide resin, or the like can be used. The thickness of the insulating layer 32 on the insulating layer 26 can be, for example, 30 μm to 50 μm.

  Subsequently, the second via 33 made of the seed layer 83 and the conductive metal 84 and the wirings 35 and 36 made of the seed layer 83 and the conductive metal 84 are formed by the same method as the steps of FIGS. Are simultaneously formed (second via formation step). As a material of the seed layer 83, for example, Cu, Ni or the like can be used. For example, Cu can be used as the conductive metal 84. Moreover, the thickness of the wirings 35 and 36 can be 20 micrometers, for example.

  Next, in the step shown in FIG. 19, the insulating layer 38 having the openings 38A and 38B is formed on the structure shown in FIG. 18 by the same method as the steps shown in FIGS. The opening 38 </ b> A corresponds to the shape and formation position of the via 39, and is used for disposing the via 39. The opening 38A is formed so that the upper surface of the wiring 35 is exposed. The opening 38B corresponds to the shape and formation position of the via 41, and is used for disposing the via 41. The opening 38B is formed so that the upper surface of the wiring 36 is exposed. The insulating layer 38 can be formed by, for example, a printing method or lamination of resin films. As the insulating layer 38, for example, an epoxy resin, a polyimide resin, or the like can be used. The thickness of the insulating layer 38 on the insulating layer 32 can be, for example, 30 μm to 50 μm.

  Subsequently, the vias 39 and 41 made of the seed layer 86 and the conductive metal 87 and the wirings 43 and 46 made of the seed layer 86 and the conductive metal 87 are formed by a method similar to the process of FIGS. Form at the same time. As a material of the seed layer 86, for example, Cu, Ni or the like can be used. Further, as the conductive metal 87, for example, Cu can be used. The thickness of the wirings 43 and 46 can be set to 20 μm, for example.

  Next, in the step shown in FIG. 20, a protective film 49 is formed on the insulating layer 38 so as to cover the wirings 43 and 46 other than the connection portions 44 and 47. The protective film 49 can be formed by, for example, a printing method. As the protective film 49, for example, a solder resist can be used. The thickness of the protective film 49 can be set to 20 μm, for example. Next, in a step shown in FIG. 21, a resist film 89 having an opening 89A that exposes only the connection portion 44 is formed on the structure shown in FIG.

  Next, in the step shown in FIG. 22, the diffusion prevention film 51 is formed on the connection portion 44 by electrolytic plating using the wiring 43 as a power feeding layer. As the diffusion preventing film 51, for example, a Ni / Au laminated film in which a Ni layer and an Au layer are laminated in this order on the connection portion 44 can be used.

  Next, in the step shown in FIG. 23, the resist film 89 is removed. Next, in the step shown in FIG. 24, the support plate 71 and the conductive metal 72 are removed by etching. Thereby, the wiring board 11 is manufactured.

  Next, in the process shown in FIG. 25, solder 57 is applied on the connecting portion 47 and the solder 57 is melted, and then the stud bump 56 is brought into contact with the connecting portion 47 to connect the stud bump 56 and the connecting portion 47. . As a result, the first semiconductor chip 14 is flip-chip connected to the wiring substrate 11. Subsequently, an underfill resin 58 is filled between the first semiconductor chip 14 and the wiring substrate 11.

  Next, in the process shown in FIG. 26, the second semiconductor chip 15 is bonded onto the first semiconductor chip 14 by the adhesive 62. Subsequently, a wire 63 that electrically connects the electrode pad 61 and the diffusion prevention film 51 is formed. As a result, the second semiconductor chip 15 is connected to the wiring substrate 11 by wire bonding.

  Next, in a step shown in FIG. 27, a sealing resin 16 is formed on the structure shown in FIG. 26 so as to seal the first and second semiconductor chips 14 and 15 and the wire 63. The sealing resin 16 can be formed by, for example, a transfer mold method. For example, an epoxy resin can be used as the sealing resin 16.

  Next, in the process shown in FIG. 28, the external connection terminals 12 are formed on the pads 19, and then, by dicing, the sealing resin 16 and the insulating layers 18, corresponding to the outer position (see FIG. 27) of the semiconductor device formation region E, A plurality of semiconductor devices 10 are manufactured by cutting 26, 32 and 38.

  According to the manufacturing method of the present embodiment, the first via 28 and the metal layer 27 are simultaneously formed by using an electrolytic plating method, thereby simplifying the manufacturing process, and the semiconductor device 10 and the wiring substrate 11. Manufacturing cost can be reduced.

  Further, by forming the opening 32A in which the second via 33 is disposed so as to face the first via 28, the opening is opened in the first via 28 even when the laser penetrates the metal layer 27. Since the bottom surface and the side wall of the portion 32A can be stopped, electrical connection between the first via 28 and the second via 33 is ensured, and the yield of the wiring board 11 can be improved. .

  The support plate 71 and the conductive metal 72 may be removed after the first and second semiconductor chips 14 and 15 are mounted on the wiring substrate 11 and the sealing resin 16 is formed.

(Second Embodiment)
FIG. 29 is a sectional view of a semiconductor device according to the second embodiment of the present invention. In FIG. 29, the same components as those of the semiconductor device 10 of the first embodiment are denoted by the same reference numerals.

  A semiconductor device 95 according to the second embodiment of the present invention will be described with reference to FIG. The semiconductor device 95 includes an external connection terminal 12, a first semiconductor chip 14, a second semiconductor chip 15, a sealing resin 16, and a wiring substrate 96 including a metal layer 97. The semiconductor device 95 is configured in the same manner as the semiconductor device 10 except that a metal layer 97 is provided instead of the metal layer 27 provided in the semiconductor device 10 of the first embodiment.

  FIG. 30 is a plan view of the metal layer corresponding to region A shown in FIG.

  Referring to FIGS. 29 and 30, the metal layer 97 is provided on the insulating layer 26. The metal layer 97 is configured in the same manner as the metal layer 27 described in the first embodiment except that the metal layer 97 has a plurality of through holes 97A (first through holes). The plurality of through holes 97 </ b> A are formed over the entire surface of the metal layer 97. The plurality of through holes 97A can be arranged in a staggered pattern or a grid pattern, for example. FIG. 30 illustrates a case where a plurality of through holes 97A are arranged in a staggered manner. The through-hole 97A can be formed in a shape such as a cylinder or a quadrangular prism, for example. When the shape of the through hole 97A is a cylinder, the diameter of the through hole 97A can be, for example, 30 μm to 300 μm.

  According to the semiconductor device of the present embodiment, the metal layer 97 having a plurality of through holes 97A is provided on the insulating layer 26 instead of the metal layer 27, so that the inside of the plurality of through holes 97A is filled with the insulating layer 32. Thus, the contact area between the insulating layer 26 and the insulating layer 32 can be increased, and the adhesion between the insulating layers 26 and 32 can be improved.

  Further, the plurality of through holes 97A can be used as gas vent holes for releasing gas generated from the insulating layers 18, 26, 32, and 38 during manufacturing.

  31 and 32 are views showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention. FIG. 33 is a plan view of a resist film corresponding to the region D shown in FIG. 31 to 33, the same components as those of the semiconductor device 95 of the second embodiment are denoted by the same reference numerals.

  With reference to FIGS. 31 to 33, a method of manufacturing the semiconductor device 95 according to the second embodiment of the present invention will be described.

  First, the structure shown in FIG. 14 is formed by the same method as the steps shown in FIGS. 3 to 14 described above. Next, in a step shown in FIG. 31, a resist pattern 99 having first and second patterns 99A and 99B is formed on the structure shown in FIG. 14 (see FIG. 33). The first pattern 99 </ b> A is a pattern corresponding to the outer position of the metal layer 97. The second pattern 99B is a pattern corresponding to the shape and formation position of the through hole 97A.

  Next, in a step shown in FIG. 32, a conductive metal 82 is formed on the seed layer 79 exposed from the resist pattern 99 by an electrolytic plating method using the seed layer 79 as a power feeding layer. As a result, the first via 28 made of the seed layer 79 and the conductive metal 82 and the metal layer 97 made of the seed layer 79 and the conductive metal 82 are simultaneously formed. The thickness of the metal layer 97 can be, for example, 10 μm to 30 μm.

  Thereafter, the semiconductor device 95 is manufactured by performing the same processing as the steps shown in FIGS.

  According to the manufacturing method of the present embodiment, the manufacturing process is simplified by simultaneously forming the first via 28 and the metal layer 97 by the electrolytic plating method. Manufacturing cost can be reduced. Further, by forming the metal layer 27 by the electrolytic plating method, the metal layer 97 can be easily adjusted to have a desired thickness.

(Third embodiment)
FIG. 34 is a cross-sectional view of a semiconductor device according to the third embodiment of the present invention. In FIG. 34, B indicates a region (hereinafter referred to as “mounting region B”) on which the first and second semiconductor chips 14 and 15 of the wiring substrate 106 are mounted. In FIG. 34, the same components as those of the semiconductor device 95 of the second embodiment are denoted by the same reference numerals.

  A semiconductor device 105 according to the third embodiment of the present invention will be described with reference to FIG. The semiconductor device 105 includes an external connection terminal 12, a first semiconductor chip 14, a second semiconductor chip 15, a sealing resin 16, and a wiring substrate 106 including a metal layer 107. The semiconductor device 105 is configured in the same manner as the semiconductor device 95 except that the metal layer 107 is provided instead of the metal layer 97 provided in the semiconductor device 95 of the second embodiment. The metal layer 107 is configured in the same manner as the metal layer 97 except that a plurality of through holes 97A are provided only in the metal layer 107 positioned outside the mounting region B of the first and second semiconductor chips 14 and 15. The

  According to the semiconductor device of the present embodiment, by providing a plurality of through holes 97A in the metal layer 107 located outside the mounting region B of the first and second semiconductor chips 14 and 15, Adhesion between the insulating layers 26 and 32 can be improved in a state where rigidity is ensured.

  In addition, since the rigidity of the wiring board 106 is ensured, the first and second semiconductor chips 14 and 15 can be accurately mounted on the wiring board 106.

  Note that the semiconductor device 105 of the present embodiment can be manufactured by a method similar to that of the semiconductor device 95 of the second embodiment.

(Fourth embodiment)
FIG. 35 is a sectional view of a semiconductor device according to the fourth embodiment of the present invention. In FIG. 35, C indicates a region of the metal layer 27 facing the first and second semiconductor chips 14 and 15 (hereinafter referred to as “opposing region C”). In FIG. 35, the same components as those of the semiconductor device 10 of the first embodiment are denoted by the same reference numerals.

  A semiconductor device 110 according to the fourth embodiment of the present invention will be described with reference to FIG. The semiconductor device 110 includes an external connection terminal 12, a first semiconductor chip 14, a second semiconductor chip 15, a sealing resin 16, a wiring substrate 111 including a metal layer 27 and a thermal expansion coefficient relaxation member 112. Have The semiconductor device 110 is configured in the same manner as the semiconductor device 10 except that a thermal expansion coefficient relaxation member 112 is further provided in the configuration of the semiconductor device 10 of the first embodiment.

  The thermal expansion coefficient relaxation member 112 is provided on the facing region C of the metal layer 27 facing the first and second semiconductor chips 14 and 15. The thermal expansion coefficient relaxation member 112 is a member having a thermal expansion coefficient substantially equal to that of the semiconductor substrate (not shown) of the first and second semiconductor chips 14 and 15. When the material of the metal layer 27 is Cu, as the material of the thermal expansion coefficient relaxation member 112, for example, Ni, Co, Fe, Ni, Ni—Fe, or the like can be used. Moreover, the thickness of the thermal expansion coefficient relaxation member 112 can be set to 10 μm to 20 μm, for example.

  According to the semiconductor device of the present embodiment, the semiconductor substrates (first and second semiconductor chips 14 and 15) on the opposing region C of the metal layer 27 facing the first and second semiconductor chips 14 and 15. By providing the thermal expansion coefficient relaxation member 112 having a thermal expansion coefficient substantially equal to that (not shown), the difference in thermal expansion coefficient between the first and second semiconductor chips 14 and 15 and the wiring substrate 111 is reduced. Therefore, warpage of the semiconductor device 110 can be suppressed. Furthermore, damage to the first and second semiconductor chips 14 and 15 can be prevented.

  36 to 38 are views showing manufacturing steps of the semiconductor device according to the fourth embodiment of the present invention. 36 to 38, the same components as those of the semiconductor device 110 described in the fourth embodiment are denoted by the same reference numerals.

  A method of manufacturing the semiconductor device 110 according to the fourth embodiment of the present invention will be described with reference to FIGS.

  First, the structure shown in FIG. 17 is formed by the same method as the steps shown in FIGS. 3 to 17 described above. 36, a resist film 114 having an opening 114A that exposes the opposing region C of the metal layer 27 is formed on the structure shown in FIG.

  Next, in the step shown in FIG. 37, the thermal expansion coefficient relaxation member 112 is formed on the opposing region C of the metal layer 27 by an electrolytic plating method using the metal layer 27 as a power feeding layer. When the material of the metal layer 27 is Cu, as the material of the thermal expansion coefficient relaxation member 112, for example, Ni, Co, Fe, Ni, Ni—Fe, or the like can be used. Moreover, the thickness of the thermal expansion coefficient relaxation member 112 can be set to 10 μm to 20 μm, for example.

  Next, in a step shown in FIG. 38, the resist film 114 is removed. Then, the semiconductor device 110 can be manufactured by performing the same process as the process of FIGS.

  In the present embodiment, the case where the thermal expansion coefficient relaxation member 112 is provided on the metal layer 27 has been described as an example. However, the thermal expansion coefficient relaxation member 112 is in contact with the lower surface of the metal layer 27. It may be provided. Furthermore, the thermal expansion coefficient relaxation member 112 may be provided in the insulating layers 18, 26, 32, 38 facing the semiconductor chips 14, 15.

(Fifth embodiment)
FIG. 39 is a cross-sectional view of a semiconductor device according to the fifth embodiment of the present invention. In FIG. 39, the same components as those of the semiconductor device 95 of the second embodiment are denoted by the same reference numerals.

  With reference to FIG. 39, a semiconductor device 115 according to a fifth embodiment of the present invention will be described. The semiconductor device 115 includes an external connection terminal 12, a first semiconductor chip 14, a second semiconductor chip 15, a sealing resin 16, a wiring substrate 116 including a metal layer 97 and a thermal expansion coefficient relaxing member 117. Have The semiconductor device 115 is configured in the same manner as the semiconductor device 95 except that a thermal expansion coefficient relaxation member 117 is further provided in the configuration of the semiconductor device 95 of the second embodiment.

  The thermal expansion coefficient relaxation member 117 is provided on the facing region C of the metal layer 97 facing the first and second semiconductor chips 14 and 15. The thermal expansion coefficient relaxation member 117 is a member having a thermal expansion coefficient substantially equal to that of the semiconductor substrates (not shown) of the first and second semiconductor chips 14 and 15, and includes a plurality of through holes 117A (second through holes). ). The plurality of through holes 117 </ b> A are arranged to face the through holes 97 </ b> A provided in the metal layer 97. The shape and diameter of the through hole 117A are configured to be substantially equal to the through hole 97A.

  When the material of the metal layer 97 is Cu, for example, Ni, Co, Fe, Ni, Ni—Fe, or the like can be used as the material of the thermal expansion coefficient relaxation member 117. Moreover, the thickness of the thermal expansion coefficient relaxation member 117 can be set to 10 μm to 20 μm, for example.

  According to the semiconductor device of the present embodiment, the through hole 117A facing the through hole 97A of the metal layer 97 is provided on the facing region C of the metal layer 97 facing the first and second semiconductor chips 14 and 15. In addition, by providing the thermal expansion coefficient relaxation member 117 having a thermal expansion coefficient substantially equal to that of the semiconductor substrate (not shown) provided in the first and second semiconductor chips 14 and 15, the warp of the semiconductor device 115 can be suppressed. At the same time, the adhesion between the insulating layers 26 and 32 can be improved.

  Further, by providing the plurality of through holes 97A and 117A, it is possible to release the gas generated from the insulating layers 18, 26, 32, and 38 at the time of manufacture.

  40 to 42 are views showing the manufacturing process of the semiconductor device according to the fifth embodiment of the invention, and FIG. 43 is a view of the structure shown in FIG. 40 to 43, the same components as those of the semiconductor device 115 described in the fifth embodiment are denoted by the same reference numerals.

  With reference to FIGS. 40 to 43, a method of manufacturing the semiconductor device 115 according to the fifth embodiment of the invention will be described.

  First, the structure shown in FIG. 32 is formed by the same method as the steps shown in FIGS. 3 to 14, 31, and 32 described above.

  Next, in the step shown in FIG. 40, the resist pattern 99 is removed. Next, in a step shown in FIG. 41, a resist having a first pattern 119A corresponding to the outer shape and formation position of the thermal expansion coefficient relaxation member 117 and a second pattern 119B corresponding to the shape and formation position of the through hole 117A. A pattern 119 is formed (see FIG. 43).

  Next, in the step shown in FIG. 42, the thermal expansion coefficient relaxation member 117 having the through hole 117A is formed on the opposing region C of the metal layer 97 by electrolytic plating using the metal layer 97 as a power feeding layer. When the material of the metal layer 97 is Cu, for example, Ni, Co, Fe, Ni, Ni—Fe, or the like can be used as the material of the thermal expansion coefficient relaxation member 117. Moreover, the thickness of the thermal expansion coefficient relaxation member 117 can be set to 10 μm to 20 μm, for example. Then, the semiconductor device 115 can be manufactured by performing the same process as the process of FIGS. 17 to 28 described above.

  In this embodiment, the case where the thermal expansion coefficient relaxation member 117 is provided on the metal layer 97 has been described as an example. However, the thermal expansion coefficient relaxation member 117 is in contact with the lower surface of the metal layer 97. It may be provided. Further, the thermal expansion coefficient relaxation member 117 may be provided in the insulating layers 18, 26, 32, 38 facing the semiconductor chips 14, 15.

(Sixth embodiment)
FIG. 44 is a sectional view of a semiconductor device according to the sixth embodiment of the present invention. In FIG. 44, the same symbols are affixed to the same constituent portions as those of the semiconductor device 105 of the third embodiment.

  With reference to FIG. 44, a semiconductor device 125 according to a sixth embodiment of the present invention will be described. The semiconductor device 125 includes an external connection terminal 12, a first semiconductor chip 14, a second semiconductor chip 15, a sealing resin 16, a wiring substrate 126 including a metal layer 107 and a thermal expansion coefficient relaxation member 112, Have The semiconductor device 125 is configured in the same manner as the semiconductor device 105 except that the configuration of the semiconductor device 105 of the third embodiment is further provided with the thermal expansion coefficient relaxation member 112 described in the fourth embodiment. .

  According to the semiconductor device of the present embodiment, the thermal expansion coefficient relaxation member 112 is formed on the metal layer 107 having a plurality of through holes 107A outside the mounting region B of the first and second semiconductor chips 14 and 15. Even in the semiconductor device 125 having such a configuration, the same effect as that of the semiconductor device 110 of the fourth embodiment can be obtained.

  The semiconductor device 125 can be manufactured by combining the manufacturing method of the semiconductor device 105 of the third embodiment and the manufacturing method of the fourth semiconductor device 110.

  In this embodiment, the case where the thermal expansion coefficient relaxation member 112 is provided on the metal layer 107 has been described as an example. However, the thermal expansion coefficient relaxation member 112 is in contact with the lower surface of the metal layer 107. It may be provided. Furthermore, the thermal expansion coefficient relaxation member 112 may be provided in the insulating layers 18, 26, 32, 38 facing the semiconductor chips 14, 15.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims. Deformation / change is possible.

  In the semiconductor devices 10, 95, 105, 110, 115, and 125 according to the first to sixth embodiments, the case where the solder balls are provided as the external connection terminals 12 on the pads 19 is described as an example. The first to sixth embodiments can also be applied to a PGA (Pin Grid Array) having pins instead of solder balls. The first to sixth embodiments can also be applied to an LGA (Land Grid Array) that does not include the external connection terminal 12. In the case of LGA (Land Grid Array), the pad 19 functions as the external connection terminal 12.

  Furthermore, the number of semiconductor chips mounted on the wiring boards 11, 96, 106, 111, 116, 126 shown in the first to sixth embodiments may be one or three or more.

  INDUSTRIAL APPLICABILITY The present invention can be applied to a wiring board, a semiconductor device, and a method for manufacturing a wiring board that can suppress warping of the wiring board and improve electrical connection reliability.

It is sectional drawing of the conventional coreless board | substrate. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 6 is a diagram (part 1) illustrating a manufacturing process of the semiconductor device according to the first embodiment of the invention; FIG. 8 is a diagram (part 2) for illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention; It is FIG. (The 3) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 4 is a diagram (part 4) illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention; It is FIG. (5) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (6) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (The 7) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (The 8) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (9) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (10) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (11) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (12) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (13) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (14) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (15) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (16) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (17) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (18) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (19) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (20) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (21) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (22) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (23) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (The 24) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (25) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (26) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a top view of the metal layer corresponding to the area | region A shown in FIG. It is FIG. (1) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is FIG. (2) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. FIG. 32 is a plan view of a resist film corresponding to a region D shown in FIG. 31. It is sectional drawing of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 4th Embodiment of this invention. It is FIG. (1) which shows the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention. It is FIG. (2) which shows the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention. It is FIG. (3) which shows the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 5th Embodiment of this invention. It is FIG. (1) which shows the manufacturing process of the semiconductor device which concerns on the 5th Embodiment of this invention. It is FIG. (2) which shows the manufacturing process of the semiconductor device which concerns on the 5th Embodiment of this invention. It is FIG. (3) which shows the manufacturing process of the semiconductor device which concerns on the 5th Embodiment of this invention. It is the figure which looked at the structure shown in FIG. It is sectional drawing of the semiconductor device which concerns on the 6th Embodiment of this invention.

Explanation of symbols

10, 95, 105, 110, 115, 125 Semiconductor device 11, 96, 106, 111, 116, 126 Wiring board 12 External connection terminal 14 First semiconductor chip 15 Second semiconductor chip 16 Sealing resin 18, 26, 32, 38 Insulating layer 18A, 53A, 59A Upper surface 18B, 53B, 59B Lower surface 18C, 20A, 26A, 32A, 38A, 38B, 75A, 80A, 89A, 97A, 114A Opening 19 Pad 19A Surface 20, 49 Protective film 21 Wiring pattern 22, 39, 41 Via 24, 35, 36, 43, 46 Wiring 27, 97, 107 Metal layer 28 First via 33 Second via 44, 47 Connection portion 51 Diffusion prevention film 53, 59 Chip body 54 , 61 Electrode pad 56 Stud bump 57 Solder 58 Underfill resin 62 Adhesion 63 Wire 71 Support plate 72, 77, 82, 84, 87 Conductive metal 74, 79, 83, 86 Seed layer 75, 80, 89, 114 Resist film 97A, 117A Through hole 99, 119 Resist pattern 99A, 119A First Pattern 99B, 119B Second pattern 112, 117 Thermal expansion coefficient relaxation member A, D region B Mounting region C Opposite region E Semiconductor device formation region

Claims (10)

A wiring board comprising a laminated insulating layer, a wiring pattern provided in the laminated insulating layer, and a reinforcing metal layer provided between the laminated insulating layers,
The insulating layer located immediately below the metal layer is provided with a first via that is in contact with the metal layer and electrically connected to the wiring pattern disposed below the metal layer;
The insulating layer located immediately above the metal layer is provided with a second via that is in contact with the metal layer and is electrically connected to the wiring pattern disposed above the metal layer. Wiring board.   The wiring substrate according to claim 1, wherein the second via is disposed so as to face the first via.   3. The wiring board according to claim 1, wherein a plurality of first through holes penetrating the metal layer are provided in the metal layer.   4. The thermal expansion coefficient relaxation member substantially equal to the thermal expansion coefficient of the semiconductor chip is provided in the insulating layer portion facing the mounted semiconductor chip. Wiring board.   The wiring board according to claim 4, wherein the thermal expansion coefficient relaxation member is provided in contact with the metal layer.   6. The wiring board according to claim 4, wherein the thermal expansion coefficient relaxation member is provided with a second through hole that penetrates the thermal expansion coefficient relaxation member and faces the first through hole. . A wiring board having a laminated insulating layer, a wiring pattern provided in the laminated insulating layer, and a reinforcing metal layer provided between the laminated insulating layers;
A semiconductor device comprising a semiconductor chip disposed on the wiring board and electrically connected to the wiring pattern,
The insulating layer located immediately below the metal layer is provided with a first via that is in contact with the metal layer and electrically connected to the wiring pattern disposed below the metal layer;
The insulating layer located immediately above the metal layer is provided with a second via that is in contact with the metal layer and is electrically connected to the wiring pattern disposed above the metal layer. A semiconductor device.   The semiconductor device according to claim 7, wherein the second via is disposed to face the first via. A wiring pattern provided on the laminated insulating layer; a reinforcing metal layer provided between the laminated insulating layers; and the metal layer and the metal provided on the insulating layer located immediately below the metal layer. A first via electrically connected to the wiring pattern disposed below the layer; and the insulating layer located immediately above the metal layer, and disposed above the metal layer and the metal layer. A method of manufacturing a wiring board comprising a second via electrically connected to the wiring pattern,
A method of manufacturing a wiring board, comprising: a first via and metal layer forming step of simultaneously forming the first via and metal layer by electrolytic plating.   The wiring according to claim 9, further comprising a second via forming step of forming the second via so as to face the first via after the first via and metal layer forming step. A method for manufacturing a substrate.

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