KR101850123B1 - 파이프라인 전력 게이팅 - Google Patents

파이프라인 전력 게이팅 Download PDF

Info

Publication number
KR101850123B1
KR101850123B1 KR1020147000438A KR20147000438A KR101850123B1 KR 101850123 B1 KR101850123 B1 KR 101850123B1 KR 1020147000438 A KR1020147000438 A KR 1020147000438A KR 20147000438 A KR20147000438 A KR 20147000438A KR 101850123 B1 KR101850123 B1 KR 101850123B1
Authority
KR
South Korea
Prior art keywords
power
source
storage elements
destination
gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020147000438A
Other languages
English (en)
Korean (ko)
Other versions
KR20140040207A (ko
Inventor
다니엘 더블유. 베일레이
아론 에스. 로져스
제임스 제이. 몬타나로
브래들리 지. 버게스
피터 제이. 하난
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20140040207A publication Critical patent/KR20140040207A/ko
Application granted granted Critical
Publication of KR101850123B1 publication Critical patent/KR101850123B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Sources (AREA)
  • Logic Circuits (AREA)
KR1020147000438A 2011-07-06 2012-07-05 파이프라인 전력 게이팅 Active KR101850123B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/176,842 2011-07-06
US13/176,842 US8736308B2 (en) 2011-07-06 2011-07-06 Pipeline power gating
PCT/US2012/045559 WO2013006702A1 (en) 2011-07-06 2012-07-05 Pipeline power gating

Publications (2)

Publication Number Publication Date
KR20140040207A KR20140040207A (ko) 2014-04-02
KR101850123B1 true KR101850123B1 (ko) 2018-04-19

Family

ID=46640093

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020147000438A Active KR101850123B1 (ko) 2011-07-06 2012-07-05 파이프라인 전력 게이팅

Country Status (6)

Country Link
US (1) US8736308B2 (enExample)
EP (1) EP2730027B1 (enExample)
JP (1) JP5799167B2 (enExample)
KR (1) KR101850123B1 (enExample)
CN (1) CN103650346B (enExample)
WO (1) WO2013006702A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9496851B2 (en) 2014-09-10 2016-11-15 Qualcomm Incorporated Systems and methods for setting logic to a desired leakage state
CN112100793B (zh) * 2019-05-31 2023-06-13 超威半导体(上海)有限公司 用于重定时流水线的基于条带的自选通

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1195902A2 (en) 2000-09-27 2002-04-10 Kabushiki Kaisha Toshiba Semiconductor integrated circuit with reduced leakage current
US20070024318A1 (en) 2005-07-29 2007-02-01 Sequence Design, Inc. Automatic extension of clock gating technique to fine-grained power gating
JP2007053680A (ja) 2005-08-19 2007-03-01 Toshiba Corp 半導体集積回路装置
JP2007335980A (ja) 2006-06-12 2007-12-27 Toshiba Corp 半導体集積回路装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980836A (en) 1988-10-14 1990-12-25 Compaq Computer Corporation Apparatus for reducing computer system power consumption
US6946869B2 (en) 2003-10-15 2005-09-20 International Business Machines Corporation Method and structure for short range leakage control in pipelined circuits
US7262631B2 (en) 2005-04-11 2007-08-28 Arm Limited Method and apparatus for controlling a voltage level
US7397271B2 (en) * 2005-08-19 2008-07-08 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device
US7295036B1 (en) 2005-11-30 2007-11-13 Altera Corporation Method and system for reducing static leakage current in programmable logic devices
US8527797B2 (en) * 2007-12-26 2013-09-03 Qualcomm Incorporated System and method of leakage control in an asynchronous system
US8266569B2 (en) 2010-03-05 2012-09-11 Advanced Micro Devices, Inc. Identification of critical enables using MEA and WAA metrics
US8436647B2 (en) 2011-07-06 2013-05-07 Advanced Micro Devices, Inc. Pipeline power gating for gates with multiple destinations

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1195902A2 (en) 2000-09-27 2002-04-10 Kabushiki Kaisha Toshiba Semiconductor integrated circuit with reduced leakage current
JP2002110920A (ja) 2000-09-27 2002-04-12 Toshiba Corp 半導体集積回路
US20070024318A1 (en) 2005-07-29 2007-02-01 Sequence Design, Inc. Automatic extension of clock gating technique to fine-grained power gating
JP2007053680A (ja) 2005-08-19 2007-03-01 Toshiba Corp 半導体集積回路装置
JP2007335980A (ja) 2006-06-12 2007-12-27 Toshiba Corp 半導体集積回路装置

Also Published As

Publication number Publication date
KR20140040207A (ko) 2014-04-02
US8736308B2 (en) 2014-05-27
WO2013006702A1 (en) 2013-01-10
EP2730027B1 (en) 2018-09-05
EP2730027A1 (en) 2014-05-14
CN103650346B (zh) 2017-11-17
US20130009697A1 (en) 2013-01-10
JP5799167B2 (ja) 2015-10-21
CN103650346A (zh) 2014-03-19
JP2014526175A (ja) 2014-10-02

Similar Documents

Publication Publication Date Title
US7323909B2 (en) Automatic extension of clock gating technique to fine-grained power gating
CN101185049B (zh) 存储信号值的电路、方法和数据处理装置
CN103684355B (zh) 门控时钟锁存器、其操作方法和采用其的集成电路
US7622955B2 (en) Power savings with a level-shifting boundary isolation flip-flop (LSIFF) and a clock controlled data retention scheme
KR20070026441A (ko) 상태 유지 플립-플롭 및 그를 포함하는 회로와, 전력 손실감소 방법
US20140068305A1 (en) Circuit system and semiconductor device
US9083337B2 (en) Multi-threshold sleep convention logic without nsleep
CN115114801A (zh) 一种工业用微控制器超低功耗优化设计方法
US8074086B1 (en) Circuit and method for dynamic in-rush current control in a power management circuit
Lin et al. Fine-grained power gating for leakage and short-circuit power reduction by using asynchronous-logic
US8436647B2 (en) Pipeline power gating for gates with multiple destinations
KR101850123B1 (ko) 파이프라인 전력 게이팅
US9348402B2 (en) Multiple critical paths having different threshold voltages in a single processor core
Chen et al. Self-super-cutoff power gating with state retention on a 0.3 V 0.29 fJ/cycle/gate 32b RISC core in 0.13 µm CMOS
Liu et al. New MTCMOS flip-flops with simple control circuitry and low leakage data retention capability
CN102224677B (zh) 电路的内部电荷转移
US20080030224A1 (en) Logic with state retentive sleep mode
US7447099B2 (en) Leakage mitigation logic
JP5627163B2 (ja) 動作モード及びスリープモードでのデータ保持方法および回路
Giacomotto et al. Energy efficiency of power-gating in low-power clocked storage elements
Tiwari et al. Power gating technique for reducing leakage power in digital asynchronous GasP circuits
Zhang et al. A new flip-flop based on multiple leakage reduction techniques
Patel et al. Low power SOC design Techniques
Kapilachander et al. Technical Study on low power VLSI methods
Shilpa et al. Clock Related Flip-Flop with Sleepy Transistor Merging For Power Saving

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20140107

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20170622

Comment text: Request for Examination of Application

PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20180131

PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20180412

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20180413

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20210324

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20220411

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20230411

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 20240411

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 20250407

Start annual number: 8

End annual number: 8