KR101840240B1 - 마이크로 전자 패키지 - Google Patents

마이크로 전자 패키지 Download PDF

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Publication number
KR101840240B1
KR101840240B1 KR1020147012161A KR20147012161A KR101840240B1 KR 101840240 B1 KR101840240 B1 KR 101840240B1 KR 1020147012161 A KR1020147012161 A KR 1020147012161A KR 20147012161 A KR20147012161 A KR 20147012161A KR 101840240 B1 KR101840240 B1 KR 101840240B1
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South Korea
Prior art keywords
semiconductor chip
microelectronic
package
terminal
substrate
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Expired - Fee Related
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KR1020147012161A
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English (en)
Korean (ko)
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KR20140084131A (ko
Inventor
리차드 드윗 크리스프
와엘 조니
벨가셈 하바
프랭크 람브레히트
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인벤사스 코포레이션
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Priority claimed from US13/439,286 external-priority patent/US8525327B2/en
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Publication of KR20140084131A publication Critical patent/KR20140084131A/ko
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Publication of KR101840240B1 publication Critical patent/KR101840240B1/ko
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
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    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
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    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/273—Interconnections for measuring or testing, e.g. probe pads
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
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    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
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    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/834—Interconnections on sidewalls of chips
    • H—ELECTRICITY
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/853—On the same surface
    • H10W72/859—Bump connectors and bond wires
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/865—Die-attach connectors and bond wires
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/874—On different surfaces
    • H10W72/879—Bump connectors and bond wires
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
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    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
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    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/961—Functions of bonds pads
    • H10W72/967—Multiple bond pads having different functions
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    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
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    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
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    • H10W90/231—Configurations of stacked chips the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure
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    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
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    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Memories (AREA)
  • Wire Bonding (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR1020147012161A 2011-10-03 2012-09-27 마이크로 전자 패키지 Expired - Fee Related KR101840240B1 (ko)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US201161542488P 2011-10-03 2011-10-03
US201161542553P 2011-10-03 2011-10-03
US61/542,553 2011-10-03
US61/542,488 2011-10-03
US201261600361P 2012-02-17 2012-02-17
US61/600,361 2012-02-17
US13/439,286 US8525327B2 (en) 2011-10-03 2012-04-04 Stub minimization for assemblies without wirebonds to package substrate
US13/439,286 2012-04-04
PCT/US2012/057554 WO2013052345A1 (en) 2011-10-03 2012-09-27 Stub minimization for assemblies without wirebonds to package substrate

Publications (2)

Publication Number Publication Date
KR20140084131A KR20140084131A (ko) 2014-07-04
KR101840240B1 true KR101840240B1 (ko) 2018-05-04

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KR1020147012161A Expired - Fee Related KR101840240B1 (ko) 2011-10-03 2012-09-27 마이크로 전자 패키지
KR1020147012162A Active KR101901218B1 (ko) 2011-10-03 2012-10-01 패키지 기판에 대한 와이어본드를 갖지 않는 어셈블리를 위한 스터브 최소화

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