KR101822238B1 - 반도체 장치의 제조 방법, 기판 처리 장치, 가스 공급 시스템, 프로그램, 삼차원 플래시 메모리, 다이내믹 랜덤 액세스 메모리 및 반도체 장치 - Google Patents

반도체 장치의 제조 방법, 기판 처리 장치, 가스 공급 시스템, 프로그램, 삼차원 플래시 메모리, 다이내믹 랜덤 액세스 메모리 및 반도체 장치 Download PDF

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KR101822238B1
KR101822238B1 KR1020150153316A KR20150153316A KR101822238B1 KR 101822238 B1 KR101822238 B1 KR 101822238B1 KR 1020150153316 A KR1020150153316 A KR 1020150153316A KR 20150153316 A KR20150153316 A KR 20150153316A KR 101822238 B1 KR101822238 B1 KR 101822238B1
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film
silicon
gas
seed layer
substrate
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KR1020150153316A
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Korean (ko)
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KR20160059952A (ko
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아츠시 모리야
나오하루 나카이소
유고 오리하시
고타로 무라카미
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가부시키가이샤 히다치 고쿠사이 덴키
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    • H01L21/205
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/02068Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/2018
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1434Memory
    • H01L2924/1435Random access memory [RAM]
    • H01L2924/1436Dynamic random-access memory [DRAM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1434Memory
    • H01L2924/1435Random access memory [RAM]
    • H01L2924/1438Flash memory

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical Vapour Deposition (AREA)
  • Recrystallisation Techniques (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
KR1020150153316A 2014-11-19 2015-11-02 반도체 장치의 제조 방법, 기판 처리 장치, 가스 공급 시스템, 프로그램, 삼차원 플래시 메모리, 다이내믹 랜덤 액세스 메모리 및 반도체 장치 KR101822238B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2014234401 2014-11-19
JPJP-P-2014-234401 2014-11-19
JP2015185891A JP6100854B2 (ja) 2014-11-19 2015-09-18 半導体装置の製造方法、基板処理装置、ガス供給システムおよびプログラム
JPJP-P-2015-185891 2015-09-18

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KR20160059952A KR20160059952A (ko) 2016-05-27
KR101822238B1 true KR101822238B1 (ko) 2018-01-25

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JP (1) JP6100854B2 (zh)
KR (1) KR101822238B1 (zh)
TW (1) TWI672800B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200030451A (ko) * 2018-09-12 2020-03-20 가부시키가이샤 코쿠사이 엘렉트릭 반도체 장치의 제조 방법, 기판 처리 장치 및 프로그램
KR20210092884A (ko) * 2020-01-17 2021-07-27 성균관대학교산학협력단 C-free 할로겐 기반의 가스를 이용한 실리콘 산화막 대비 높은 식각 선택비를 갖는 실리콘 질화막 건식 식각 방법

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6585551B2 (ja) * 2016-06-15 2019-10-02 株式会社Kokusai Electric 半導体装置の製造方法、基板処理装置、およびプログラム
KR101960763B1 (ko) * 2016-11-03 2019-03-21 주식회사 유진테크 저온 에피택셜층 형성방법
JP2018113322A (ja) 2017-01-11 2018-07-19 株式会社日立国際電気 半導体装置の製造方法、プログラムおよび基板処理装置
JP6778139B2 (ja) * 2017-03-22 2020-10-28 株式会社Kokusai Electric 半導体装置の製造方法、基板処理装置およびプログラム
JP6752357B2 (ja) * 2017-03-31 2020-09-09 株式会社Kokusai Electric 半導体装置の製造方法、基板処理装置およびプログラム
JP6777624B2 (ja) 2017-12-28 2020-10-28 株式会社Kokusai Electric 半導体装置の製造方法、基板処理装置、およびプログラム
JP7199286B2 (ja) * 2019-03-29 2023-01-05 東京エレクトロン株式会社 基板処理装置
JP7065818B2 (ja) 2019-10-28 2022-05-12 株式会社Kokusai Electric 半導体装置の製造方法、基板処理方法、基板処理装置、およびプログラム

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012029661A1 (ja) 2010-09-01 2012-03-08 株式会社日立国際電気 半導体装置の製造方法及び基板処理装置
JP2014067796A (ja) * 2012-09-25 2014-04-17 Hitachi Kokusai Electric Inc 半導体装置の製造方法及び基板処理装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4522662A (en) * 1983-08-12 1985-06-11 Hewlett-Packard Company CVD lateral epitaxial growth of silicon over insulators
JPS61179571A (ja) * 1984-09-27 1986-08-12 テキサス インスツルメンツ インコ−ポレイテツド メモリセルおよびそのアレイ
JPS62183508A (ja) * 1986-02-07 1987-08-11 Nippon Telegr & Teleph Corp <Ntt> 半導体基板およびその製造法
JPH0451565A (ja) * 1990-06-19 1992-02-20 Toshiba Corp 半導体記憶装置およびその製造方法
JP3403231B2 (ja) * 1993-05-12 2003-05-06 三菱電機株式会社 半導体装置およびその製造方法
JPH08204032A (ja) * 1995-01-20 1996-08-09 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP3382114B2 (ja) * 1997-02-27 2003-03-04 株式会社東芝 半導体装置及びその製造方法
FR2774509B1 (fr) * 1998-01-30 2001-11-16 Sgs Thomson Microelectronics Procede de depot d'une region de silicium monocristallin
JP3485081B2 (ja) * 1999-10-28 2004-01-13 株式会社デンソー 半導体基板の製造方法
US7202523B2 (en) * 2003-11-17 2007-04-10 Micron Technology, Inc. NROM flash memory devices on ultrathin silicon
JP2007317874A (ja) * 2006-05-25 2007-12-06 Toshiba Corp 不揮発性半導体記憶装置
JP4791949B2 (ja) * 2006-12-22 2011-10-12 株式会社東芝 不揮発性半導体メモリ
JP5023004B2 (ja) * 2008-06-30 2012-09-12 株式会社日立国際電気 基板処理方法及び基板処理装置
JP2010114360A (ja) * 2008-11-10 2010-05-20 Toshiba Corp 半導体装置及びその製造方法
JP5692763B2 (ja) * 2010-05-20 2015-04-01 東京エレクトロン株式会社 シリコン膜の形成方法およびその形成装置
JP5815443B2 (ja) * 2012-03-19 2015-11-17 株式会社日立国際電気 半導体装置の製造方法、基板処理方法および基板処理装置
WO2014070600A1 (en) * 2012-10-29 2014-05-08 Matheson Tri-Gas, Inc. Methods for selective and conformal epitaxy of highly doped si-containing materials for three dimensional structures
JP6068130B2 (ja) * 2012-12-25 2017-01-25 株式会社日立国際電気 半導体装置の製造方法、基板処理装置およびプログラム

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012029661A1 (ja) 2010-09-01 2012-03-08 株式会社日立国際電気 半導体装置の製造方法及び基板処理装置
JP2014067796A (ja) * 2012-09-25 2014-04-17 Hitachi Kokusai Electric Inc 半導体装置の製造方法及び基板処理装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200030451A (ko) * 2018-09-12 2020-03-20 가부시키가이샤 코쿠사이 엘렉트릭 반도체 장치의 제조 방법, 기판 처리 장치 및 프로그램
KR102401389B1 (ko) 2018-09-12 2022-05-24 가부시키가이샤 코쿠사이 엘렉트릭 반도체 장치의 제조 방법, 기판 처리 장치 및 프로그램
KR20210092884A (ko) * 2020-01-17 2021-07-27 성균관대학교산학협력단 C-free 할로겐 기반의 가스를 이용한 실리콘 산화막 대비 높은 식각 선택비를 갖는 실리콘 질화막 건식 식각 방법
KR102328573B1 (ko) 2020-01-17 2021-11-17 성균관대학교산학협력단 C-free 할로겐 기반의 가스를 이용한 실리콘 산화막 대비 높은 식각 선택비를 갖는 실리콘 질화막 건식 식각 방법

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TWI672800B (zh) 2019-09-21
JP2016105457A (ja) 2016-06-09
JP6100854B2 (ja) 2017-03-22
TW201637135A (zh) 2016-10-16
KR20160059952A (ko) 2016-05-27

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