KR101759689B1 - 절연층 및 보조층을 갖는 적층 칩셋 및 이를 형성하는 방법 - Google Patents

절연층 및 보조층을 갖는 적층 칩셋 및 이를 형성하는 방법 Download PDF

Info

Publication number
KR101759689B1
KR101759689B1 KR1020167009373A KR20167009373A KR101759689B1 KR 101759689 B1 KR101759689 B1 KR 101759689B1 KR 1020167009373 A KR1020167009373 A KR 1020167009373A KR 20167009373 A KR20167009373 A KR 20167009373A KR 101759689 B1 KR101759689 B1 KR 101759689B1
Authority
KR
South Korea
Prior art keywords
layer
circuit
insulating layer
semiconductor die
soi structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020167009373A
Other languages
English (en)
Korean (ko)
Other versions
KR20160044591A (ko
Inventor
쳉지에 주오
창한 윤
상준 박
치 ? 로
치 šœ 로
마리오 에프. 베레즈
종해 김
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20160044591A publication Critical patent/KR20160044591A/ko
Application granted granted Critical
Publication of KR101759689B1 publication Critical patent/KR101759689B1/ko
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00Three-dimensional [3D] integrated devices
    • H01L27/0688
    • H01L21/8238
    • H01L24/28
    • H01L24/31
    • H01L27/0826
    • H01L2924/1461
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Micromachines (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Laminated Bodies (AREA)
KR1020167009373A 2011-11-16 2012-11-16 절연층 및 보조층을 갖는 적층 칩셋 및 이를 형성하는 방법 Expired - Fee Related KR101759689B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201161560471P 2011-11-16 2011-11-16
US61/560,471 2011-11-16
US13/356,717 US9496255B2 (en) 2011-11-16 2012-01-24 Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same
US13/356,717 2012-01-24
PCT/US2012/065644 WO2013075007A1 (en) 2011-11-16 2012-11-16 Stacked chipset having an insulating layer and a secondary layer and method of forming same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
KR1020147016198A Division KR20140100526A (ko) 2011-11-16 2012-11-16 절연층 및 보조층을 갖는 적층 칩셋 및 이를 형성하는 방법

Publications (2)

Publication Number Publication Date
KR20160044591A KR20160044591A (ko) 2016-04-25
KR101759689B1 true KR101759689B1 (ko) 2017-07-19

Family

ID=48280458

Family Applications (2)

Application Number Title Priority Date Filing Date
KR1020167009373A Expired - Fee Related KR101759689B1 (ko) 2011-11-16 2012-11-16 절연층 및 보조층을 갖는 적층 칩셋 및 이를 형성하는 방법
KR1020147016198A Ceased KR20140100526A (ko) 2011-11-16 2012-11-16 절연층 및 보조층을 갖는 적층 칩셋 및 이를 형성하는 방법

Family Applications After (1)

Application Number Title Priority Date Filing Date
KR1020147016198A Ceased KR20140100526A (ko) 2011-11-16 2012-11-16 절연층 및 보조층을 갖는 적층 칩셋 및 이를 형성하는 방법

Country Status (7)

Country Link
US (1) US9496255B2 (https=)
EP (1) EP2780942A1 (https=)
JP (2) JP5937225B2 (https=)
KR (2) KR101759689B1 (https=)
CN (1) CN104054175B (https=)
IN (1) IN2014MN01027A (https=)
WO (1) WO2013075007A1 (https=)

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104058363B (zh) * 2013-03-22 2016-01-20 上海丽恒光微电子科技有限公司 基于mems透射光阀的显示装置及其形成方法
US9418985B2 (en) * 2013-07-16 2016-08-16 Qualcomm Incorporated Complete system-on-chip (SOC) using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) technology
US9032353B2 (en) 2013-10-10 2015-05-12 Taiwan Semiconductor Manufacturing Co., Ltd. Method and system for three-dimensional layout design of integrated circuit elements in stacked CMOS
US9257407B2 (en) * 2013-10-28 2016-02-09 Qualcomm Incorporated Heterogeneous channel material integration into wafer
US9443758B2 (en) * 2013-12-11 2016-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. Connecting techniques for stacked CMOS devices
KR102360695B1 (ko) 2014-01-23 2022-02-08 글로벌웨이퍼스 씨오., 엘티디. 고 비저항 soi 웨이퍼 및 그 제조 방법
US20160043108A1 (en) * 2014-08-07 2016-02-11 Silanna Semiconductor U.S.A., Inc. Semiconductor Structure with Multiple Active Layers in an SOI Wafer
US9786613B2 (en) * 2014-08-07 2017-10-10 Qualcomm Incorporated EMI shield for high frequency layer transferred devices
US9899499B2 (en) 2014-09-04 2018-02-20 Sunedison Semiconductor Limited (Uen201334164H) High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss
WO2016081367A1 (en) 2014-11-18 2016-05-26 Sunedison Semiconductor Limited HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED BY He-N2 CO-IMPLANTATION
JP6650463B2 (ja) 2014-11-18 2020-02-19 グローバルウェーハズ カンパニー リミテッドGlobalWafers Co.,Ltd. 電荷トラップ層を備えた高抵抗率の半導体・オン・インシュレーターウェハーの製造方法
JP6726180B2 (ja) 2014-11-18 2020-07-22 グローバルウェーハズ カンパニー リミテッドGlobalWafers Co.,Ltd. 高抵抗率半導体・オン・インシュレータウエハおよび製造方法
WO2016081363A1 (en) * 2014-11-18 2016-05-26 Sunedison Semiconductor Limited A system-on-chip on a semiconductor-on-insulator wafer and a method of manufacturing
EP4120320A1 (en) 2015-03-03 2023-01-18 GlobalWafers Co., Ltd. Charge trapping polycrystalline silicon films on silicon substrates with controllable film stress
CN107408532A (zh) 2015-03-17 2017-11-28 太阳能爱迪生半导体有限公司 用于绝缘体上半导体结构的制造的热稳定电荷捕获层
US9881832B2 (en) 2015-03-17 2018-01-30 Sunedison Semiconductor Limited (Uen201334164H) Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof
CN107873106B (zh) 2015-06-01 2022-03-18 环球晶圆股份有限公司 制造绝缘体上硅锗的方法
WO2016196060A1 (en) 2015-06-01 2016-12-08 Sunedison Semiconductor Limited A method of manufacturing semiconductor-on-insulator
US20160379943A1 (en) * 2015-06-25 2016-12-29 Skyworks Solutions, Inc. Method and apparatus for high performance passive-active circuit integration
US20170033135A1 (en) * 2015-07-28 2017-02-02 Skyworks Solutions, Inc. Integrated passive device on soi substrate
US9768109B2 (en) * 2015-09-22 2017-09-19 Qualcomm Incorporated Integrated circuits (ICS) on a glass substrate
JP6585978B2 (ja) * 2015-09-24 2019-10-02 ラピスセミコンダクタ株式会社 半導体装置および半導体装置の製造方法
JP6749394B2 (ja) 2015-11-20 2020-09-02 グローバルウェーハズ カンパニー リミテッドGlobalWafers Co.,Ltd. 滑らかな半導体表面の製造方法
US10256863B2 (en) * 2016-01-11 2019-04-09 Qualcomm Incorporated Monolithic integration of antenna switch and diplexer
US9831115B2 (en) 2016-02-19 2017-11-28 Sunedison Semiconductor Limited (Uen201334164H) Process flow for manufacturing semiconductor on insulator structures in parallel
US10622247B2 (en) 2016-02-19 2020-04-14 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a buried high resistivity layer
US10468294B2 (en) 2016-02-19 2019-11-05 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface
EP3758050A1 (en) 2016-03-07 2020-12-30 GlobalWafers Co., Ltd. Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof
WO2017155806A1 (en) 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof
WO2017155804A1 (en) 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Method of manufacturing a semiconductor on insulator structure by a pressurized bond treatment
US11114332B2 (en) 2016-03-07 2021-09-07 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof
CN111201341B (zh) 2016-06-08 2023-04-04 环球晶圆股份有限公司 具有经改进的机械强度的高电阻率单晶硅锭及晶片
US10269617B2 (en) 2016-06-22 2019-04-23 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising an isolation region
US20180068886A1 (en) * 2016-09-02 2018-03-08 Qualcomm Incorporated Porous semiconductor layer transfer for an integrated circuit structure
US9812580B1 (en) * 2016-09-06 2017-11-07 Qualcomm Incorporated Deep trench active device with backside body contact
EP4723861A2 (en) 2016-10-26 2026-04-08 GlobalWafers Co., Ltd. High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency
CN115714130A (zh) 2016-12-05 2023-02-24 环球晶圆股份有限公司 高电阻率绝缘体上硅结构及其制造方法
CN114093764B (zh) 2016-12-28 2025-07-22 太阳能爱迪生半导体有限公司 单晶硅晶片
JP6881066B2 (ja) * 2017-06-19 2021-06-02 大日本印刷株式会社 貫通電極基板および貫通電極基板の製造方法
SG11201913769RA (en) 2017-07-14 2020-01-30 Sunedison Semiconductor Ltd Method of manufacture of a semiconductor on insulator structure
JP7160943B2 (ja) 2018-04-27 2022-10-25 グローバルウェーハズ カンパニー リミテッド 半導体ドナー基板からの層移転を容易にする光アシスト板状体形成
JP2019212729A (ja) * 2018-06-04 2019-12-12 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
EP4210092A1 (en) 2018-06-08 2023-07-12 GlobalWafers Co., Ltd. Method for transfer of a thin layer of silicon
EP3675168A1 (en) * 2018-12-24 2020-07-01 IMEC vzw 3d power semiconductor device and system
FR3091004B1 (fr) * 2018-12-24 2020-12-04 Soitec Silicon On Insulator Structure de type semi-conducteur pour applications digitales et radiofréquences
JP2020141090A (ja) * 2019-03-01 2020-09-03 ソニーセミコンダクタソリューションズ株式会社 容量素子、半導体素子基板及び電子機器
KR102804065B1 (ko) 2020-07-13 2025-05-09 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
CN114122134B (zh) * 2020-09-01 2023-12-22 苏州华太电子技术股份有限公司 一种射频ldmos集成器件
US12412835B2 (en) * 2021-04-27 2025-09-09 Intel Corporation Back-side power delivery with glass support at the front
WO2022232533A1 (en) * 2021-04-30 2022-11-03 Qorvo Us, Inc. Vertically stacked mems device and controller device
DE102022211198A1 (de) * 2022-10-21 2024-05-02 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung eines mikromechanischen Bauelements

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6399997B1 (en) 2000-08-01 2002-06-04 Megic Corporation High performance system-on-chip using post passivation process and glass substrates
JP2004349513A (ja) 2003-05-22 2004-12-09 Seiko Epson Corp 薄膜回路装置及びその製造方法、並びに電気光学装置、電子機器
US20070228383A1 (en) 2006-03-31 2007-10-04 Kerry Bernstein 3-dimensional integrated circuit architecture, structure and method for fabrication thereof

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001102523A (ja) 1999-09-28 2001-04-13 Sony Corp 薄膜デバイスおよびその製造方法
TW548860B (en) 2001-06-20 2003-08-21 Semiconductor Energy Lab Light emitting device and method of manufacturing the same
JP4244120B2 (ja) 2001-06-20 2009-03-25 株式会社半導体エネルギー研究所 発光装置及びその作製方法
WO2004015764A2 (en) 2002-08-08 2004-02-19 Leedy Glenn J Vertical system integration
JP2004165269A (ja) 2002-11-11 2004-06-10 Canon Inc 積層形半導体装置
CN102290425B (zh) * 2004-08-20 2014-04-02 Kamiyacho知识产权控股公司 具有三维层叠结构的半导体器件的制造方法
US7179719B2 (en) 2004-09-28 2007-02-20 Sharp Laboratories Of America, Inc. System and method for hydrogen exfoliation
US20070207592A1 (en) 2006-03-03 2007-09-06 Lu James J Wafer bonding of damascene-patterned metal/adhesive redistribution layers
US20080128901A1 (en) * 2006-11-30 2008-06-05 Peter Zurcher Micro-electro-mechanical systems device and integrated circuit device integrated in a three-dimensional semiconductor structure
US20080149832A1 (en) * 2006-12-20 2008-06-26 Miguel Zorn Scanning Probe Microscope, Nanomanipulator with Nanospool, Motor, nucleotide cassette and Gaming application
JP2009067098A (ja) 2007-09-10 2009-04-02 Harison Toshiba Lighting Corp 照明装置
JP2009267098A (ja) * 2008-04-25 2009-11-12 Denso Corp 半導体装置及びその製造方法
US7943428B2 (en) * 2008-12-24 2011-05-17 International Business Machines Corporation Bonded semiconductor substrate including a cooling mechanism
US7943423B2 (en) 2009-03-10 2011-05-17 Infineon Technologies Ag Reconfigured wafer alignment
US9406561B2 (en) 2009-04-20 2016-08-02 International Business Machines Corporation Three dimensional integrated circuit integration using dielectric bonding first and through via formation last
JP2011029609A (ja) * 2009-06-26 2011-02-10 Semiconductor Energy Lab Co Ltd Soi基板の作製方法およびsoi基板
US9076664B2 (en) * 2011-10-07 2015-07-07 Freescale Semiconductor, Inc. Stacked semiconductor die with continuous conductive vias

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6399997B1 (en) 2000-08-01 2002-06-04 Megic Corporation High performance system-on-chip using post passivation process and glass substrates
JP2004349513A (ja) 2003-05-22 2004-12-09 Seiko Epson Corp 薄膜回路装置及びその製造方法、並びに電気光学装置、電子機器
US20070228383A1 (en) 2006-03-31 2007-10-04 Kerry Bernstein 3-dimensional integrated circuit architecture, structure and method for fabrication thereof

Also Published As

Publication number Publication date
KR20160044591A (ko) 2016-04-25
WO2013075007A1 (en) 2013-05-23
CN104054175B (zh) 2018-03-06
IN2014MN01027A (https=) 2015-05-01
JP6099794B2 (ja) 2017-03-22
JP2015503228A (ja) 2015-01-29
KR20140100526A (ko) 2014-08-14
JP5937225B2 (ja) 2016-06-22
US9496255B2 (en) 2016-11-15
JP2016174170A (ja) 2016-09-29
EP2780942A1 (en) 2014-09-24
CN104054175A (zh) 2014-09-17
US20130120951A1 (en) 2013-05-16

Similar Documents

Publication Publication Date Title
KR101759689B1 (ko) 절연층 및 보조층을 갖는 적층 칩셋 및 이를 형성하는 방법
US8148793B2 (en) Three dimensional integrated passive device and method of fabrication
US7663196B2 (en) Integrated passive device and method of fabrication
US11164891B2 (en) Integrated circuits with components on both sides of a selected substrate and methods of fabrication
US20200219861A1 (en) Front end system having an acoustic wave resonator (awr) on an interposer substrate
US11309352B2 (en) Integrated acoustic filter on complementary metal oxide semiconductor (CMOS) die
KR102675753B1 (ko) 후면 실리사이드화에 의한 벌크 층 전사 프로세싱
TWI756206B (zh) 使用壓電封裝積體切換裝置的可調射頻系統
KR20190072674A (ko) 듀얼-사이디드 프로세싱을 갖는 로직 회로 블록 레이아웃들
US20180068886A1 (en) Porous semiconductor layer transfer for an integrated circuit structure
JP5304398B2 (ja) 可変容量素子
WO2019132925A1 (en) Rf front end system with co-integrated acoustic wave resonator
KR20210052243A (ko) 고주파 모듈 및 통신 장치
TW202324918A (zh) 高諧波效能射頻濾波器
US12016247B2 (en) Package comprising an integrated passive device configured as a cap for a filter
JP2007000961A (ja) 半導体複合装置およびその製造方法
CN217216521U (zh) 一种混合叠放式滤波器芯片
JP2010239344A (ja) 無線回路モジュール
JP2024535779A (ja) マルチレベル積層音響波(aw)フィルタパッケージ及び関連する製造方法
TH2301002046A (th) วงจรแบบปรับได้ซึ่งรวมถึงวงจรฟิลเตอร์แบบบูรณาการที่คู่ควบกับค่าประจุแบบแปรผัน, และแพ็คเกจวงจรรวม (ไอซี) ที่เกี่ยวข้อง และวิธีการผลิต

Legal Events

Date Code Title Description
A107 Divisional application of patent
PA0104 Divisional application for international application

St.27 status event code: A-0-1-A10-A16-div-PA0104

St.27 status event code: A-0-1-A10-A18-div-PA0104

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
A302 Request for accelerated examination
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PA0302 Request for accelerated examination

St.27 status event code: A-1-2-D10-D16-exm-PA0302

St.27 status event code: A-1-2-D10-D17-exm-PA0302

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

Fee payment year number: 1

St.27 status event code: A-2-2-U10-U12-oth-PR1002

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

Fee payment year number: 4

St.27 status event code: A-4-4-U10-U11-oth-PR1001

PC1903 Unpaid annual fee

Not in force date: 20210714

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

St.27 status event code: A-4-4-U10-U13-oth-PC1903

PC1903 Unpaid annual fee

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20210714

St.27 status event code: N-4-6-H10-H13-oth-PC1903

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000