KR101746203B1 - 멀티 칩 시스템에서 칩들 간의 클럭 신호의 위상차 보상방법 및 장치 - Google Patents

멀티 칩 시스템에서 칩들 간의 클럭 신호의 위상차 보상방법 및 장치 Download PDF

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Publication number
KR101746203B1
KR101746203B1 KR1020140151527A KR20140151527A KR101746203B1 KR 101746203 B1 KR101746203 B1 KR 101746203B1 KR 1020140151527 A KR1020140151527 A KR 1020140151527A KR 20140151527 A KR20140151527 A KR 20140151527A KR 101746203 B1 KR101746203 B1 KR 101746203B1
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KR
South Korea
Prior art keywords
signal
chip
clock
receiving
phase
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KR1020140151527A
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English (en)
Korean (ko)
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KR20160053348A (ko
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황창익
천영일
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(주)에프씨아이
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Priority to KR1020140151527A priority Critical patent/KR101746203B1/ko
Priority to JP2014254699A priority patent/JP6013440B2/ja
Publication of KR20160053348A publication Critical patent/KR20160053348A/ko
Application granted granted Critical
Publication of KR101746203B1 publication Critical patent/KR101746203B1/ko

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22—Demodulator circuits; Receiver circuits
    • H04L27/233—Demodulator circuits; Receiver circuits using non-coherent demodulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Information Transfer Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
KR1020140151527A 2014-11-03 2014-11-03 멀티 칩 시스템에서 칩들 간의 클럭 신호의 위상차 보상방법 및 장치 KR101746203B1 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020140151527A KR101746203B1 (ko) 2014-11-03 2014-11-03 멀티 칩 시스템에서 칩들 간의 클럭 신호의 위상차 보상방법 및 장치
JP2014254699A JP6013440B2 (ja) 2014-11-03 2014-12-17 マルチチップシステムにおける各チップ間のクロック信号の位相差補償方法及び装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020140151527A KR101746203B1 (ko) 2014-11-03 2014-11-03 멀티 칩 시스템에서 칩들 간의 클럭 신호의 위상차 보상방법 및 장치

Publications (2)

Publication Number Publication Date
KR20160053348A KR20160053348A (ko) 2016-05-13
KR101746203B1 true KR101746203B1 (ko) 2017-06-21

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020140151527A KR101746203B1 (ko) 2014-11-03 2014-11-03 멀티 칩 시스템에서 칩들 간의 클럭 신호의 위상차 보상방법 및 장치

Country Status (2)

Country Link
JP (1) JP6013440B2 (ja)
KR (1) KR101746203B1 (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106774634A (zh) * 2016-12-08 2017-05-31 郑州云海信息技术有限公司 一种时钟偏斜校正方法、装置和系统
CN110618957B (zh) * 2019-08-30 2023-07-28 晶晨半导体(上海)股份有限公司 接口时序校准方法及装置
CN110995537B (zh) * 2019-12-02 2023-02-03 重庆矢崎仪表有限公司 多芯片闭环通信延迟计算方法、通信同步方法及通信系统

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006173689A (ja) 2004-12-13 2006-06-29 Nec Corp 非同期信号転送システム、非同期信号転送装置及びそれらに用いる非同期信号転送方法
JP2009219078A (ja) 2008-03-13 2009-09-24 Hitachi Ltd クロックデータリカバリ回路

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3566686B2 (ja) * 2001-10-16 2004-09-15 Ｎｅｃマイクロシステム株式会社 逓倍クロック生成回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006173689A (ja) 2004-12-13 2006-06-29 Nec Corp 非同期信号転送システム、非同期信号転送装置及びそれらに用いる非同期信号転送方法
JP2009219078A (ja) 2008-03-13 2009-09-24 Hitachi Ltd クロックデータリカバリ回路

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Publication number Publication date
JP2016091530A (ja) 2016-05-23
JP6013440B2 (ja) 2016-10-25
KR20160053348A (ko) 2016-05-13

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