KR101665569B1 - Overlay mark, overlay measurement method and semiconductor device manufacturing method using the overlay mark - Google Patents

Overlay mark, overlay measurement method and semiconductor device manufacturing method using the overlay mark Download PDF

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Publication number
KR101665569B1
KR101665569B1 KR1020160061643A KR20160061643A KR101665569B1 KR 101665569 B1 KR101665569 B1 KR 101665569B1 KR 1020160061643 A KR1020160061643 A KR 1020160061643A KR 20160061643 A KR20160061643 A KR 20160061643A KR 101665569 B1 KR101665569 B1 KR 101665569B1
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South Korea
Prior art keywords
bars
overlay
overlay mark
mark
sub
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KR1020160061643A
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Korean (ko)
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장현진
하호철
이길수
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(주)오로스 테크놀로지
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Priority to KR1020160061643A priority Critical patent/KR101665569B1/en
Application granted granted Critical
Publication of KR101665569B1 publication Critical patent/KR101665569B1/en
Priority to PCT/KR2016/011584 priority patent/WO2017200159A1/en
Priority to CN201680007966.5A priority patent/CN108351595B/en
Priority to TW105133791A priority patent/TWI600134B/en
Priority to JP2016209326A priority patent/JP6063602B1/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G03F1/42—Alignment or registration features, e.g. alignment marks on the mask substrates
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70681—Metrology strategies
    • G03F7/70683—Mark designs
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Length Measuring Devices By Optical Means (AREA)

Abstract

The present invention relates to an overlay mark and to an overlay measurement method and a semiconductor device manufacturing method using the same. The present invention provides an overlay mark, which determines relative stagger between two consecutive pattern layers or among two or more patterns formed separately on one layer, comprising: a first overlay structure including a pair of first bars, which face each other and extend in a first direction, and a pair of second bars, which face each other and extend in a second direction perpendicular to the first direction; and a second overlay structure including multiple pairs of third bars parallel to the first bars and multiple pairs of fourth bars parallel to the second bars, wherein gaps between the adjacent third bars are different from one another and gaps between the adjacent fourth bars are different from one another. The overlay mark according to the present invention can minimize the occurrence of errors during the analysis of an image by varying gaps between bars.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an overlay mark, an overlay measurement method using the overlay mark,

The present invention relates to an overlay mark, an overlay measurement method using the overlay mark, and a semiconductor device manufacturing method.

A plurality of pattern layers are sequentially formed on the semiconductor substrate. In addition, a circuit of one layer is formed by dividing into two patterns through double patterning or the like. The desired pattern elements or a plurality of patterns of one layer are precisely formed at predetermined positions, so that a desired semiconductor element can be manufactured.

Thus, overlay marks formed at the same time as the pattern layers are used to ensure that the pattern layers are correctly aligned.

The method of measuring the overlay using the overlay mark is as follows. First, one structure, which is a part of the overlay marks, is formed in the pattern layer formed in the previous step, for example, the etching step, at the same time as the pattern layer formation. And in subsequent processes, e.g., photolithography processes, form the remaining structures of the overlay marks on the photoresist. Then, an overlay structure (obtained by passing through the photoresist layer) of the pattern layer formed in the previous process and an image of the overlay structure of the photoresist layer are obtained through the overlay measuring device, and an offset value between the centers of these images is measured Measure the overlay value. If the overlay value is outside the acceptable range, remove the photoresist layer and rework.

Commonly known overlay macros include box-in-box (BIB) and Advanced Imaging Metrology (AIM). Further, as shown in Fig. 1, the BIB is improved to form a square box 1 in the upper layer, and a lower layer having a relatively weak signal is provided with a plurality of bars 2 parallel to the respective sides of the box There is also a mark. In the mark shown in Fig. 1, since the plurality of bars 2 are arranged at equal intervals, when the intensity of the signal is weak, Likewise, when analyzing an image, there is a problem that an error may occur in reading by shifting to the left by one cycle. If such an error occurs, the position of the center of the bar is misrecognized, and the overlay value may be calculated incorrectly.

Japanese Patent JP 5180419

It is an object of the present invention to provide a new overlay mark formed simultaneously with pattern layers to ensure that the pattern layers are correctly aligned in a semiconductor manufacturing process. It is also an object of the present invention to minimize the occurrence of errors in image analysis as the bars are arranged at regular intervals as described above.

The present invention is an overlay mark for determining the relative dislocation between two or more successive pattern layers or two or more patterns formed separately on one layer, the overlay mark comprising a pair of first bars facing each other and extending in a first direction, A first overlay structure including a pair of second bars extending in a second direction orthogonal to the first direction, a plurality of pairs of third bars aligned with the first bars, and a plurality of pairs And the second overlay structure includes a fourth bar of adjacent first bars, wherein the spacing between adjacent third bars is different and the spacing between adjacent fourth bars is different.

In addition, the third bars and the fourth bars provide overlay marks that are divided into a plurality of sub bars along the longitudinal direction, respectively.

In addition, the plurality of sub bars provide an overlay mark including at least two sub bars of different widths.

In addition, the sub bars each provide an overlay mark that is divided into a plurality of segment bars along the width direction.

In addition, adjacent sub bars provide overlay marks that are divided into different numbers of segment bars.

The third bars and the fourth bars provide an overlay mark having a longer length as it is disposed on the outside.

The present invention also relates to a method of manufacturing a semiconductor device, comprising the steps of: forming two patterns formed separately on two successive pattern layers or one pattern layer and simultaneously forming overlay marks; measuring an overlay value using the overlay marks; Using the measured overlay value for process control to form two consecutive pattern layers or two patterns formed separately in one pattern layer, wherein the overlay mark is the above-mentioned overlay mark. And a manufacturing method thereof.

The method of claim 1, further comprising the steps of: forming two patterns that are separately formed in two successive pattern layers or one pattern layer and obtaining images of overlay marks formed at the same time; and analyzing images of the overlay marks, And the marks are the above-mentioned overlay marks.

The overlay mark according to the present invention can be used as a mark to confirm that the pattern layers are correctly aligned in the semiconductor manufacturing process. It may also be used as a mark to confirm whether a plurality of patterns of one layer are correctly aligned.

The overlay mark according to the present invention is advantageous in minimizing errors in image analysis by varying the intervals between bars.

1 is a plan view of a conventional overlay mark.
Fig. 2 is a view for explaining the image analysis step of the overlay mark shown in Fig. 1. Fig.
3 is a plan view of an embodiment of an overlay mark according to the present invention.
4 is a diagram for explaining an increase in the number of signals by a segment bar.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments of the present invention may be modified into various other forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. Embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. Therefore, the shapes and the like of the elements in the drawings are exaggerated in order to emphasize a clearer description, and elements denoted by the same symbols in the drawings denote the same elements.

3 is a plan view of an embodiment of an overlay mark according to the present invention.

Referring to FIG. 3, one embodiment of an overlay mark 100 in accordance with the present invention includes a first overlay structure 10 and a second overlay structure 20. The overlay mark 100 may be provided in a scribe lane of the wafer to provide an overlay between two or more pattern layers on a wafer or between two or more patterns on a single layer.

The first overlay structure 10 and the second overlay structure 20 are formed in different pattern layers when utilized for overlay measurement between different pattern layers. And when the first overlay structure 10 and the second overlay structure 20 are utilized for overlay measurement between different patterns of the same layer, for example, two patterns formed in the double patterning process, As shown in FIG. At this time, the first overlay structure 10 and the second overlay structure 20 are formed on the same layer through different processes. For convenience, the following description will be made on the basis of overlay measurement between different pattern layers.

As shown in Fig. 3, in this embodiment, the first overlay structure 10 includes first bars 12a, 12b and second bars 14a, 14b. A pair of first bars (12a, 12b) facing each other are elongated in the first direction. The pair of second bars 14a and 14b facing each other are elongated in a second direction orthogonal to the first direction. The first direction and the second direction may be the Y-axis direction and the X-axis direction, respectively. The first overlay structure 10 generally has a generally square shape and is point symmetrical with respect to the center point.

The second overlay structure 20 includes first regions 22a and 22b disposed on the left and right sides of the first overlay structure 10 and second regions 24a and 24b disposed on the upper and lower sides, respectively. In the present embodiment, the first areas 22a and 22b are formed by three rows of third bars 221a, 222a, and 223a disposed on the left side of the first overlay structure 10 and three rows of third 242b, and 243b, which are six upper and lower four bars, 241a, 242a, 243a, 241b, 242b, and 243b, . The third bars 221a, 222a, 223a, 221b, 222b and 223b are used for X-axis overlay measurement together with the first bars 12a and 12b and the fourth bars 241a, 242a, 243a, 241b, 243b are used together with the second bars 14a, 14b for Y-axis direction overlay measurement.

The third bars 221a, 222a, 223a, 221b, 222b, and 223b and the fourth bars 241a, 242a, 243a, 241b, 242b, and 243b become longer as they are disposed outward. In the present embodiment, since the bar is disposed at an outer position, the signal that can be secured by the outer bars 221a, 241a, 221b, and 241b increases. It is judged by summing the signals secured along the longitudinal direction of the bar. Therefore, if the length is increased, the amount of signals that can be obtained increases. The bars 221a, 241a, 221b, and 241b disposed outside are highly likely to be damaged. However, in this embodiment, the bar bars 221a, 241a, 221b, and 241b disposed outside are long, A signal can be secured.

As can be seen from Fig. 3, in the present embodiment, the intervals between adjacent bars are different from each other. Third bars 222a and 222b in which the intervals between the third bars 223a and 223b disposed in the innermost position and the third bars 222a and 222b disposed in the middle are disposed in the middle, Which is narrower than the interval between the bars 221a and 221b. Similarly, the intervals between the adjacent fourth bars are also different from each other. Since the spacing between the bars is different, an image of a portion of the second overlay structure 20 can be obtained to determine where the bars captured in the image are located when measuring the overlay. For example, if the outermost third bars 221a and 221b are damaged so that only images of the middle and inner third bars 222a and 223a or 222b and 223b are obtained, In the conventional overlay mark disposed, it is impossible to discriminate whether this image is the image of the outermost two bars 221a, 222a or 221b, 222b or the image of the inner two bars 222a, 223a or 222b, 223b, Errors occurred in some cases. However, in the present invention, since it is immediately possible to confirm that the images are the third bars 223a and 223b arranged in the innermost part and the third bars 222a and 222b arranged in the middle through the interval between the two bars, Does not occur.

The third bars and the fourth bars each include a plurality of sub bars. And the sub bars each include a plurality of segment bars. Since all the bars are divided into sub bars and segments in the same manner, the third bar 221a located at the leftmost position in the figure will be referred to as the following description.

The third bar 221a includes three sub bars 311a, 312a, and 313a. That is, one bar is divided into three sub bars 311a, 312a, and 313a along the length direction. The thickness of the sub-bar 312a positioned at the center of the sub-bars is thinner than the thickness of the other two sub-bars 311a and 313a. Also, in this embodiment, one subbar includes two or three segment bars. That is, the centered sub-bar 312a includes two segment bars 342a, and the remaining two sub-bars 311a and 313a include three segment bars 341a and 343a, respectively. As shown in FIG. 4, when two subbars are divided into two segment bars, four signals can be obtained. In this case, in terms of reproducibility and accuracy, Do. Furthermore, by varying the number of segment bars for each sub-bar, it is also possible to evaluate the reliability of the overlay mark by measuring the overlay for each sub-bar and comparing them with each other.

Since the first overlay structure 10 and the second overlay structure 20 are all deformed for 90-degree rotation and the rotation centers of the first overlay structure 10 and the second overlay structure 20 coincide with each other, The exemplary overlay mark 100 is an entirety for an 90 degree rotation.

Alternatively, the second overlay structure 20 may be formed on the pattern layer formed in the previous process, and the first overlay structure 10 may be formed on the pattern layer formed in the subsequent process. Since the pattern layer formed in the previous process is masked by the pattern layer formed in the subsequent process, accurate image acquisition is difficult compared to the pattern layer formed in the subsequent process. This is because it is advantageous to form the second overlay structure 20 which is easier to measure more accurately in the previous process.

Hereinafter, an overlay measurement method using the overlay mark 100 shown in FIG. 1 will be described. The overlay metrology method includes obtaining an image of the overlay mark 100 and analyzing the image of the overlay mark 100. The overlay mark 100 is formed at the same time as forming two consecutive pattern layers or two patterns formed separately on one pattern layer.

Obtaining an image of the overlay mark 100 may include obtaining an image of the first overlay structure 10, acquiring an image of the second overlay structure 20, Step < / RTI >

If the first overlay structure 10 and the second overlay structure 20 are formed on different layers, an image can be obtained using different light sources. Since the second overlay structure 20 formed in the previous process is covered by the pattern layer formed in the subsequent process, it is preferable to obtain the image using the light of the wavelength capable of passing through the pattern layer formed in the subsequent process.

Analyzing the image of the overlay mark 100 may be a step of measuring the offset of the center of the first overlay structure 10 and the center of the second overlay structure 20 in the obtained combined image. It may also be a step of measuring the distance between the center of the second overlay structure 20 and the lines corresponding to the inner edge of the first overlay structure 10.

Hereinafter, a method of manufacturing a semiconductor device using the overlay mark 100 shown in FIG. 1 will be described. The method of manufacturing a semiconductor device using the overlay mark 100 starts with the step of forming the overlay mark 100. The overlay marks 100 are formed while forming two patterns formed separately on two consecutive pattern layers or one pattern layer.

Next, the overlay mark 100 is used to measure the overlay value. The step of measuring the overlay value is the same as the above-described overlay measurement method.

Finally, the measured overlay value is used for process control to form two successive pattern layers or two patterns formed separately on one pattern layer. That is, the derived overlay is utilized for process control so that a continuous pattern layer or two patterns are formed at predetermined positions.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It will be understood by those skilled in the art that various changes, modifications, or substitutions will be possible, and that these embodiments are within the scope of the present invention.

100: overlay mark
10: first overlay structure
20: second overlay structure
22: first region
24: second region
221, 222, 223: the third bar
241, 242, 243: fourth bar
311, 312, 313, 321, 322, 323, 331, 332, 333:
411, 412, 413, 421, 422, 423, 431, 432, 433:
341, 342, 343, 351, 352, 353, 361, 362, 363:
441, 442, 443, 451, 452, 453, 461, 462, 463:

Claims (8)

An overlay mark for determining a relative stagger between two or more successive pattern layers or two or more patterns formed separately in one layer,
A first overlay structure including a pair of first bars facing each other and extending in a first direction and a pair of second bars facing each other and extending in a second direction orthogonal to the first direction,
A plurality of third bars arranged in parallel with the first bars and a plurality of fourth bars arranged in parallel with the second bars, wherein the intervals between the adjacent third bars are different from each other, and the interval between the adjacent fourth bars And a second overlay structure,
The third bars and the fourth bars are each divided into a plurality of sub bars along a longitudinal direction, the plurality of sub bars are formed in the same layer,
The plurality of sub bars including at least two sub bars having different widths,
The sub bars are each divided into a plurality of segment bars along the width direction,
Wherein the adjacent sub bars are divided into different number of segment bars. delete delete delete delete The method according to claim 1,
And the third bars and the fourth bars are longer in length as they are disposed on the outside. A method of manufacturing a semiconductor device,
Forming two overlay marks simultaneously with forming two patterns formed separately on two successive pattern layers or one pattern layer;
Measuring an overlay value using the overlay mark;
Using the measured overlay value for process control to form two successive pattern layers or two patterns formed separately in one pattern layer,
Wherein the overlay mark is an overlay mark according to claim 1 or claim 6. A method for measuring an overlay between two successive pattern layers or two patterns formed separately on one pattern layer,
Forming two patterns formed separately on two successive pattern layers or one pattern layer and acquiring an image of overlay marks formed at the same time,
And analyzing the image of the overlay mark,
Wherein the overlay mark is the overlay mark according to claim 1 or 6.
KR1020160061643A 2016-05-19 2016-05-19 Overlay mark, overlay measurement method and semiconductor device manufacturing method using the overlay mark KR101665569B1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020160061643A KR101665569B1 (en) 2016-05-19 2016-05-19 Overlay mark, overlay measurement method and semiconductor device manufacturing method using the overlay mark
PCT/KR2016/011584 WO2017200159A1 (en) 2016-05-19 2016-10-14 Overlay mark, and overlay measurement method and semiconductor device manufacturing method using same
CN201680007966.5A CN108351595B (en) 2016-05-19 2016-10-14 Alignment mark, alignment measurement method and manufacturing method for semiconductor device using it
TW105133791A TWI600134B (en) 2016-05-19 2016-10-20 Overlay mark, overlay measurement method and semiconductor device manufacturing method using the overlay mark
JP2016209326A JP6063602B1 (en) 2016-05-19 2016-10-26 Overlay mark, overlay measurement method using the same, and semiconductor device manufacturing method

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CN (1) CN108351595B (en)
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WO (1) WO2017200159A1 (en)

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KR102440758B1 (en) * 2021-08-17 2022-09-06 (주)오로스 테크놀로지 Overlay mark, overlay measurement method and semiconductor device manufacturing method using the overlay mark
KR102460132B1 (en) * 2022-07-19 2022-10-31 (주)오로스 테크놀로지 Overlay mark, overlay measurement method and semiconductor device manufacturing method using the overlay mark

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