KR101564312B1 - Overlay mark, overlay measurement method and semiconductor device manufacturing method using the overlay mark - Google Patents

Overlay mark, overlay measurement method and semiconductor device manufacturing method using the overlay mark Download PDF

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Publication number
KR101564312B1
KR101564312B1 KR1020150130524A KR20150130524A KR101564312B1 KR 101564312 B1 KR101564312 B1 KR 101564312B1 KR 1020150130524 A KR1020150130524 A KR 1020150130524A KR 20150130524 A KR20150130524 A KR 20150130524A KR 101564312 B1 KR101564312 B1 KR 101564312B1
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KR
South Korea
Prior art keywords
overlay
patterns
mark
bars
pattern layer
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KR1020150130524A
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Korean (ko)
Inventor
장명식
이준우
장현진
김세웅
이길수
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(주)오로스 테크놀로지
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Publication of KR101564312B1 publication Critical patent/KR101564312B1/en
Priority to PCT/KR2015/011610 priority Critical patent/WO2017007072A1/en
Priority to JP2015218547A priority patent/JP6014845B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

Abstract

The present invention relates to an overlay mark and a method for measuring overlay and a method for manufacturing a semiconductor device using the same. The present invention provides an overlay mark, which determines the relative crisscross between two patterns formed separately on two continuous pattern layers or a single pattern layer, and comprises: a first overlay structure in the shape of a square; and a second overlay structure which comprises four overlay patterns placed on the top, bottom, left, and right of the first overlay structure, each of which comprises multiple bars that are parallel to each other. According to the present invention, the overlay mark can be used as a mark for checking if pattern layers are accurately aligned in the manufacturing process of a semiconductor. In addition, the overlay mark can be used as a mark for checking if multiple patterns in a single layer are accurately aligned.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an overlay mark, an overlay measurement method using the overlay mark,

The present invention relates to an overlay mark, an overlay measurement method using the overlay mark, and a semiconductor device manufacturing method.

A plurality of pattern layers are sequentially formed on the semiconductor substrate. In addition, a circuit of one layer is formed by dividing into two patterns through double patterning or the like. The desired semiconductor device can be manufactured only when these pattern layers or a plurality of patterns of one layer are precisely formed at predetermined positions.

Thus, overlay marks formed at the same time as the pattern layers are used to ensure that the pattern layers are correctly aligned.

The method of measuring the overlay using the overlay mark is as follows. First, one structure, which is a part of the overlay marks, is formed in the pattern layer formed in the previous step, for example, the etching step, at the same time as the pattern layer formation. And in subsequent processes, e.g., photolithography processes, form the remaining structures of the overlay marks on the photoresist. Then, an overlay structure (obtained by passing through the photoresist layer) of the pattern layer formed in the previous process and an image of the overlay structure of the photoresist layer are obtained through the overlay measuring device, and an offset value between the centers of these images is measured Measure the overlay value. If the overlay value is outside the acceptable range, remove the photoresist layer and rework.

Japanese Patent JP 5180419

It is an object of the present invention to provide a new overlay mark formed simultaneously with pattern layers to ensure that the pattern layers are correctly aligned in a semiconductor manufacturing process.

In order to achieve the above object, the present invention is an overlay mark for determining the relative dislocation between two patterns formed on two consecutive pattern layers or one pattern layer, which is a square shape and has a square corner portion and a center portion Wherein the mesa structure has a first overlay structure connected by a plurality of trenches arranged in parallel and four overlay patterns respectively disposed on upper and lower and left and right sides of the first overlay structure, Each having a plurality of bars parallel to each other, wherein the plurality of bars are elongated as they are away from the first overlay structure, have a narrower width, and have a trench structure and a mesa structure alternately formed along the longitudinal direction And a second overlay structure, wherein the first overlay structure and the second overlay structure Plaiting provides an overlay marks characterized in that each formation is formed on another layer or a pattern with a different pattern that is formed separately on one of the pattern layer.

In the overlay mark, the areas of the bars are preferably equal to each other.

It is further preferred that the trench structure comprises a plurality of trenches arranged in parallel, wherein the mesa structure further comprises a plurality of mesas arranged in parallel.

Further, for critical dimension measurement, the first overlay structure may further include a circular structure formed inside the first overlay structure.

Also, the second overlay structure may be an invariant to 90 degree rotation.

Further, the interval between the plurality of bars of the overlay patterns may be constant.

In addition, among the four overlay patterns, the bars of the overlay patterns disposed on the top and bottom of the first overlay structure and the bars of the overlay patterns disposed on the right and left of the first overlay structure may be orthogonal to each other.

delete

It is also preferable that the rotation centers of the first overlay structure and the second overlay structure coincide with each other.

The second overlay structure may be formed on a pattern layer formed by a previous process, and the first overlay structure may be formed on a pattern layer formed by a subsequent process.

The present invention also relates to a method of manufacturing a semiconductor device, comprising the steps of: forming two patterns formed separately on two successive pattern layers or one pattern layer and simultaneously forming overlay marks; measuring an overlay value using the overlay marks; Using the measured overlay value for process control to form two consecutive pattern layers or two patterns formed separately in one pattern layer, wherein the overlay mark is the above-mentioned overlay mark. And a manufacturing method thereof.

The method of claim 1, further comprising the steps of: forming two patterns that are separately formed in two successive pattern layers or one pattern layer and obtaining images of overlay marks formed at the same time; and analyzing images of the overlay marks, And the marks are the above-mentioned overlay marks.

The overlay mark according to the present invention can be used as a mark to confirm that the pattern layers are correctly aligned in the semiconductor manufacturing process. It may also be used as a mark to confirm whether a plurality of patterns of one layer are correctly aligned.

1 is a plan view showing an embodiment of an overlay mark according to the present invention.
2 is an enlarged cross-sectional view of a part of the overlay pattern shown in FIG.
3 is a plan view showing another embodiment of the overlay mark according to the present invention.
4 is a plan view showing another embodiment of the overlay mark according to the present invention.
Figure 5 is a cross-sectional view of one of the second overlay structures shown in Figure 4;
6 is a diagram for explaining the inaccuracy of the measurement due to the asymmetry of a general overlay mark.
7 is a plan view showing a part of another embodiment of an overlay mark according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments of the present invention may be modified into various other forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. Embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. Therefore, the shapes and the like of the elements in the drawings are exaggerated in order to emphasize a clearer description, and elements denoted by the same symbols in the drawings denote the same elements.

1 is a plan view showing an embodiment of an overlay mark according to the present invention.

Referring to FIG. 1, one embodiment of an overlay mark 100 in accordance with the present invention includes a first overlay structure 110 and a second overlay structure 120. The overlay mark 100 may be provided in a scribe lane of the wafer to provide an overlay between two or more pattern layers on a wafer or between two or more patterns on a single layer.

The first overlay structure 110 and the second overlay structure 120 are formed in different pattern layers when utilized for overlay measurement between different pattern layers. And when the first overlay structure 110 and the second overlay structure 120 are utilized for overlay measurement between different patterns of the same layer, for example, two patterns formed in a double patterning process, As shown in FIG. At this time, the first overlay structure 110 and the second overlay structure 120 are formed on the same layer through different processes. For convenience, the following description will be made on the basis of overlay measurement between different pattern layers.

As shown in Figure 1, in this embodiment, the first overlay structure 110 is square in shape. Two opposing sides of the first overlay structure 110 are parallel to the first direction and the other two sides are parallel to the second direction orthogonal to the first direction. The first direction and the second direction may be the X axis direction and the Y axis direction, respectively.

The second overlay structure 120 has four overlay patterns 121, 122, 123, and 124 disposed on the top, bottom, left, and right sides of the first overlay structure 110, respectively. Each of the four overlay patterns 121, 122, 123, 124 has a plurality of bars 125, 126, 127, 128 arranged side by side. The plurality of bars 125, 126, 127, 128 of the respective overlay patterns 121, 122, 123, 124 are arranged at regular intervals. The lengths and widths of the plurality of bars 125, 126, 127, 128 of the overlay patterns 121, 122, 123, 124 are also equal to each other.

The bars 127 and 128 of the overlay patterns 123 and 124 disposed above and below the first overlay structure 110 among the four overlay patterns 121 and 122 and the first overlay structure 110, The bars 125 and 126 of the overlay patterns 121 and 122 arranged on the right and left sides of the overlay patterns 121 and 122 are orthogonal to each other. The bars 127 and 128 of the overlay patterns 123 and 124 arranged above and below the first overlay structure 110 are elongated in the X axis direction and are arranged along the Y axis direction, The bars 125 and 126 of the overlay patterns 121 and 122 arranged on the left and right sides of the substrate 110 are elongated in the Y axis direction and are arranged along the X axis direction. The left and right overlay patterns 121 and 122 can be used for measuring the overlay in the X-axis direction, and the upper and lower overlay patterns 123 and 124 can be used for measuring the overlay in the Y-axis direction.

Since the first overlay structure 110 and the second overlay structure 120 are both unchanged for 90 degree rotation and the first overlay structure 110 and the second overlay structure 120 have the same rotational center C , The overlay mark 100 of the present embodiment is an entirety for 90 degree rotation.

Alternatively, the second overlay structure 120 may be formed on the pattern layer formed in the previous process, and the first overlay structure 110 may be formed on the pattern layer formed in the subsequent process. Since the pattern layer formed in the previous process is masked by the pattern layer formed in the subsequent process, accurate image acquisition is difficult compared to the pattern layer formed in the subsequent process. This is because it is advantageous to form the second overlay structure 120, which is easier to measure more accurately, in the previous process.

2 is an enlarged cross-sectional view of a part of the overlay pattern shown in FIG. As shown in FIG. 2, the plurality of bars 125, 126, 127, 128 of the overlay patterns 121, 122, 123, 124 preferably each include a plurality of fine bars 130. Having the overlay mark 100 have an interval and width similar to the spacing and width defined in the design rules applied to the die area of the wafer helps to reduce the error between the overlay of the actual die area and the overlay mark measured through the overlay mark Because. The plurality of fine bars 130 may be formed at equal intervals.

3 is a plan view showing another embodiment of the overlay mark according to the present invention.

The embodiment shown in FIG. 3 differs from the embodiment shown in FIG. 1 in the second overlay structure 220, and therefore only this embodiment will be described. The embodiment shown in FIG. 3 differs from the embodiment shown in FIG. 1 in that the second overlay structure 220 is variable for 90 degree rotation. It is also a variable body for 180-degree rotation. In this embodiment, the overlay patterns 221, 222, 223 and 224 of the second overlay structure 220 are formed by the bars 225 and 226 and 227 of the overlay patterns 221 and 222, 223 and 224, And 228 are orthogonal to each other.

Hereinafter, an overlay measurement method using the overlay mark 100 shown in FIG. 1 will be described. The overlay metrology method includes obtaining an image of the overlay mark 100 and analyzing the image of the overlay mark 100. The overlay mark 100 is formed at the same time as forming two consecutive pattern layers or two patterns formed separately on one pattern layer.

Obtaining an image of the overlay mark 100 may include obtaining an image of the first overlay structure 110, acquiring an image of the second overlay structure 120, acquiring an image of the second overlay structure 120 Step < / RTI >

If the first overlay structure 110 and the second overlay structure 120 are formed on different layers, an image can be obtained using different light sources. Since the second overlay structure 120 formed in the previous process is covered by the pattern layer formed in the subsequent process, it is preferable to obtain the image using the light of the wavelength capable of passing through the pattern layer formed in the subsequent process.

Analyzing the image of the overlay mark 100 may be a step of measuring the offset of the center of the first overlay structure 110 and the center of the second overlay structure 120 in the obtained combined image. It may also be a step of measuring the distance between the center of the second overlay structure 120 and the lines corresponding to the inner edge of the first overlay structure 110.

Hereinafter, a method of manufacturing a semiconductor device using the overlay mark 100 shown in FIG. 1 will be described. The method of manufacturing a semiconductor device using the overlay mark 100 starts with the step of forming the overlay mark 100. The overlay marks 100 are formed while forming two patterns formed separately on two consecutive pattern layers or one pattern layer.

Next, the overlay mark 100 is used to measure the overlay value. The step of measuring the overlay value is the same as the above-described overlay measurement method.

Finally, the measured overlay value is used for process control to form two successive pattern layers or two patterns formed separately on one pattern layer. That is, the derived overlay is utilized for process control so that a continuous pattern layer or two patterns are formed at predetermined positions.

FIG. 4 is a plan view showing another embodiment of an overlay mark according to the present invention, and FIG. 5 is a view showing a cross section of one bar of the second overlay structure shown in FIG.

4, the present embodiment includes a first overlay structure 310, a second overlay structure 320, and a prototype structure 330. As shown in FIG. The circular structure 330 is formed inside the first overlay structure 310. The circular structure 330 allows for approximate critical dimension measurement based on the optical image. This makes it possible to secure process stability in the semiconductor manufacturing process. In addition, the circular structure 330 may provide a more specific environment for pattern recognition through the first overlay structure 310 to more stably target centering, which is a process for measuring the overlay You can also play the role of making it happen.

As shown in Figure 4, in this embodiment, the first overlay structure 310 is square in shape. The second overlay structure 320 includes four overlay patterns 321, 322, 323, and 324 disposed on upper, lower, left, and right sides of the first overlay structure 310, respectively. Each of the four overlay patterns 321, 322, 323, and 324 has a plurality of bars 325, 326, 327, and 328 aligned with each other. The plurality of bars 325, 326, 327, 328 of the respective overlay patterns 321, 322, 323, 324 are arranged at regular intervals.

The feature of this embodiment that is different from the embodiment shown in Fig. 1 is that the lengths and widths of the plurality of bars 325a, 325b, 325c, 325d and 325e constituting one overlay pattern (for example, 321) are different from each other. The plurality of bars 325a, 325b, 325c, 325d, and 325e are formed such that the lengths of the bars 325a, 325b, 325c, 325d, and 325e are the same as the distance from the first overlay structure 310 It gets longer and narrower. That is, the bars 325a disposed at the innermost side have the shortest length and the widest width, and the outermost bar 325e has the longest length and the narrowest width.

This embodiment has an advantage in that precision can be easily secured even when a defocus occurs, as compared with the case where bars having a single width are provided. In addition, since the amount of intensity information of light can be secured in a region close to the optical center as compared with the case of having a single width of bars, it is possible to obtain accuracy of precision in combination with the following mesa and trench type There is an advantage that it is easy.

Another aspect of this embodiment that is different from the embodiment shown in Figure 1 is that the sides of the first overlay structure 310 and the bars 325, 326, 327, 328 of the second overlay structure 320 are spaced apart from the mesa mesa, M) structure and trench (T) structure are alternately formed. In Fig. 4, the darkly marked portion is the concave portion. In the embodiment shown in FIG. 4, a region is allocated to each of the mesa-trench-mesa-trench-mesa by 1/5, but regions may be divided differently if necessary.

The application of such a structure has an advantage that an error caused by asymmetry in the process of manufacturing an overlay mark can be reduced.

As shown in FIG. 6, when the overlay structure is manufactured through the semiconductor process, the angles? And? Of the inclined surfaces of the structure may be different from each other. This asymmetry can occur in semiconductor processes such as chemical mechanical polishing (CMP), chemical vapor deposition (CVD), and reactive ion etching (RIE). When all the overlay structures of the same layer are fabricated with a trench structure or a mesa structure, there is a problem in that the overlay measurement value can be measured differently depending on the focus height and the wavelength band of light used for the measurement due to the asymmetry in the manufacture of the overlay mark have.

However, as shown in FIGS. 4 and 5, when the overlay structure in which the trench structure and the mesa structure are alternately formed in the same layer is used, the error in the trench structure and the error in the mesa structure partially cancel each other, It can be minimized. That is, when the structure is formed by the semiconductor process, the asymmetry may be different depending on whether the structure is a mesa structure or a trench structure, so that some errors may be canceled. It is also possible to increase the accuracy of the overlay measurement by measuring the magnitude of the error. For example, the inaccuracy of the overlay structure is measured by calculating the difference between the center point of a pair of trench structures arranged at the same distance from the center of the overlay mark and the center point of a pair of mesa structures arranged at the same distance from the center , Which can increase the accuracy of the overlay measurement. It is also possible to increase the accuracy of the overlay measurement by measuring the error in the trench structure and the error in the mesa structure and using the measurement value with a small error.

7 is a plan view of another embodiment of an overlay mark according to the present invention. In this embodiment, two or more trenches and / or mesas are arranged alternately along the longitudinal direction, unlike the embodiment shown in FIG. Only the trench structure may be formed of two or more trenches arranged side by side or only the mesa structure may be formed of two or more mesas arranged side by side and both of the trench structure and the mesa structure may be formed of two or more side by side. The structure of this embodiment has an advantage that the strength of a signal can be improved.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It will be understood by those skilled in the art that various changes, modifications, or substitutions will be possible, and that these embodiments are within the scope of the present invention.

100, 200, 300, 400: overlay mark
110, 310, 410: a first overlay structure
120, 220, 320, 420: a second overlay structure
121, 122, 123, 124: overlay pattern
125, 126, 127, 128: bar
130: Fine bar
221, 222, 223, 224: Overlay pattern
225, 226, 227, 228: bar
321, 322, 323, 324: Overlay pattern

Claims (22)

An overlay mark (400) for determining a relative stagger between two successive pattern layers or two patterns formed separately on one pattern layer,
And a mesa structure M is formed at the corner portion of the square and the center portion of each side. The mesa structure M includes a first overlay structure 410 connected by a plurality of trenches arranged in parallel,
And four overlay patterns 421, 422, 423, and 424 disposed on upper, lower, left, and right sides of the first overlay structure 410, respectively. The four overlay patterns 421, 422, 423, And the plurality of bars 425, 426, 427, and 428 are formed such that the length of the bars 425, 426, 427, and 428 increases as the distance from the first overlay structure 410 increases, And a second overlay structure 420 having a trench structure T alternately formed along the length direction and a mesa structure M,
Wherein the first overlay structure (410) and the second overlay structure (420) are formed on different pattern layers or are formed with different patterns formed separately on one pattern layer. delete The method according to claim 1,
An overlay mark characterized in that the areas of the bars (425, 426, 427, 428) are equal to each other. delete delete delete delete The method according to claim 1,
Wherein the trench structure (T) of the plurality of bars (425, 426, 427, 428) comprises a plurality of trenches arranged in parallel. The method according to claim 1,
Wherein the mesa structure (M) of the plurality of bars (425, 426, 427, 428) comprises a plurality of mesas arranged in parallel. The method according to claim 1,
An overlay mark, further comprising a circular structure (430) formed within the first overlay structure (410) for critical dimension measurement. The method according to claim 1,
Wherein the second overlay structure (420) is unchanged for 90 degree rotation. delete delete The method according to claim 1,
Wherein an interval between the plurality of bars (425, 426, 427, 428) of the overlay patterns (421, 422, 423, 424) is constant. delete delete The method according to claim 1,
The bars 427 and 428 of the overlay patterns 423 and 424 disposed above and below the first overlay structure 410 among the four overlay patterns 421, 422, 423 and 424, (425, 426) of the overlay patterns (421, 422) disposed on the right and left sides of the overlay pattern (410) are orthogonal to each other. delete The method according to claim 1,
Characterized in that the rotational centers of the first overlay structure (410) and the second overlay structure (420) coincide. The method according to claim 1,
Wherein the second overlay structure (420) is formed in a pattern layer formed by a previous process, and the first overlay structure (410) is formed in a pattern layer formed by a subsequent process. A method of manufacturing a semiconductor device,
Forming two overlay marks (400) while forming two patterns formed separately on two successive pattern layers or one pattern layer,
Measuring an overlay value using the overlay mark (400)
Using the measured overlay value for process control to form two successive pattern layers or two patterns formed separately in one pattern layer,
Characterized in that the overlay mark (400) is the overlay mark (400) according to any one of claims 1, 3, 8 to 11, 14, 17, 19 and 20 Gt; A method for measuring an overlay between two successive pattern layers or two patterns formed separately on one pattern layer,
Obtaining an image of the overlay mark 400 formed while forming two patterns formed separately on two successive pattern layers or one pattern layer,
Analyzing the image of the overlay mark (400)
Characterized in that the overlay mark (400) is an overlay mark (400) according to any one of claims 1, 3, 8 to 11, 14, 17, 19 and 20 .
KR1020150130524A 2015-07-07 2015-09-15 Overlay mark, overlay measurement method and semiconductor device manufacturing method using the overlay mark KR101564312B1 (en)

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PCT/KR2015/011610 WO2017007072A1 (en) 2015-07-07 2015-11-02 Overlay mark, overlay measurement method using same, and method for manufacturing semiconductor device
JP2015218547A JP6014845B1 (en) 2015-07-07 2015-11-06 Overlay mark, overlay measurement method using the same, and semiconductor device manufacturing method

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CN108351595A (en) * 2016-05-19 2018-07-31 奥路丝科技有限公司 Alignment mark, alignment measurement method and manufacturing method for semiconductor device using it
KR101906098B1 (en) * 2018-01-12 2018-10-10 (주)오로스 테크놀로지 Overlay mark, overlay measurement method and semiconductor device manufacturing method using the overlay mark
KR20200031744A (en) 2018-09-14 2020-03-25 (주)오로스 테크놀로지 Apparatus for measuring overlay
KR20210031015A (en) 2019-09-10 2021-03-19 (주)오로스 테크놀로지 Apparatus for measuring overlay
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KR20220003907A (en) 2020-07-02 2022-01-11 (주)오로스 테크놀로지 Apparatus for measuring overlay
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