JP2004031542A

JP2004031542A - Method for manufacturing semiconductor device

Info

Publication number: JP2004031542A
Application number: JP2002184033A
Authority: JP
Inventors: Tetsuya Nakamura; 中村　哲也; Hisashi Watanabe; 渡辺　尚志
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 2002-06-25
Filing date: 2002-06-25
Publication date: 2004-01-29

Abstract

<P>PROBLEM TO BE SOLVED: To accurately measure the amount of positional deviation between a first overlapping measurement mark and a second one by using a conventional optical measuring apparatus. <P>SOLUTION: The first overlapping measurement mark comprises a first pair of line pattern groups 114a, 114b consisting of a plurality of parallel linear patterns and a second pair of line pattern groups 115a, 115b consisting of a plurality of parallel linear patterns. The second overlapping measurement mark comprises a third pair of line pattern groups 124a, 124b consisting of a plurality of parallel linear patterns and a fourth pair of line pattern groups 125a, 125b consisting of a plurality of parallel linear patterns. The amount of positional deviation is measured based on a pair of first moire patterns formed by the first pair of line pattern groups 114a, 114b and the third pair of line pattern groups 124a, 124b, and a second pair of moire patterns formed by the second pair of line pattern groups 115a, 115b and a fourth pair of line pattern groups 125a, 125b. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置の製造方法に関し、特に、半導体装置の製造プロセスにおいて、下層パターンに形成されている第１の重ね合わせ測定マークと、該下層パターンの上に堆積された被処理膜の上に形成されたレジストパターンに形成されている第２の重ね合わせ測定マークとの位置ずれ量を測定する方法に関する。
【０００２】
【従来の技術】
半導体集積回路装置の微細化及び高集積化に伴って、パターンサイズは一層の微細化が要求されており、最新の半導体装置の製造プロセスにおいては最小線幅が１３０ｎｍレベルの半導体チップが量産化されつつある。
【０００３】
一方、デバイス（半導体チップ）の小型化を実現するためには、パターンの微細化と共に、上層のパターンを下層のパターンに精度良く位置合わせすることが重要である。そして、上層のパターンと下層のパターンとの間の重ね合わせ誤差（以下、単にパターン間の重ね合わせ誤差という）を低減することにより、パターン間の重ね合わせ誤差のために必要なデザイン上のマージンを低減することができるので、デバイスの小型化を図ることができる。
【０００４】
ところで、パターン間の重ね合わせ誤差の測定は、下層パターンに形成されている第１の重ね合わせ測定マーク（第１のアライメント測定マーク）と、上層パターンを形成するためのレジストパターンに形成されている第２の重ね合わせ測定マーク（第２のアライメント測定マーク）との間の位置ずれを重ね合わせ精度測定装置（アライメント精度測定装置）を用いて測定することにより行なわれる。
【０００５】
以下、第１の従来例として、重ね合わせ精度測定装置を用いて第１の重ね合わせ測定マークと第２の重ね合わせ測定マークとの間の位置ずれを測定する方法について、図７（ａ）　及び（ｂ）　を参照しながら説明する。
【０００６】
図７（ａ）　及び（ｂ）　において、１１は下層パターンに形成されている第１の重ね合わせ測定マークであって、パターンを形成しようとする上層パターンよりも前の工程において、リソグラフィ及びエッチング等を用いて方形枠状に形成されている。一方、１２は上層パターンを形成するためのレジストパターンに形成されている方形状の第２の重ね合わせ測定マークであって、第１の重ね合わせ測定マーク１１の内部に形成される。第１の重ね合わせ測定マーク１１の中心位置と第２の重ね合わせ測定マーク１２の中心位置とは一致するように設定されていると共に、第１の重ね合わせ測定マーク１１の内径及び第２の重ね合わせ測定マーク１２の外径は１０〜２０μｍ程度の設定されている。
【０００７】
第１の重ね合わせ測定マーク１１と第２の重ね合わせ測定マーク１２との位置ずれ量は、光学式の重ねあわせ測定装置により計測される。この場合、第１の重ね合わせ測定マーク１１の外径からその中心位置を求めると共に、第２の重ね合わせ測定マーク１２の外径からその中心位置を求め、２つの中心位置から中心位置間距離δを計算することにより、第１の重ね合わせ測定マーク１１と第２の重ね合わせ測定マーク１２との位置ずれ量が測定される。
【０００８】
以下、第２の従来例として、例えば特開平０３−２６８４１５号公報に示されるように、モアレ干渉を用いる重ね合わせ測定方法について説明する。すなわち、それぞれが複数の円環よりなる第１の重ね合わせ測定マーク及び第２の重ね合わせ測定マークを用いて、第１の重ね合わせ測定マークと第２の重ね合わせ測定マークとの重なりによりモアレパターンを生じさせ、該モアレパターンを観察することにより重ね合わせずれを検出する方法である。
【０００９】
また、第３の従来例として、特開平０３−１３４５０４号公報に示されるようなモアレ干渉を用いる重ね合わせ測定マークも知られている。
【００１０】
【発明が解決しようとする課題】
以下、第１の従来例の課題について説明する。
【００１１】
従来のデバイスでは、重ね合わせ測定装置の測定精度は、求められる重ね合わせ測定精度に対して十分に余裕があったが、現在量産化されている１３０ｎｍのルールのデバイスでは、必要な重ね合わせ精度は約８０ｎｍ程度であり、また、今後一層の微細化が進むにつれて、重ね合わせ精度に対する要求はさらに厳しくなってくる。ところが、従来の光学式の検査方法を用いる限り、重ね合わせ測定装置はデバイスから要求される重ね合わせ精度を測定することができる性能を有していない。
【００１２】
また、従来の重ね合わせ測定マークの形状は、１辺が１０〜２０μｍの方形状であって、実際に用いられる回路パターン（実パターン）のサイズと比較すると大きな隔たりがある。このように、重ね合わせ測定マークのサイズと実パターンのサイズとの差が大きいと、露光装置の収差の影響により、下地層における重ね合わせ測定マークが結像する位置と実パターンが結像する位置との間に差異が生じることがある。このような差異が発生すると、重ね合わせ測定マーク同士の位置ずれを正確に測定したとしても、所望の結果を得られないためにパターン同士が短絡するという不具合が生じる。
【００１３】
第２の従来例によると、第１の重ね合わせ測定マークと第２の重ね合わせ測定マークとの間に発生する位置ずれを精度良く検出することはできるが、第１の重ね合わせ測定マークと第２の重ね合わせ測定マークとの間の位置ずれ量及び位置ずれの方向を検出することは困難である。また、第２の従来例においては、モアレパターンを測定するための具体的な方法は示されておらず、実際にモアレパターンを測定しようとすると、特別な計測装置が必要になる。
【００１４】
第３の従来例においては、モアレパターンを測定するための具体的な方法は示されているが、モアレパターンを測定しようとすると、特別な計測装置が必要になる。
【００１５】
前記に鑑み、本発明は、下層パターンに形成されている第１の重ね合わせ測定マークと、該下層パターンの上に堆積された被処理膜の上に形成されたレジストパターンに形成されている第２の重ね合わせ測定マークとの位置ずれ量を従来の光学式測定装置を用いて、高精度に測定できるようにすることを目的とする。
【００１６】
【課題を解決するための手段】
前記の目的を達成するため、本発明に係る第１の半導体装置の製造方法は、第１の被処理膜よりなり、第１の重ね合わせ測定マークを有する下層パターンを形成する工程と、下層パターンの上に第２の被処理膜を形成した後、第２の被処理膜の上に、第２の重ね合わせ測定マークを有するレジストパターンを形成する工程と、第２の重ね合わせ測定マークの第１の重ね合わせ測定マークに対する位置ずれ量を計測する工程と、位置ずれ量が許容範囲内であるときに、第２の被処理膜に対してレジストパターンをマスクにエッチングを行なって、第２の被処理膜よりなる上層パターンを形成する工程とを備えた半導体装置の製造方法を前提とし、第１の重ね合わせ測定マークは、互いに直交する第１の直線及び第２の直線のうちの第１の直線上に位置し且つ第１の直線と第２の直線との第１の交点を介して互いに対向すると共に、それぞれが第１の直線に平行な複数の線状パターンよりなる一対の第１のラインパターン群と、第２の直線上に位置し且つ第１の交点を介して互いに対向すると共に、それぞれが第２の直線に平行な複数の線状パターンよりなる一対の第２のラインパターン群とを有し、第２の重ね合わせ測定マークは、第１の直線に対して第１の所定角度だけ傾く第３の直線及び第２の直線に対して第２の所定角度だけ傾く第４の直線のうち第３の直線上に位置し且つ第３の直線と第４の直線との第２の交点を介して互いに対向すると共に、それぞれが第３の直線に平行な複数の線状パターンよりなる一対の第３のラインパターン群と、第４の直線上に位置し且つ第２の交点を介して互いに対向すると共に、それぞれが第４の直線に平行な複数の線状パターンよりなる一対の第４のラインパターン群とを有し、位置ずれ量を計測する工程は、一対の第１のラインパターン群と一対の第３のラインパターン群とにより形成される一対の第１のモアレパターン、及び一対の第２のラインパターン群と一対の第４のラインパターン群とにより形成される一対の第２のモアレパターンに基づいて、第２の重ね合わせ測定マークの第１の重ね合わせ測定マークに対する位置ずれ量を算出する工程を含む。
【００１７】
本発明に係る第１の半導体装置の製造方法によると、一対の第１のラインパターン群と一対の第３のラインパターン群とにより形成される一対の第１のモアレパターン、及び一対の第２のラインパターン群と一対の第４のラインパターン群とにより形成される一対の第２のモアレパターンは、いずれも、直線状に現われるため、重ね合わせ測定装置のような従来の光学式測定器を用いて第１及び第２のモアレパターンを観察することができる。また、第１及び第２のモアレパターンの移動量は、第１の重ね合わせ測定マークと第２の重ね合わせ測定マークとの重ね合わせずれ量の数十倍の大きさになるので、重ね合わせずれ量の測定精度が大きく向上する。
【００１８】
本発明に係る第１の半導体装置の製造方法において、一対の第１のラインパターン群を構成する複数の線状パターン、一対の第２のラインパターン群を構成する複数の線状パターン、一対の第３のラインパターン群を構成する複数の線状パターン及び一対の第４のラインパターン群を構成する複数の線状パターンは、すべて同一のピッチで配置されていることが好ましい。
【００１９】
このようにすると、第１及び第２のモアレパターンが明確に現われるので、第１及び第２のモアレパターンの測定が正確になる。
【００２０】
この場合、同一のピッチは、上層パターンのデザインルールと等しいことが好ましい。
【００２１】
このようにすると、露光装置の収差による影響が、実際の回路パターンと重ね合わせ測定マークとの間で等しく現われるので、実際の重ね合わせずれ量が正確に反映される。
【００２２】
本発明に係る第１の半導体装置の製造方法において、一対の第１のラインパターン群は第１の交点に対して点対称であり、一対の第２のラインパターン群は第１の交点に対して点対称であり、一対の第３のラインパターン群は第２の交点に対して点対称であり、一対の第４のラインパターン群は第２の交点に対して点対称であることが好ましい。
【００２３】
このようにすると、第１及び第２のモアレパターンの移動量の測定、ひいては第１の重ね合わせ測定マークと第２の重ね合わせ測定マークとの重ね合わせずれ量の測定が容易になる。
【００２４】
本発明に係る第１の半導体装置の製造方法において、一対の第１のラインパターン群を構成する複数の線状パターン、一対の第２のラインパターン群を構成する複数の線状パターン、一対の第３のラインパターン群を構成する複数の線状パターン及び一対の第４のラインパターン群を構成する複数の線状パターンは、それぞれ、等しいピッチで配置された多数のホールパターン群よりなることが好ましい。
【００２５】
このようにすると、上層パターンがコンタクトホールが形成される層である場合に、露光装置の収差の影響を低減できるので、重ね合わせずれ量の測定精度が向上する。
【００２６】
本発明に係る第２の半導体装置の製造方法は、第１の被処理膜よりなり、第１の重ね合わせ測定マークを有する下層パターンを形成する工程と、下層パターンの上に第２の被処理膜を形成した後、第２の被処理膜の上に、第２の重ね合わせ測定マークを有するレジストパターンを形成する工程と、第２の重ね合わせ測定マークの第１の重ね合わせ測定マークに対する位置ずれ量を計測する工程と、位置ずれ量が許容範囲内であるときに、第２の被処理膜に対してレジストパターンをマスクにエッチングを行なって、第２の被処理膜よりなる上層パターンを形成する工程とを備えた半導体装置の製造方法を前提とし、第１の重ね合わせ測定マークは、互いに直交する第１の直線及び第２の直線のうち第１の直線上に位置し且つ第１の直線と第２の直線との第１の交点を介して互いに対向すると共に、それぞれが互いに平行な複数の折れ線状の線状パターンよりなる一対の第１のラインパターン群と、第２の直線上に位置し且つ第１の交点を介して互いに対向すると共に、それぞれが互いに平行な複数の折れ線状の線状パターンよりなる一対の第２のラインパターン群とを有し、第２の重ね合わせ測定マークは、第１の直線に対して平行か又は第１の所定角度だけ傾く第３の直線及び第２の直線に対して平行か又は第２の所定角度だけ傾く第４の直線のうちの第３の直線上に位置し且つ第３の直線と第４の直線との第２の交点を介して互いに対向すると共に、それぞれが互いに平行な複数の折れ線状の線状パターンよりなる一対の第３のラインパターン群と、第４の直線上に位置し且つ第２の交点を介して互いに対向すると共に、それぞれが互いに平行な複数の折れ線状の線状パターンよりなる一対の第４のラインパターン群とを有し、位置ずれ量を計測する工程は、一対の第１のラインパターン群と一対の第３のラインパターン群とにより形成される一対の第１のモアレパターン、及び一対の第２のラインパターン群と一対の第４のラインパターン群とにより形成される一対の第２のモアレパターンに基づいて、第２の重ね合わせ測定マークの第１の重ね合わせ測定マークに対する位置ずれ量を算出する工程を含む。
【００２７】
本発明に係る第２の半導体装置の製造方法によると、一対の第１のラインパターン群と一対の第３のラインパターン群とにより形成される一対の第１のモアレパターン、及び一対の第２のラインパターン群と一対の第４のラインパターン群とにより形成される一対の第２のモアレパターンは、いずれも、直線状に現われるため、重ね合わせ測定装置のような従来の光学式測定器を用いて第１及び第２のモアレパターンを観察することができる。また、第１及び第２のモアレパターンの移動量は、第１の重ね合わせ測定マークと第２の重ね合わせ測定マークとの重ね合わせずれ量の数十倍の大きさになるので、重ね合わせずれ量の測定精度が大きく向上する。
【００２８】
本発明に係る第２の半導体装置の製造方法において、一対の第１のラインパターン群を構成する複数の折れ線状の線状パターン、一対の第２のラインパターン群を構成する複数の折れ線状の線状パターン、一対の第３のラインパターン群を構成する複数の折れ線状の線状パターン及び一対の第４のラインパターン群を構成する複数の折れ線状の線状パターンは、すべて同一のピッチで配置されていることが好ましい。
【００２９】
このようにすると、第１及び第２のモアレパターンが明確に現われるので、第１及び第２のモアレパターンの測定が正確になる。
【００３０】
この場合、同一のピッチは、上層パターンのデザインルールと等しいことが好ましい。
【００３１】
このようにすると、露光装置の収差による影響が、実際の回路パターンと重ね合わせ測定マークとの間で等しく現われるので、実際の重ね合わせずれ量が正確に反映される。
【００３２】
本発明に係る第２の半導体装置の製造方法において、一対の第１のラインパターン群は第１の交点に対して点対称であり、一対の第２のラインパターン群は第１の交点に対して点対称であり、一対の第３のラインパターン群は第２の交点に対して点対称であり、一対の第４のラインパターン群は第２の交点に対して点対称であることが好ましい。
【００３３】
このようにすると、第１及び第２のモアレパターンの移動量の測定、ひいては第１の重ね合わせ測定マークと第２の重ね合わせ測定マークとの重ね合わせずれ量の測定が容易になる。
【００３４】
本発明に係る第２の半導体装置の製造方法において、一対の第１のラインパターン群を構成する複数の折れ線状の線状パターン、一対の第２のラインパターン群を構成する複数の折れ線状の線状パターン、一対の第３のラインパターン群を構成する複数の折れ線状の線状パターン及び一対の第４のラインパターン群を構成する複数の折れ線状の線状パターンは、それぞれ、等間隔で配置された多数のホールパターン群よりなることが好ましい。
【００３５】
このようにすると、上層パターンがコンタクトホールが形成される層である場合に、露光装置の収差の影響を低減できるので、重ね合わせずれ量の測定精度が向上する。
【００３６】
【発明の実施の形態】
（第１の実施形態）
以下、本発明の第１の実施形態に係る半導体装置の製造方法について、図１〜図３を参照しながら説明する。
【００３７】
まず、半導体基板上に形成されている第１の被処理膜の上に第１のレジストパターンを形成した後、第１の被処理膜に対して第１のレジストパターンをマスクしてエッチングを行なうことにより、第１の被処理膜よりなる下層パターンを形成する。この場合、該下層パターンには、図１に示す第１の重ね合わせ測定マーク１１０を形成する。
【００３８】
第１の重ね合わせ測定マーク１１０は、互いに直交する第１の直線１１１及び第２の直線１１２のうちの第１の直線１１１の上に位置し且つ第１の直線１１１と第２の直線１１２との第１の交点１１３を介して互いに対向すると共に、それぞれが第１の直線１１１に平行な複数の線状パターンよりなる一対の第１のラインパターン群１１４ａ、１１４ｂと、第２の直線１１２の上に位置し且つ第１の交点１１３を介して互いに対向すると共に、それぞれが第２の直線１１２に平行な複数の線状パターンよりなる一対の第２のラインパターン群１１５ａ、１１５ｂとを有する。尚、一対の第１のラインパターン群１１４ａ、１１４ｂは第１の交点１１３に関して点対象であると共に、一対の第１のラインパターン群１１５ａ、１１５ｂは第１の交点１１３に関して点対象である。
【００３９】
ここでは、一対の第１のラインパターン群１１４ａ、１１４ｂ及び一対の第２のラインパターン群１１５ａ、１１５ｂにおいては、すべて、複数の線状パターンのライン幅は０．２μｍであり、複数の線状パターンのピッチは０．４μｍであり、ラインパターン群の幅は１０μｍであり、ラインパターン群の長さは１０μｍである。
【００４０】
次に、下層パターンの上に第２の被処理膜を形成した後、該第２の被処理膜の上に、図２に示す第２の重ね合わせ測定マーク１２０を有するレジストパターンを形成する。
【００４１】
第２の重ね合わせ測定マーク１２０は、第１の直線１１１に対して所定角度だけ傾く第３の直線１２１及び第２の直線１１２に対して所定角度だけ傾く第４の直線１２２のうち第３の直線１２１の上に位置し且つ第３の直線１２１と第４の直線１２２との第２の交点１２３を介して互いに対向すると共に、それぞれが第３の直線１２１に平行な複数の線状パターンよりなる一対の第３のラインパターン群１２４ａ、１２４ｂと、第４の直線１２２の上に位置し且つ第２の交点１２３を介して互いに対向すると共に、それぞれが第４の直線１２２に平行な複数の線状パターンよりなる一対の第４のラインパターン群１２５ａ、１２５ｂとを有する。尚、一対の第３のラインパターン群１２４ａ、１２４ｂは第２の交点１２３に関して点対象であると共に、一対の第４のラインパターン群１２５ａ、１２５ｂは第２の交点１２３に関して点対象である。
【００４２】
ここでは、一対の第３のラインパターン群１２４ａ、１２４ｂ及び一対の第４のラインパターン群１２５ａ、１２５ｂにおいては、すべて、複数の線状パターンのライン幅は０．２μｍであり、複数の線状パターンのピッチは０．４μｍであり、ラインパターン群の幅は１０μｍであり、ラインパターン群の長さは１０μｍである。
【００４３】
次に、第２の重ね合わせ測定マーク１２０の第１の重ね合わせ測定マーク１１０に対する位置ずれ量を計測する。この工程については後述する。
【００４４】
次に、第２の重ね合わせ測定マーク１２０の第１の重ね合わせ測定マーク１１０に対する位置ずれ量が許容範囲内であるときに、第２の被処理膜に対してレジストパターンをマスクにエッチングを行なって、第２の被処理膜よりなる上層パターンを形成する。
【００４５】
ここで、第２の重ね合わせ測定マーク１２０の第１の重ね合わせ測定マーク１１０に対する位置ずれ量を計測する工程について説明する。
【００４６】
第１の重ね合わせ測定マーク１１０の中心部（第１の交点１１３）と第２の重ね合わせ測定マーク１２０の中心部（第２の交点１２３）とは一致するように設計されている。
【００４７】
図３は、第２の重ね合わせ測定マーク１２０と第１の重ね合わせ測定マーク１１０とを実際に重ねた場合の状態を示しており、両測定マークが重なった状態を光学式の重ね合わせ測定装置で観測すると、モアレパターンが観察される。前述のように、第３の直線１２１は第１の直線１１１に対して所定角度だけ傾いていると共に、第４の直線１２２は第２の直線１１２に対して所定角度だけ傾斜しているため、一対の第１のラインパターン群１１４ａ、１１４ｂと一対の第３のラインパターン群１２４ａ、１２４ｂとの重なり領域において、第１のラインパターン群１１４ａ、１１４ｂの各線状パターンと第３のラインパターン群１２４ａ、１２４ｂの各線状パターンとが所定角度を持って重なると共に、一対の第２のラインパターン群１１５ａ、１１５ｂと一対の第４のラインパターン群１２５ａ、１２５ｂとの重なり領域において、第２のラインパターン群１１５ａ、１１５ｂの各線状パターンと第４のラインパターン群１２５ａ、１２５ｂの各線状パターンとが所定角度を持って互いに重なる。
【００４８】
このため、第１のラインパターン群１１４ａ、１１４ｂと第３のラインパターン群１２４ａ、１２４ｂとの重なり領域において、周囲に比べて明度が高くなる線状の部分１３２、１３４が第１の直線１１１に垂直な方向に第１のモアレパターンとして現われると共に、第２のラインパターン群１１５ａ、１１５ｂと第４のラインパターン群１２５ａ、１２５ｂとの重なり領域において、周囲に比べて明度が高くなる線状の部分１３１、１３３が第２の直線１１２に垂直な方向に第２のモアレパターンとして現われる。従来の光学式重ね合わせ測定装置を用いて、明度が高い線状の部分（モアレパターン）１３１、１３２、１３３、１３４を検出できるので、この明度が高い線状の部分（モアレパターン）１３１〜１３４を、従来の方形状の重ね合わせ測定マークのエッジ部分と同様に取り扱うことができる。
【００４９】
明度が高い線状の部分（モアレパターン）１３１〜１３４は、第１の重ね合わせ測定マーク１１０と第２の重ね合わせ測定マーク１２０との位置関係によって移動するが、一対の第３のラインパターン群１２４ａ、１２４ｂの各線状パターンが延びる方向は第１の直線１１１に対して所定角度だけ傾き、且つ一対の第４のラインパターン群１２５ａ、１２５ｂの各線状パターンが延びる方向は第２の直線１１２に対して所定角度だけ傾いていると共に、一対の第３のラインパターン群１２４ａ、１２４ｂは第２の交点１２３に対して点対称であり且つ一対の第４のラインパターン群１２５ａ、１２５ｂは第２の交点１２３に対して点対称であるので、明度が高い線状の部分（モアレパターン）１３１の移動方向と明度が高い線状の部分（モアレパターン）１３３の移動方向は互いに等しいと共に、明度が高い線状の部分（モアレパターン）１３２の移動方向と明度が高い線状の部分（モアレパターン）１３４の移動方向とは互いに等しい。
【００５０】
そして、第３の直線１２１の第１の直線１１１に対する角度及び第４の直線１２２の第２の直線１１２に対する角度をθとし、第２の重ね合わせ測定マーク１２０の第１の重ね合わせ測定マーク１１０に対する重ね合わせずれ量をｘとし、明度が高い線状の部分（モアレパターン）１３１〜１３４の移動量をｙとすると、ｙ＝ｘ／ｔａｎθの関係が成り立つ。
【００５１】
例えば、角度θを１度、重ね合わせずれ量ｘを０．０１μｍとした場合、明度が高い線状の部分の移動量ｙは０．５７μｍとなり、重ね合わせずれ量ｘの約５７倍の大きさになる。
【００５２】
この変動量ｙを、図３（ｂ）　に示すように、内側のエッジ１３５、１３６及び外側のエッジ１３２、１３４より得られる信号に基づき、内側のエッジ１３５、１３６と外側のエッジ１３２、１３４との中心のずれ量、つまり移動量ｙを求めた後、前述の関係式から重ね合わせずれ量ｘを計算する。
【００５３】
第１の実施形態によると、内側のエッジ１３５、１３６と外側のエッジ１３２、１３４との中心のずれ量（移動量）ｙは実際の重ね合わせずれ量ｘを増幅した形で現われてくるため、従来と同様の光学式測定装置を用いる場合、従来の重ね合わせマークに比べて測定精度が大きく向上する。従って、従来と同様の光学式測定装置を用いるにも拘わらず、位置ずれの測定精度が大きく向上する。
【００５４】
また、第１及び第２の重ね合わせ測定マーク１１０、１２０のラインパターン群を構成する複数の線状パターンの線幅及びピッチを、実際の回路パターン（上層パターン）の線幅及びピッチと一致させると、露光装置の収差による影響が重ね合わせ測定マークと実際の回路パターンとの間で等しくなるので、従来の方形状の重ね合わせ測定マークと比べると、実際の重ね合わせずれ量をより正確に反映させることができる。
【００５５】
尚、第１の実施形態においては、第１及び第２の重ね合わせ測定マーク１１０、１２０のラインパターン群を構成する複数の線状パターンは、直線状であったが、これに代えて、多数のホールパターンが線状に等ピッチで並ぶ線状のホールパターンであってもよい。
【００５６】
例えば、上層のパターンがコンタクトホールが形成される層である場合、線状のホールパターンよりなる重ね合わせ測定マークを用いてマスク合わせ工程を行なうと、露光装置の収差の影響を低減することができるので、重ね合わせ精度を向上することができる。
【００５７】
以下、第１の実施形態を評価するために行なった実験結果について説明する。
【００５８】
実際の回路パターン（上層パターン）に形成された第２の重ね合わせ測定マーク１２０と、下層パターンに形成された第１の重ね合わせ測定マーク１１０との位置ずれを複数の箇所において電子式顕微鏡（ＳＥＭ）で測定すると共に、該実際の測定結果と、第１の実施形態による測定方法による測定結果及び第１の従来例に係る測定方法による測定結果とをそれぞれ比較したところ、第１の従来例と実際の測定結果とのずれ量はおよそ１０ｎｍであったのに対して、第１の実施形態と実際の測定結果とのずれ量はおよそ４ｎｍであった。
【００５９】
重ね合わせ測定マークと実際の回路パターンとのずれ量が大きい場合には、マスク合わせ工程の管理規格を本来の値よりも厳しくしなければ、所望の製品歩留まりが得られないことになる。ところが、マスク合わせ工程の管理規格を厳しくし過ぎると、マスク合わせ工程での工程歩留まりが低下する。
【００６０】
これに対して、第１の実施形態によると、マスク合わせ工程の管理規格を６ｎｍに広げることができる。この広い管理規格を実際の製造プロセスに当てはめて歩留まりを試算したところ、工程歩留まりが約３％向上することが分かった。
【００６１】
また、工程歩留まりを現在と同一に設定する場合には、半導体装置のデザインルールを６ｎｍ縮小することができる。これは実際のデバイスで考えた場合、約６％の縮小効果が見込めることになる。
【００６２】
（第２の実施形態）
以下、本発明の第２の実施形態に係る半導体装置の製造方法について、図４〜図６を参照しながら説明する。
【００６３】
まず、半導体基板上に形成されている第１の被処理膜の上に第１のレジストパターンを形成した後、第１の被処理膜に対して第１のレジストパターンをマスクしてエッチングを行なうことにより、第１の被処理膜よりなる下層パターンを形成する。この場合、該下層パターンには、図４に示す第１の重ね合わせ測定マーク２１０を形成する。
【００６４】
第１の重ね合わせ測定マーク２１０は、互いに直交する第１の直線２１１及び第２の直線２１２のうちの第１の直線２１１の上に位置し且つ第１の直線２１１と第２の直線２１２との第１の交点２１３を介して互いに対向すると共に、それぞれが第１の直線２１１に平行な複数の線分パターンよりなる一対の第１のラインパターン群２１４ａ、２１４ｂと、第２の直線２１２の上に位置し且つ第１の交点２１３を介して互いに対向すると共に、それぞれが第２の直線２１２に平行な複数の線分パターンよりなる一対の第２のラインパターン群２１５ａ、２１５ｂとを有する。尚、一対の第１のラインパターン群２１４ａ、２１４ｂは第１の交点２１３に関して点対象であると共に、一対の第１のラインパターン群２１５ａ、２１５ｂは第１の交点２１３に関して点対象である。
【００６５】
ここでは、一対の第１のラインパターン群２１４ａ、２１４ｂ及び一対の第２のラインパターン群２１５ａ、２１５ｂにおいては、すべて、複数の線状パターンのライン幅は０．２μｍであり、複数の線状パターンのピッチは０．４μｍであり、ラインパターン群の幅は１０μｍであり、ラインパターン群の長さは１０μｍである。
【００６６】
次に、下層パターンの上に第２の被処理膜を形成した後、該第２の被処理膜の上に、図５（ａ）　に示す第２の重ね合わせ測定マーク２２０を有するレジストパターンを形成する。
【００６７】
第２の重ね合わせ測定マーク２２０は、第１の直線２１１と平行な第３の直線２２１及び第２の直線２１２と平行な第４の直線２２２のうち第３の直線２２１の上に位置し且つ第３の直線２２１と第４の直線２２２との第２の交点２２３を介して互いに対向すると共に、それぞれが互いに平行な複数の折れ線パターンよりなる一対の第３のラインパターン群２２４ａ、２２４ｂと、第４の直線２２２の上に位置し且つ第２の交点２２３を介して互いに対向すると共に、それぞれが互いに平行な複数の折れ線パターンよりなる一対の第４のラインパターン群２２５ａ、２２５ｂとを有する。尚、一対の第３のラインパターン群２２４ａ、２２４ｂは第２の交点２２３に関して点対象であると共に、一対の第４のラインパターン群２２５ａ、２２５ｂは第２の交点２２３に関して点対象である。
【００６８】
図５（ｂ）　は、一対の第２のラインパターン群２２４ａ、２２４ｂ及び一対の第２のラインパターン群２２５ａ、２２５ｂを構成する各折れ線の第３の直線２２１又は第４の直線２２２に対する角度α、βを示している。角度αと角度βとは異なっていてもよいし等しくてもよいが、第２の実施形態においては角度αと角度βとは等しい。
【００６９】
ここでは、一対の第３のラインパターン群２２４ａ、２２４ｂ及び一対の第４のラインパターン群２２５ａ、２２５ｂにおいては、すべて、複数の折れ線パターンのライン幅は０．２μｍであり、複数の折れ線パターンのピッチは０．４μｍであり、ラインパターン群の幅は１０μｍであり、ラインパターン群の長さは１０μｍである。
【００７０】
次に、第２の重ね合わせ測定マーク２２０の第１の重ね合わせ測定マーク２１０に対する位置ずれ量を計測する。この工程については後述する。
【００７１】
次に、第２の重ね合わせ測定マーク２２０の第１の重ね合わせ測定マーク２１０に対する位置ずれ量が許容範囲内であるときに、第２の被処理膜に対してレジストパターンをマスクにエッチングを行なって、第２の被処理膜よりなる上層パターンを形成する。
【００７２】
ここで、第２の重ね合わせ測定マーク２２０の第１の重ね合わせ測定マーク２１０に対する位置ずれ量を計測する工程について説明する。
【００７３】
第１の重ね合わせ測定マーク２１０の中心部（第１の交点２１３）と第２の重ね合わせ測定マーク２２０の中心部（第２の交点２２３）とは一致するように設計されている。
【００７４】
図６は、第２の重ね合わせ測定マーク２２０と第１の重ね合わせ測定マーク２１０とを実際に重ねた場合の状態を示しており、両測定マークが重なった状態を光学式の重ね合わせ測定装置で観測すると、モアレパターンが観察される。前述のように、第１の直線２１１と第３の直線２１３とは互いに平行であると共に、一対の第１のラインパターン群２１４ａ、２１４ｂは第１の直線２１１に平行な複数の線分よりなり且つ一対の第３のラインパターン群２２４ａ、２２４ｂは互いに平行な複数の折れ線よりなるため、一対の第１のラインパターン群２１４ａ、２１４ｂと一対の第３のラインパターン群２２４ａ、２２４ｂとの重なり領域において、周囲に比べて明度が高くなる線状の部分（モアレパターン）２３２、２３４が第１の直線２１１（第３の直線２２１）に垂直な方向に現われる。また、同様にして、第２の直線２１２と第４の直線２２２とは互いに平行であると共に、一対の第２のラインパターン群２１５ａ、２１５ｂは第１の直線２１１に平行な複数の線分よりなり且つ一対の第４のラインパターン群２２５ａ、２２５ｂは互いに平行な複数の折れ線よりなるため、一対の第２のラインパターン群２１５ａ、２１５ｂと一対の第４のラインパターン群２２５ａ、２２５ｂとの重なり領域において、周囲に比べて明度が高くなる線状の部分（モアレパターン）２３１、２３３が第２の直線２１２（第４の直線２２２）に垂直な方向に現われる。従来の光学式重ね合わせ測定装置を用いて、明度が高い線状の部分（モアレパターン）２３１、２３２、２３３、２３４を検出できるので、この明度が高い線状の部分（モアレパターン）２３１〜２３４を、従来の方形状の重ね合わせ測定マークのエッジ部分と同様に取り扱うことができる。
【００７５】
明度が高い線状の部分（モアレパターン）２３１〜２３４は、第１の重ね合わせ測定マーク２１０と第２の重ね合わせ測定マーク２２０との位置関係によって移動するが、一対の第１のラインパターン群２１４ａ、２１４ｂは直線状のパターンよりなるのに対して一対の第３のラインパターン群２２４ａ、２２４ｂは折れ線状のパターンよりなり、また、一対の第２のラインパターン群２１５ａ、２１５ｂは直線状のパターンよりなるのに対して一対の第４のラインパターン群２２５ａ、２２５ｂは折れ線状のパターンよりなるので、明度が高い線状の部分（モアレパターン）２３１の移動方向と明度が高い線状の部分（モアレパターン）２３３の移動方向は互いに等しいと共に、明度が高い線状の部分（モアレパターン）２３２の移動方向と明度が高い線状の部分（モアレパターン）２３４の移動方向とは互いに等しい。
【００７６】
そして、第１のラインパターン群２１４ａ、２１４ｂと第３のラインパターン群２２４ａ、２２４ｂとの角度、及び第２のラインパターン群２１５ａ、２１５ｂと第４のラインパターン群２２５ａ、２２５ｂとの角度をθとし、第２の重ね合わせ測定マーク２２０の第１の重ね合わせ測定マーク２１０に対する重ね合わせずれ量をｘとし、明度が高い線状の部分１３１〜１３４の移動量をｙとすると、ｙ＝ｘ／ｔａｎθの関係が成り立つ。
【００７７】
例えば、角度θを１度、重ね合わせずれ量ｘを０．０１μｍとした場合、明度が高い線状の部分（モアレパターン）の移動量ｙは０．５７μｍとなり、重ね合わせずれ量ｘの約５７倍の大きさになる。
【００７８】
この変動量ｙを、図６（ｂ）　に示すように、内側のエッジ２３５、２３６及び外側のエッジ２３２、２３４より得られる信号に基づき、内側のエッジ２３５、２３６と外側のエッジ２３２、２３４との中心のずれ量、つまり移動量ｙを求めた後、前述の関係式から重ね合わせずれ量ｘを計算する。
【００７９】
第２の実施形態によると、内側のエッジ２３５、２３６と外側のエッジ２３２、２３４との中心のずれ量（移動量）ｙは実際の重ね合わせずれ量ｘを増幅した形で現われてくるため、従来と同様の光学式重ね合わせ測定装置を用いる場合、従来の重ね合わせマークに比べて測定精度が大きく向上する。従って、従来と同様の重ね合わせ測定装置を用いるにも拘わらず、位置ずれの測定精度が大きく向上する。
【００８０】
また、第１及び第２の重ね合わせ測定マーク２１０、２２０のラインパターン群を構成する複数の線状パターンの線幅及びピッチを、実際の回路パターン（上層パターン）の線幅及びピッチと一致させると、露光装置の収差による影響が重ね合わせ測定マークと実際の回路パターンとの間で等しくなるので、従来の方形状の重ね合わせ測定マークと比べると、実際の重ね合わせずれ量をより正確に反映させることができる。
【００８１】
尚、第２の実施形態においては、第１の重ね合わせ測定マーク２１０のラインパターン群を構成する複数の線分は直線であったが、これに代えて、多数のホールパターンが直線状に等ピッチで並ぶ直線状のホールパターンであると共に、第２の重ね合わせ測定マーク２２０のラインパターン群を構成する複数の折れ線状パターンは、折れ線であったが、これに代えて、多数のホールパターンが折れ線状に等ピッチで並ぶ折れ線状のホールパターンであってもよい。
【００８２】
例えば、上層のパターンがコンタクトホールが形成される層である場合、多数のホールパターンよりなる重ね合わせ測定マークを用いてマスク合わせ工程を行なうと、露光装置の収差の影響を低減することができるので、重ね合わせ精度を向上することができる。
【００８３】
以下、第２の実施形態を評価するために行なった実験結果について説明する。
【００８４】
実際の回路パターン（上層パターン）に形成された第２の重ね合わせ測定マーク２２０と、下層パターンに形成された第１の重ね合わせ測定マーク２１０との位置ずれを複数の箇所において電子式顕微鏡（ＳＥＭ）で測定すると共に、該実際の測定結果と、第２の実施形態による測定方法による測定結果及び第１の従来例に係る測定方法による測定結果とをそれぞれ比較したところ、第１の従来例と実際の測定結果とのずれ量はおよそ１０ｎｍであったのに対して、第２の実施形態と実際の測定結果とのずれ量はおよそ４ｎｍであった。
【００８５】
重ね合わせ測定マークと実際の回路パターンとのずれ量が大きい場合には、マスク合わせ工程の管理規格を本来の値よりも厳しくしなければ、所望の製品歩留まりが得られないことになる。ところが、マスク合わせ工程の管理規格を厳しくし過ぎると、マスク合わせ工程での工程歩留まりが低下する。
【００８６】
これに対して、第２の実施形態によると、マスク合わせ工程の管理規格を６ｎｍに広げることができる。この広い管理規格を実際の製造プロセスに当てはめて歩留まりを試算したところ、工程歩留まりが約３％向上することが分かった。
【００８７】
また、工程歩留まりを現在と同一に設定する場合には、半導体装置のデザインルールを６ｎｍ縮小することができる。これは実際のデバイスで考えた場合、約６％の縮小効果が見込めることになる。
【００８８】
【発明の効果】
本発明に係る第１又は第２の半導体装置の製造方法によると、従来の光学式測定器を用いて第１及び第２のモアレパターンを観察することができると共に、重ね合わせずれ量の測定精度が大きく向上する。
【図面の簡単な説明】
【図１】第１の実施形態に係る半導体装置の製造方法に用いる第１の重ね合わせ測定マークの平面図である。
【図２】第１の実施形態に係る半導体装置の製造方法に用いる第２の重ね合わせ測定マークの平面図である。
【図３】（ａ）　は第１の実施形態に係る半導体装置の製造方法において、第１の重ね合わせ測定マークと第２の重ね合わせ測定マークとを重ね合わせた状態を示す平面図であり、（ｂ）　は第１の実施形態に係る半導体装置の製造方法における重ね合わせずれ量を説明する図である。
【図４】第２の実施形態に係る半導体装置の製造方法に用いる第１の重ね合わせ測定マークの平面図である。
【図５】（ａ）　は第２の実施形態に係る半導体装置の製造方法に用いる第２の重ね合わせ測定マークの平面図であり、（ｂ）　は第２の重ね合わせ測定マークの部分拡大図である。
【図６】（ａ）　は第２の実施形態に係る半導体装置の製造方法において、第１の重ね合わせ測定マークと第２の重ね合わせ測定マークとを重ね合わせた状態を示す平面図であり、（ｂ）　は第２の実施形態に係る半導体装置の製造方法における重ね合わせずれ量を説明する図である。
【図７】従来の半導体装置の製造方法における重ね合わせずれ量を説明する図である。
【符号の説明】
１１０　第１の重ね合わせ測定マーク
１１１　第１の直線
１１２　第２の直線
１１３　第１の交点
１１４ａ、１１４ｂ　一対の第１のラインパターン群
１１５ａ、１１５ｂ　一対の第２のラインパターン群
１２０　第２の重ね合わせ測定マーク
１２１　第１の直線
１２２　第２の直線
１２３　第２の交点
１２４ａ、１２４ｂ　一対の第１のラインパターン群
１２５ａ、１２５ｂ　一対の第２のラインパターン群
１３１　明度が高い線状の部分（モアレパターン）
１３２　　明度が高い線状の部分（モアレパターン）
１３３　　明度が高い線状の部分（モアレパターン）
１３４　　明度が高い線状の部分（モアレパターン）
１３５　内側のエッジ
１３６　内側のエッジ
２１０　第１の重ね合わせ測定マーク
２１１　第１の直線
２１２　第２の直線
２１３　第１の交点
２１４ａ、２１４ｂ　一対の第１のラインパターン群
２１５ａ、２１５ｂ　一対の第２のラインパターン群
２２０　第２の重ね合わせ測定マーク
２２１　第１の直線
２２２　第２の直線
２２３　第２の交点
２２４ａ、２２４ｂ　一対の第１のラインパターン群
２２５ａ、２２５ｂ　一対の第２のラインパターン群
２３１　明度が高い線状の部分（モアレパターン）
２３２　　明度が高い線状の部分（モアレパターン）
２３３　　明度が高い線状の部分（モアレパターン）
２３４　　明度が高い線状の部分（モアレパターン）
２３５　内側のエッジ
２３６　内側のエッジ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device, wherein a first overlay measurement mark formed on a lower layer pattern and a film to be processed deposited on the lower layer pattern are formed. The present invention relates to a method for measuring a positional shift amount with respect to a second overlay measurement mark formed on a resist pattern formed on a substrate.
[0002]
[Prior art]
With the miniaturization and high integration of semiconductor integrated circuit devices, further miniaturization of the pattern size is required, and in the latest semiconductor device manufacturing process, semiconductor chips having a minimum line width of 130 nm level are mass-produced. It is getting.
[0003]
On the other hand, in order to realize miniaturization of a device (semiconductor chip), it is important to precisely align a pattern in an upper layer with a pattern in a lower layer in addition to miniaturization of a pattern. By reducing the overlay error between the upper layer pattern and the lower layer pattern (hereinafter, simply referred to as the overlay error between the patterns), the design margin required for the overlay error between the patterns is reduced. As a result, the size of the device can be reduced.
[0004]
Incidentally, the measurement of the overlay error between the patterns is performed on the first overlay measurement mark (first alignment measurement mark) formed on the lower layer pattern and on the resist pattern for forming the upper layer pattern. This is performed by measuring the positional deviation between the second overlay measurement mark (second alignment measurement mark) and the second overlay measurement mark using an overlay accuracy measurement device (alignment accuracy measurement device).
[0005]
Hereinafter, as a first conventional example, a method of measuring a positional shift between a first overlay measurement mark and a second overlay measurement mark using an overlay accuracy measuring device will be described with reference to FIGS. This will be described with reference to FIG.
[0006]
In FIGS. 7A and 7B, reference numeral 11 denotes a first overlay measurement mark formed on the lower layer pattern, which is formed by lithography, etching, or the like before the upper layer pattern to be formed. Is used to form a rectangular frame. On the other hand, reference numeral 12 denotes a square second overlay measurement mark formed on the resist pattern for forming the upper layer pattern, which is formed inside the first overlay measurement mark 11. The center position of the first overlay measurement mark 11 and the center position of the second overlay measurement mark 12 are set to coincide, and the inner diameter of the first overlay measurement mark 11 and the second overlay The outer diameter of the alignment measurement mark 12 is set to about 10 to 20 μm.
[0007]
The amount of displacement between the first overlay measurement mark 11 and the second overlay measurement mark 12 is measured by an optical overlay measurement device. In this case, the center position is obtained from the outer diameter of the first overlay measurement mark 11 and the center position is obtained from the outer diameter of the second overlay measurement mark 12, and the distance δ between the center positions is obtained from the two center positions. Is calculated, the amount of displacement between the first overlay measurement mark 11 and the second overlay measurement mark 12 is measured.
[0008]
Hereinafter, as a second conventional example, an overlay measurement method using moiré interference as described in, for example, Japanese Patent Application Laid-Open No. 03-268415 will be described. That is, using the first overlay measurement mark and the second overlay measurement mark, each of which is composed of a plurality of rings, the moire pattern is formed by the overlap between the first overlay measurement mark and the second overlay measurement mark. This is a method of detecting overlay displacement by observing the moire pattern.
[0009]
As a third conventional example, an overlay measurement mark using moiré interference as disclosed in Japanese Patent Application Laid-Open No. 03-134504 is also known.
[0010]
[Problems to be solved by the invention]
Hereinafter, the problem of the first conventional example will be described.
[0011]
In the conventional device, the measurement accuracy of the overlay measurement apparatus had a sufficient margin with respect to the required overlay measurement accuracy. However, in the device of 130 nm rule currently mass-produced, the required overlay accuracy is not enough. Approximately 80 nm, and with further miniaturization in the future, the requirements for overlay accuracy will become more stringent. However, as long as a conventional optical inspection method is used, the overlay measurement apparatus does not have a performance capable of measuring overlay accuracy required from a device.
[0012]
Further, the shape of the conventional overlay measurement mark is a square shape having one side of 10 to 20 μm, which is largely different from the size of a circuit pattern (actual pattern) actually used. As described above, when the difference between the size of the overlay measurement mark and the size of the actual pattern is large, the position where the overlay measurement mark forms an image and the position where the actual pattern forms on the base layer are affected by the aberration of the exposure apparatus. May be different from. When such a difference occurs, even if the misalignment between the overlay measurement marks is accurately measured, a short circuit occurs between the patterns because a desired result cannot be obtained.
[0013]
According to the second conventional example, it is possible to accurately detect a positional shift generated between the first overlay measurement mark and the second overlay measurement mark, but the first overlay measurement mark and the second overlay measurement mark can be accurately detected. It is difficult to detect the amount of displacement and the direction of the displacement between the two overlay measurement marks. Further, in the second conventional example, a specific method for measuring a moiré pattern is not shown, and a special measuring device is required to actually measure a moiré pattern.
[0014]
In the third conventional example, a specific method for measuring a moire pattern is shown, but a special measuring device is required to measure a moire pattern.
[0015]
In view of the above, the present invention provides a method of forming a first overlay measurement mark formed on a lower layer pattern and a resist pattern formed on a film to be processed deposited on the lower layer pattern. It is an object of the present invention to be able to measure the amount of displacement with respect to the second overlay measurement mark with high accuracy using a conventional optical measuring device.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, a first method for manufacturing a semiconductor device according to the present invention includes a step of forming a lower layer pattern comprising a first processing target film and having a first overlay measurement mark; Forming a second target film on the second target film, forming a resist pattern having a second overlay measurement mark on the second target film, and forming a second resist pattern on the second target film. Measuring the amount of misalignment with respect to the first overlay measurement mark; and etching the second film to be processed using the resist pattern as a mask when the amount of misalignment is within an allowable range. A method for manufacturing a semiconductor device including a step of forming an upper layer pattern made of a film to be processed, wherein the first overlay measurement mark is a first straight line and a second straight line which are orthogonal to each other. On a straight line A pair of first line pattern groups each including a plurality of linear patterns which are positioned and are opposed to each other via a first intersection of the first straight line and the second straight line, and each of which is parallel to the first straight line; And a pair of second line pattern groups each comprising a plurality of linear patterns that are located on the second straight line, face each other via the first intersection, and are each parallel to the second straight line. The second overlay measurement mark is formed of a third straight line inclined by a first predetermined angle with respect to the first straight line and a fourth straight line inclined by a second predetermined angle with respect to the second straight line. A pair of linear patterns located on the third straight line, opposed to each other via a second intersection point of the third straight line and the fourth straight line, and each including a plurality of linear patterns parallel to the third straight line. A third line pattern group and a second line pattern A pair of fourth line pattern groups each including a plurality of linear patterns each of which is opposed to each other via a point and which is parallel to the fourth straight line. A pair of first moire patterns formed by one line pattern group and a pair of third line pattern groups, and a pair of second line pattern groups and a pair of fourth line pattern groups. Calculating a positional shift amount of the second overlay measurement mark with respect to the first overlay measurement mark based on the pair of second moiré patterns.
[0017]
According to the first method for manufacturing a semiconductor device of the present invention, the pair of first moire patterns formed by the pair of first line pattern groups and the pair of third line pattern groups, and the pair of second moire patterns are formed. A pair of second moiré patterns formed by a pair of line patterns and a pair of fourth line patterns appear in a straight line, so that a conventional optical measuring device such as an overlay measuring device can be used. To observe the first and second moiré patterns. In addition, since the amount of movement of the first and second moiré patterns is several tens times the amount of misalignment between the first overlay measurement mark and the second overlay measurement mark, the overlay misalignment is large. The measurement accuracy of the quantity is greatly improved.
[0018]
In the first method for manufacturing a semiconductor device according to the present invention, a plurality of linear patterns forming a pair of first line pattern groups, a plurality of linear patterns forming a pair of second line pattern groups, a pair of It is preferable that the plurality of linear patterns forming the third line pattern group and the plurality of linear patterns forming the pair of fourth line pattern groups are all arranged at the same pitch.
[0019]
In this way, the first and second moiré patterns appear clearly, so that the measurement of the first and second moiré patterns becomes accurate.
[0020]
In this case, the same pitch is preferably equal to the design rule of the upper layer pattern.
[0021]
In this case, the influence of the aberration of the exposure apparatus appears equally between the actual circuit pattern and the overlay measurement mark, so that the actual overlay deviation is accurately reflected.
[0022]
In the first method for manufacturing a semiconductor device according to the present invention, the pair of first line pattern groups is point-symmetric with respect to the first intersection, and the pair of second line pattern groups is with respect to the first intersection. Preferably, the pair of third line pattern groups are point-symmetric with respect to the second intersection, and the pair of fourth line pattern groups are point-symmetric with respect to the second intersection. .
[0023]
This facilitates the measurement of the amount of movement of the first and second moiré patterns and the measurement of the amount of misalignment between the first overlay measurement mark and the second overlay measurement mark.
[0024]
In the first method for manufacturing a semiconductor device according to the present invention, a plurality of linear patterns forming a pair of first line pattern groups, a plurality of linear patterns forming a pair of second line pattern groups, a pair of Each of the plurality of linear patterns forming the third line pattern group and the plurality of linear patterns forming the pair of fourth line pattern groups may be formed of a large number of hole pattern groups arranged at equal pitches. preferable.
[0025]
In this case, when the upper layer pattern is a layer in which a contact hole is formed, the influence of the aberration of the exposure apparatus can be reduced, so that the measurement accuracy of the overlay shift amount is improved.
[0026]
A second method of manufacturing a semiconductor device according to the present invention includes a step of forming a lower layer pattern having a first processing target film and having a first overlay measurement mark, and a step of forming a second processing target on the lower layer pattern. After forming the film, forming a resist pattern having a second overlay measurement mark on the second film to be processed; and positioning the second overlay measurement mark with respect to the first overlay measurement mark. A step of measuring a shift amount; and, when the shift amount is within an allowable range, etching the second processing target film using a resist pattern as a mask to form an upper layer pattern formed of the second processing target film. The first overlay measurement mark is located on the first straight line among the first straight line and the second straight line that are orthogonal to each other, and the first overlay measurement mark is formed on the first straight line. Line and the second A pair of first line pattern groups each including a plurality of polygonal linear patterns which are opposed to each other via a first intersection with a straight line, and each of which is parallel to each other; A pair of second line pattern groups each composed of a plurality of polygonal linear patterns that are opposed to each other via one intersection and are parallel to each other, and the second overlay measurement mark is On a third straight line of a third straight line which is parallel to the straight line or tilts by a first predetermined angle and a fourth straight line which is parallel to the second straight line or tilted by a second predetermined angle A pair of third line pattern groups each including a plurality of polygonal linear patterns which are located and opposed to each other via a second intersection point of the third straight line and the fourth straight line, and are respectively parallel to each other; , Located on a fourth straight line and And a pair of fourth line pattern groups each including a plurality of polygonal linear patterns that are opposed to each other via two intersections, and each of which includes a pair of polygonal linear patterns. A pair of first moire patterns formed by a first line pattern group and a pair of third line pattern groups, and a pair of second line pattern groups and a pair of fourth line pattern groups are formed. Calculating a displacement amount of the second overlay measurement mark with respect to the first overlay measurement mark based on the pair of second moiré patterns.
[0027]
According to the second method for manufacturing a semiconductor device of the present invention, the pair of first moire patterns formed by the pair of first line pattern groups and the pair of third line pattern groups, and the pair of second A pair of second moiré patterns formed by a pair of line patterns and a pair of fourth line patterns appear in a straight line, so that a conventional optical measuring device such as an overlay measuring device can be used. To observe the first and second moiré patterns. In addition, since the amount of movement of the first and second moiré patterns is several tens times the amount of misalignment between the first overlay measurement mark and the second overlay measurement mark, the overlay misalignment is large. The measurement accuracy of the quantity is greatly improved.
[0028]
In the second method for manufacturing a semiconductor device according to the present invention, a plurality of polygonal linear patterns forming a pair of first line pattern groups and a plurality of polygonal linear patterns forming a pair of second line pattern groups are provided. The linear pattern, a plurality of polygonal linear patterns forming a pair of third line pattern groups, and a plurality of polygonal linear patterns forming a pair of fourth line pattern groups are all at the same pitch. Preferably, they are arranged.
[0029]
In this way, the first and second moiré patterns appear clearly, so that the measurement of the first and second moiré patterns becomes accurate.
[0030]
In this case, the same pitch is preferably equal to the design rule of the upper layer pattern.
[0031]
In this case, the influence of the aberration of the exposure apparatus appears equally between the actual circuit pattern and the overlay measurement mark, so that the actual overlay deviation is accurately reflected.
[0032]
In the second method for manufacturing a semiconductor device according to the present invention, the pair of first line pattern groups is point-symmetric with respect to the first intersection, and the pair of second line pattern groups is with respect to the first intersection. Preferably, the pair of third line pattern groups are point-symmetric with respect to the second intersection, and the pair of fourth line pattern groups are point-symmetric with respect to the second intersection. .
[0033]
This facilitates the measurement of the amount of movement of the first and second moiré patterns and the measurement of the amount of misalignment between the first overlay measurement mark and the second overlay measurement mark.
[0034]
In the second method for manufacturing a semiconductor device according to the present invention, a plurality of polygonal linear patterns forming a pair of first line pattern groups and a plurality of polygonal linear patterns forming a pair of second line pattern groups are provided. The linear pattern, a plurality of polygonal linear patterns forming a pair of third line pattern groups, and a plurality of polygonal linear patterns forming a pair of fourth line pattern groups are respectively equidistant. It is preferable that the plurality of hole patterns be arranged.
[0035]
In this case, when the upper layer pattern is a layer in which a contact hole is formed, the influence of the aberration of the exposure apparatus can be reduced, so that the measurement accuracy of the overlay shift amount is improved.
[0036]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.
[0037]
First, after forming a first resist pattern on a first processing target film formed on a semiconductor substrate, etching is performed on the first processing target film by masking the first resist pattern. Thus, a lower layer pattern made of the first film to be processed is formed. In this case, the first overlay measurement mark 110 shown in FIG. 1 is formed in the lower layer pattern.
[0038]
The first overlay measurement mark 110 is located on the first straight line 111 of the first straight line 111 and the second straight line 112 which are orthogonal to each other, and is located on the first straight line 111 and the second straight line 112. And a pair of first line pattern groups 114a and 114b, each of which includes a plurality of linear patterns parallel to the first straight line 111, and a second straight line 112, respectively. It has a pair of second line pattern groups 115a and 115b, which are located above and are opposed to each other via the first intersection point 113 and each include a plurality of linear patterns parallel to the second straight line 112. Note that the pair of first line pattern groups 114a and 114b are point targets with respect to the first intersection 113, and the pair of first line pattern groups 115a and 115b are point targets with respect to the first intersection 113.
[0039]
Here, in each of the pair of first line pattern groups 114a and 114b and the pair of second line pattern groups 115a and 115b, the line width of the plurality of linear patterns is 0.2 μm, and the The pattern pitch is 0.4 μm, the width of the line pattern group is 10 μm, and the length of the line pattern group is 10 μm.
[0040]
Next, after forming a second film to be processed on the lower layer pattern, a resist pattern having the second overlay measurement mark 120 shown in FIG. 2 is formed on the second film to be processed.
[0041]
The second overlay measurement mark 120 is formed by a third straight line 121 inclined by a predetermined angle with respect to the first straight line 111 and a fourth straight line 122 inclined by a predetermined angle with respect to the second straight line 112. A plurality of linear patterns located on the straight line 121 and opposed to each other via a second intersection 123 between the third straight line 121 and the fourth straight line 122 and each being parallel to the third straight line 121 And a plurality of third line pattern groups 124a and 124b, which are located on the fourth straight line 122 and face each other via the second intersection 123, and each of which is parallel to the fourth straight line 122. It has a pair of fourth line pattern groups 125a and 125b composed of linear patterns. Note that the pair of third line pattern groups 124a and 124b are point targets with respect to the second intersection 123, and the pair of fourth line pattern groups 125a and 125b are point targets with respect to the second intersection 123.
[0042]
Here, in each of the pair of third line pattern groups 124a and 124b and the pair of fourth line pattern groups 125a and 125b, the line width of the plurality of linear patterns is 0.2 μm, and the The pattern pitch is 0.4 μm, the width of the line pattern group is 10 μm, and the length of the line pattern group is 10 μm.
[0043]
Next, the amount of displacement of the second overlay measurement mark 120 with respect to the first overlay measurement mark 110 is measured. This step will be described later.
[0044]
Next, when the amount of displacement of the second overlay measurement mark 120 with respect to the first overlay measurement mark 110 is within an allowable range, etching is performed on the second processing target film using a resist pattern as a mask. Thus, an upper layer pattern made of the second film to be processed is formed.
[0045]
Here, the step of measuring the amount of displacement of the second overlay measurement mark 120 with respect to the first overlay measurement mark 110 will be described.
[0046]
The center of the first overlay measurement mark 110 (first intersection 113) is designed to coincide with the center of the second overlay measurement mark 120 (second intersection 123).
[0047]
FIG. 3 shows a state in which the second overlay measurement mark 120 and the first overlay measurement mark 110 are actually overlapped, and the state in which the two overlay marks are overlapped is determined by an optical overlay measurement apparatus. , A moiré pattern is observed. As described above, the third straight line 121 is inclined by a predetermined angle with respect to the first straight line 111, and the fourth straight line 122 is inclined by a predetermined angle with respect to the second straight line 112. In the overlapping region between the pair of first line pattern groups 114a and 114b and the pair of third line pattern groups 124a and 124b, each linear pattern of the first line pattern groups 114a and 114b and the third line pattern group 124a , 124b overlap with a predetermined angle, and the second line pattern is formed in an overlapping area between the pair of second line pattern groups 115a, 115b and the pair of fourth line pattern groups 125a, 125b. Each linear pattern of the groups 115a and 115b and each linear pattern of the fourth line pattern groups 125a and 125b have a predetermined angle. With overlap each other.
[0048]
For this reason, in the overlapping area between the first line pattern groups 114a and 114b and the third line pattern groups 124a and 124b, the linear portions 132 and 134 whose brightness is higher than the surroundings are formed on the first straight line 111. A linear portion that appears as a first moiré pattern in the vertical direction and has a higher brightness than the surroundings in an overlapping region of the second line pattern groups 115a and 115b and the fourth line pattern groups 125a and 125b. 131 and 133 appear as a second moiré pattern in a direction perpendicular to the second straight line 112. Using the conventional optical overlay measurement device, the linear portions (Moire patterns) 131, 132, 133, and 134 having high brightness can be detected, and thus the linear portions (Moire patterns) 131 to 134 having high brightness can be detected. Can be handled in the same manner as the edge portion of a conventional square overlay measurement mark.
[0049]
The linear portions (moiré patterns) 131 to 134 having high brightness move depending on the positional relationship between the first overlay measurement mark 110 and the second overlay measurement mark 120, but a pair of third line pattern groups The direction in which the linear patterns 124a and 124b extend is inclined at a predetermined angle with respect to the first straight line 111, and the direction in which the linear patterns of the pair of fourth line pattern groups 125a and 125b extend is the second straight line 112. The pair of third line pattern groups 124a and 124b are point-symmetric with respect to the second intersection 123, and the pair of fourth line pattern groups 125a and 125b are Since it is point-symmetric with respect to the intersection 123, the moving direction of the linear portion (moire pattern) 131 with high brightness and the linear portion (moire pattern) with high brightness The movement direction are equal to each other in the pattern) 133, are equal to each other and the moving direction of the moving direction and the brightness is high linear portion (moire pattern) 134 of the high lightness linear portion (moire pattern) 132.
[0050]
The angle of the third straight line 121 with respect to the first straight line 111 and the angle of the fourth straight line 122 with respect to the second straight line 112 are represented by θ, and the first overlay measurement mark 110 of the second overlay measurement mark 120 is represented by θ. Is assumed to be x, and the amount of movement of the linear portions (moiré patterns) 131 to 134 having high brightness is assumed to be y, the relationship y = x / tan θ is established.
[0051]
For example, when the angle θ is 1 degree and the overlay displacement amount x is 0.01 μm, the moving amount y of the linear portion having high brightness is 0.57 μm, which is about 57 times the overlay displacement amount x. become.
[0052]
As shown in FIG. 3 (b), the variation y is calculated based on the signals obtained from the inner edges 135 and 136 and the outer edges 132 and 134 and the inner edges 135 and 136 and the outer edges 132 and 134. Is calculated, that is, the shift amount y is calculated, and then the overlay shift amount x is calculated from the above relational expression.
[0053]
According to the first embodiment, the shift amount (movement amount) y of the center between the inner edges 135 and 136 and the outer edges 132 and 134 appears in an amplified form of the actual overlay shift amount x. When an optical measuring device similar to the conventional one is used, the measurement accuracy is greatly improved as compared with the conventional overlay mark. Therefore, the accuracy of measuring the positional deviation is greatly improved despite the use of the same optical measuring device as the conventional one.
[0054]
Further, the line widths and pitches of a plurality of linear patterns constituting the line pattern group of the first and second overlay measurement marks 110 and 120 are matched with the line width and pitch of an actual circuit pattern (upper layer pattern). And the influence of the aberration of the exposure device becomes equal between the overlay measurement mark and the actual circuit pattern, so that the actual overlay deviation amount is more accurately reflected as compared with the conventional rectangular overlay measurement mark. Can be done.
[0055]
In the first embodiment, the plurality of linear patterns constituting the line pattern group of the first and second overlay measurement marks 110 and 120 are linear. May be linear hole patterns arranged linearly at equal pitches.
[0056]
For example, when the pattern of the upper layer is a layer in which a contact hole is formed, the effect of the aberration of the exposure apparatus can be reduced by performing the mask alignment process using the overlay measurement mark including the linear hole pattern. Therefore, overlay accuracy can be improved.
[0057]
Hereinafter, results of experiments performed to evaluate the first embodiment will be described.
[0058]
The misalignment between the second overlay measurement mark 120 formed on the actual circuit pattern (upper layer pattern) and the first overlay measurement mark 110 formed on the lower layer pattern is determined at a plurality of locations by an electronic microscope (SEM). ), And the actual measurement result is compared with the measurement result by the measurement method according to the first embodiment and the measurement result by the measurement method according to the first conventional example. The deviation from the actual measurement result was about 10 nm, whereas the deviation from the first embodiment and the actual measurement result was about 4 nm.
[0059]
If the amount of deviation between the overlay measurement mark and the actual circuit pattern is large, a desired product yield cannot be obtained unless the management standard for the mask alignment process is stricter than the original value. However, if the management standard of the mask alignment process is too strict, the process yield in the mask alignment process is reduced.
[0060]
On the other hand, according to the first embodiment, the management standard of the mask alignment process can be extended to 6 nm. A trial calculation of the yield by applying this wide management standard to an actual manufacturing process showed that the process yield was improved by about 3%.
[0061]
When the process yield is set to be the same as the current one, the design rule of the semiconductor device can be reduced by 6 nm. This means that a reduction effect of about 6% can be expected in an actual device.
[0062]
(Second embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS.
[0063]
First, after forming a first resist pattern on a first processing target film formed on a semiconductor substrate, etching is performed on the first processing target film by masking the first resist pattern. Thus, a lower layer pattern made of the first film to be processed is formed. In this case, the first overlay measurement mark 210 shown in FIG. 4 is formed in the lower layer pattern.
[0064]
The first overlay measurement mark 210 is located on the first straight line 211 of the first straight line 211 and the second straight line 212 which are orthogonal to each other, and is located on the first straight line 211 and the second straight line 212. And a pair of first line pattern groups 214a and 214b each including a plurality of line segment patterns each of which is parallel to the first straight line 211 and a second straight line 212. It has a pair of second line pattern groups 215a and 215b, which are located on the upper side, face each other via the first intersection point 213, and are each composed of a plurality of line segment patterns parallel to the second straight line 212. Note that the pair of first line pattern groups 214a and 214b are point objects with respect to the first intersection point 213, and the pair of first line pattern groups 215a and 215b are point objects with respect to the first intersection point 213.
[0065]
Here, in each of the pair of first line pattern groups 214a and 214b and the pair of second line pattern groups 215a and 215b, the line width of the plurality of linear patterns is 0.2 μm, and the The pattern pitch is 0.4 μm, the width of the line pattern group is 10 μm, and the length of the line pattern group is 10 μm.
[0066]
Next, after forming a second film to be processed on the lower layer pattern, a resist pattern having a second overlay measurement mark 220 shown in FIG. 5A is formed on the second film to be processed. Form.
[0067]
The second overlay measurement mark 220 is located on the third straight line 221 among the third straight line 221 parallel to the first straight line 211 and the fourth straight line 222 parallel to the second straight line 212, and A pair of third line pattern groups 224a and 224b, each of which is composed of a plurality of polygonal line patterns that are opposed to each other via a second intersection point 223 between the third straight line 221 and the fourth straight line 222, and are respectively parallel to each other; It has a pair of fourth line pattern groups 225a and 225b which are located on the fourth straight line 222, face each other via the second intersection point 223, and are each composed of a plurality of polygonal line patterns parallel to each other. Note that the pair of third line pattern groups 224a and 224b are point objects with respect to the second intersection 223, and the pair of fourth line pattern groups 225a and 225b are point objects with respect to the second intersection 223.
[0068]
FIG. 5B shows an angle α of each broken line forming the pair of second line pattern groups 224a and 224b and the pair of second line pattern groups 225a and 225b with respect to the third straight line 221 or the fourth straight line 222. , Β. The angles α and β may be different or equal, but in the second embodiment, the angles α and β are equal.
[0069]
Here, in each of the pair of third line pattern groups 224a and 224b and the pair of fourth line pattern groups 225a and 225b, the line width of the plurality of polygonal line patterns is 0.2 μm, and The pitch is 0.4 μm, the width of the line pattern group is 10 μm, and the length of the line pattern group is 10 μm.
[0070]
Next, the amount of displacement of the second overlay measurement mark 220 with respect to the first overlay measurement mark 210 is measured. This step will be described later.
[0071]
Next, when the amount of displacement of the second overlay measurement mark 220 with respect to the first overlay measurement mark 210 is within an allowable range, etching is performed on the second processing target film using the resist pattern as a mask. Thus, an upper layer pattern made of the second film to be processed is formed.
[0072]
Here, a process of measuring the amount of displacement of the second overlay measurement mark 220 with respect to the first overlay measurement mark 210 will be described.
[0073]
The center of the first overlay measurement mark 210 (first intersection 213) is designed to coincide with the center of the second overlay measurement mark 220 (second intersection 223).
[0074]
FIG. 6 shows a state in which the second overlay measurement mark 220 and the first overlay measurement mark 210 are actually overlapped, and the state in which the two overlay marks are overlapped is referred to as an optical overlay measurement device. , A moiré pattern is observed. As described above, the first straight line 211 and the third straight line 213 are parallel to each other, and the pair of first line pattern groups 214a and 214b include a plurality of line segments parallel to the first straight line 211. In addition, since the pair of third line pattern groups 224a and 224b are formed of a plurality of polygonal lines parallel to each other, an overlapping area of the pair of first line pattern groups 214a and 214b and the pair of third line pattern groups 224a and 224b , Linear portions (moiré patterns) 232 and 234 whose brightness is higher than the surroundings appear in a direction perpendicular to the first straight line 211 (third straight line 221). Similarly, the second straight line 212 and the fourth straight line 222 are parallel to each other, and the pair of second line pattern groups 215a and 215b are formed by a plurality of line segments parallel to the first straight line 211. And the pair of fourth line pattern groups 225a and 225b are composed of a plurality of polygonal lines parallel to each other, so that the pair of second line pattern groups 215a and 215b overlap with the pair of fourth line pattern groups 225a and 225b. In the region, linear portions (moire patterns) 231 and 233 whose brightness is higher than the surroundings appear in a direction perpendicular to the second straight line 212 (fourth straight line 222). Since the linear portions (moire patterns) 231, 232, 233, and 234 having high brightness can be detected by using the conventional optical overlay measurement device, the linear portions (moire patterns) 231 to 234 having high brightness can be detected. Can be handled in the same manner as the edge portion of a conventional square overlay measurement mark.
[0075]
The linear portions (moiré patterns) 231 to 234 having high brightness move depending on the positional relationship between the first overlay measurement mark 210 and the second overlay measurement mark 220, but the pair of first line pattern groups While the pair of third line pattern groups 224a and 224b are formed of a broken line pattern, the pair of second line pattern groups 215a and 215b are formed of a straight line pattern. Since the pair of fourth line pattern groups 225a and 225b are composed of broken lines, the moving direction of the linear portion (moire pattern) 231 having high brightness and the linear portion having high brightness are formed. The moving directions of the (moiré pattern) 233 are equal to each other, and the moving direction of the linear portion (moiré pattern) 232 having high brightness. Brightness are equal to each other and the moving direction of the high linear portion (moire pattern) 234.
[0076]
Then, the angle between the first line pattern group 214a, 214b and the third line pattern group 224a, 224b and the angle between the second line pattern group 215a, 215b and the fourth line pattern group 225a, 225b are θ. Assuming that x is the amount of misalignment of the second overlay measurement mark 220 with respect to the first overlay measurement mark 210 and y is the amount of movement of the linear portions 131 to 134 having high brightness, y = x / The relationship of tan θ holds.
[0077]
For example, when the angle θ is 1 degree and the overlay displacement amount x is 0.01 μm, the moving amount y of the linear portion (moire pattern) having high brightness is 0.57 μm, which is approximately 57 μm of the overlay displacement amount x. Twice as large.
[0078]
As shown in FIG. 6B, the variation y is calculated based on the signals obtained from the inner edges 235 and 236 and the outer edges 232 and 234 and the inner edges 235 and 236 and the outer edges 232 and 234. Is calculated, that is, the shift amount y is calculated, and then the overlay shift amount x is calculated from the above relational expression.
[0079]
According to the second embodiment, the shift amount (movement amount) y of the center between the inner edges 235, 236 and the outer edges 232, 234 appears in an amplified form of the actual overlay shift amount x. In the case of using an optical overlay measurement device similar to the conventional one, the measurement accuracy is greatly improved as compared with the conventional overlay mark. Therefore, the accuracy of measuring the displacement is greatly improved despite the use of the same overlay measurement device as in the prior art.
[0080]
Further, the line widths and pitches of the plurality of linear patterns constituting the line pattern group of the first and second overlay measurement marks 210 and 220 are made to match the line width and pitch of the actual circuit pattern (upper layer pattern). And the influence of the aberration of the exposure device becomes equal between the overlay measurement mark and the actual circuit pattern, so that the actual overlay deviation amount is more accurately reflected as compared with the conventional rectangular overlay measurement mark. Can be done.
[0081]
In the second embodiment, the plurality of line segments constituting the line pattern group of the first overlay measurement mark 210 are straight lines, but instead, a large number of hole patterns may be straight lines. While a plurality of broken line patterns constituting a line pattern group of the second overlay measurement mark 220 are linear line patterns arranged at a pitch, the hole patterns are replaced with a large number of hole patterns. It may be a polygonal hole pattern that is arranged at a constant pitch in a polygonal fashion.
[0082]
For example, when the upper layer pattern is a layer in which a contact hole is formed, performing a mask alignment process using an overlay measurement mark including a large number of hole patterns can reduce the influence of aberration of the exposure apparatus. In addition, the overlay accuracy can be improved.
[0083]
Hereinafter, results of an experiment performed to evaluate the second embodiment will be described.
[0084]
The misalignment between the second overlay measurement mark 220 formed on the actual circuit pattern (upper layer pattern) and the first overlay measurement mark 210 formed on the lower layer pattern is determined at a plurality of locations by an electronic microscope (SEM). ), And the actual measurement result was compared with the measurement result by the measurement method according to the second embodiment and the measurement result by the measurement method according to the first conventional example. The deviation from the actual measurement result was about 10 nm, whereas the deviation from the second embodiment and the actual measurement result was about 4 nm.
[0085]
If the amount of deviation between the overlay measurement mark and the actual circuit pattern is large, a desired product yield cannot be obtained unless the management standard for the mask alignment process is stricter than the original value. However, if the management standard of the mask alignment process is too strict, the process yield in the mask alignment process is reduced.
[0086]
On the other hand, according to the second embodiment, the management standard of the mask alignment process can be extended to 6 nm. A trial calculation of the yield by applying this wide management standard to an actual manufacturing process showed that the process yield was improved by about 3%.
[0087]
When the process yield is set to be the same as the current one, the design rule of the semiconductor device can be reduced by 6 nm. This means that a reduction effect of about 6% can be expected in an actual device.
[0088]
【The invention's effect】
According to the first or second method for manufacturing a semiconductor device according to the present invention, the first and second moiré patterns can be observed using a conventional optical measuring instrument, and the measurement accuracy of the overlay displacement amount Is greatly improved.
[Brief description of the drawings]
FIG. 1 is a plan view of a first overlay measurement mark used in a method for manufacturing a semiconductor device according to a first embodiment.
FIG. 2 is a plan view of a second overlay measurement mark used in the method for manufacturing a semiconductor device according to the first embodiment.
FIG. 3A is a plan view showing a state in which a first overlay measurement mark and a second overlay measurement mark are overlaid in the method for manufacturing a semiconductor device according to the first embodiment; FIG. 3B is a diagram illustrating an overlay displacement amount in the method for manufacturing a semiconductor device according to the first embodiment.
FIG. 4 is a plan view of a first overlay measurement mark used in a method for manufacturing a semiconductor device according to a second embodiment.
FIG. 5A is a plan view of a second overlay measurement mark used in the method of manufacturing a semiconductor device according to the second embodiment, and FIG. 5B is a partially enlarged view of the second overlay measurement mark. It is.
FIG. 6A is a plan view showing a state in which a first overlay measurement mark and a second overlay measurement mark are overlaid in the method of manufacturing a semiconductor device according to the second embodiment; FIG. 6B is a diagram for explaining an overlay displacement amount in the method for manufacturing a semiconductor device according to the second embodiment.
FIG. 7 is a diagram illustrating the amount of misalignment in a conventional method for manufacturing a semiconductor device.
[Explanation of symbols]
110 First overlay measurement mark
111 1st straight line
112 Second straight line
113 1st intersection
114a, 114b A pair of first line pattern groups
115a, 115b A pair of second line pattern groups
120 Second overlay measurement mark
121 1st straight line
122 Second straight line
123 Second Intersection
124a, 124b A pair of first line pattern groups
125a, 125b A pair of second line pattern groups
131 Linear part with high brightness (Moire pattern)
132 Linear part with high brightness (Moire pattern)
133 Linear part with high brightness (moire pattern)
134 Linear part with high brightness (Moire pattern)
135 Inside Edge
136 Inner edge
210 First overlay measurement mark
211 1st straight line
212 second straight line
213 First Intersection
214a, 214b A pair of first line pattern groups
215a, 215b A pair of second line pattern groups
220 Second overlay measurement mark
221 First straight line
222 Second straight line
223 Second Intersection
224a, 224b A pair of first line pattern groups
225a, 225b A pair of second line pattern groups
231 Linear part with high brightness (moire pattern)
232 Linear part with high brightness (moire pattern)
233 Linear part with high brightness (moire pattern)
234 Linear part with high brightness (moire pattern)
235 Inside edge
236 Inner edge

Claims

Forming a lower layer pattern comprising a first film to be processed and having a first overlay measurement mark; and forming a second film to be processed on the lower layer pattern, and then forming the second film to be processed. Forming a resist pattern having a second overlay measurement mark thereon; measuring a displacement amount of the second overlay measurement mark with respect to the first overlay measurement mark; Etching the second film to be processed using the resist pattern as a mask when the shift amount is within an allowable range, thereby forming an upper layer pattern made of the second film to be processed. In the method for manufacturing a semiconductor device,
The first overlay measurement mark is located on the first straight line of the first straight line and the second straight line that are orthogonal to each other, and is a first straight line between the first straight line and the second straight line. And a pair of first line pattern groups each composed of a plurality of linear patterns each of which is parallel to the first straight line and the first line pattern group located on the second straight line and And a pair of second line pattern groups each composed of a plurality of linear patterns each of which is parallel to the second straight line, and
The second overlay measurement mark is formed of a third straight line inclined at a first predetermined angle with respect to the first straight line and a fourth straight line inclined at a second predetermined angle with respect to the second straight line. A plurality of linear shapes that are located on the third straight line, face each other via a second intersection point of the third straight line and the fourth straight line, and are each parallel to the third straight line. A pair of third line pattern groups each including a plurality of linear patterns that are located on the fourth straight line, face each other via the second intersection, and are each parallel to the fourth straight line. And a pair of fourth line pattern groups consisting of patterns.
The step of measuring the amount of displacement includes a pair of first moire patterns formed by the pair of first line pattern groups and the pair of third line pattern groups, and the pair of second lines. Based on a pair of second moiré patterns formed by the pattern group and the pair of fourth line pattern groups, the amount of misalignment of the second overlay measurement mark with respect to the first overlay measurement mark is calculated. A method for manufacturing a semiconductor device, comprising a step of calculating.

A plurality of linear patterns forming the pair of first line pattern groups, a plurality of linear patterns forming the pair of second line pattern groups, and a plurality of linear patterns forming the pair of third line pattern groups. 2. The method according to claim 1, wherein the linear patterns and the plurality of linear patterns constituting the pair of fourth line pattern groups are all arranged at the same pitch.

3. The method according to claim 2, wherein the same pitch is equal to a design rule of the upper layer pattern.

The pair of first line pattern groups are point-symmetric with respect to the first intersection, and the pair of second line pattern groups are point-symmetric with respect to the first intersection. 3. The line pattern group of No. 3 is point-symmetric with respect to the second intersection, and the pair of fourth line pattern groups is point-symmetric with respect to the second intersection. The manufacturing method of the semiconductor device described in the above.

A plurality of linear patterns forming the pair of first line pattern groups, a plurality of linear patterns forming the pair of second line pattern groups, and a plurality of linear patterns forming the pair of third line pattern groups. 2. The semiconductor according to claim 1, wherein each of the linear patterns and the plurality of linear patterns constituting the pair of fourth line pattern groups includes a large number of hole pattern groups arranged at an equal pitch. 3. Device manufacturing method.

Forming a lower layer pattern comprising a first film to be processed and having a first overlay measurement mark; and forming a second film to be processed on the lower layer pattern, and then forming the second film to be processed. Forming a resist pattern having a second overlay measurement mark thereon; measuring a displacement amount of the second overlay measurement mark with respect to the first overlay measurement mark; Etching the second film to be processed using the resist pattern as a mask when the shift amount is within an allowable range, thereby forming an upper layer pattern made of the second film to be processed. In the method for manufacturing a semiconductor device,
The first overlay measurement mark is located on the first straight line among the first straight line and the second straight line that are orthogonal to each other, and is a first line between the first straight line and the second straight line. A pair of first line pattern groups each consisting of a plurality of polygonal linear patterns each of which is opposed to each other via an intersection and which are parallel to each other, and which is located on the second straight line and has the first intersection And a pair of second line pattern groups each composed of a plurality of polygonal linear patterns parallel to each other.
The second overlay measurement mark is parallel to the first straight line or parallel to the third straight line inclined at a first predetermined angle and parallel to the second straight line or only at a second predetermined angle. A plurality of inclined fourth straight lines are located on the third straight line, face each other via a second intersection point of the third straight line and the fourth straight line, and are parallel to each other. A pair of third line pattern groups each composed of a polygonal linear pattern, and a plurality of polygonal linear lines that are located on the fourth straight line, face each other via the second intersection, and are each parallel to each other. And a pair of fourth line pattern groups consisting of a linear pattern of
The step of measuring the amount of displacement includes a pair of first moire patterns formed by the pair of first line pattern groups and the pair of third line pattern groups, and the pair of second lines. Based on a pair of second moiré patterns formed by the pattern group and the pair of fourth line pattern groups, the amount of misalignment of the second overlay measurement mark with respect to the first overlay measurement mark is calculated. A method for manufacturing a semiconductor device, comprising a step of calculating.

A plurality of polygonal linear patterns forming the pair of first line pattern groups; a plurality of polygonal linear patterns forming the pair of second line pattern groups; and the pair of third line patterns A plurality of polygonal linear patterns constituting a group and a plurality of polygonal linear patterns constituting said pair of fourth line pattern groups are all arranged at the same pitch. Item 7. A method for manufacturing a semiconductor device according to Item 6.

8. The method according to claim 7, wherein the same pitch is equal to a design rule of the upper layer pattern.

The pair of first line pattern groups are point-symmetric with respect to the first intersection, and the pair of second line pattern groups are point-symmetric with respect to the first intersection. The third line pattern group is point-symmetric with respect to the second intersection, and the pair of fourth line pattern groups is point-symmetric with respect to the second intersection. The manufacturing method of the semiconductor device described in the above.

A plurality of polygonal linear patterns forming the pair of first line pattern groups; a plurality of polygonal linear patterns forming the pair of second line pattern groups; and the pair of third line patterns The plurality of broken line-shaped linear patterns forming the group and the plurality of broken line-shaped linear patterns forming the pair of fourth line pattern groups are each composed of a large number of hole pattern groups arranged at equal intervals. 7. The method for manufacturing a semiconductor device according to claim 6, wherein: