KR20070098029A - Semiconductor integrated circuit device - Google Patents

Abstract

A semiconductor IC(Integrated Circuit) device is provided to shorten a time for confirming an alignment of a plurality of thin film layers by confirming simultaneously the alignment of the thin film layers. A plurality of thin film layers including a first thin film layer are formed on a semiconductor substrate. An overlay mark pattern includes a mark frame(110) having a grating shape formed on the first thin film layer and a plurality of overlay marks(120,130,140,150) formed on the thin film layers. The overlay marks are arranged in the inside of the grating of the mark frame. The thin film layers includes the first thin film layer and the second to the fourth thin film layers laminated on the first thin film layer. The first overlay mark and the mark frame are patterned on the first thin film layer. The second to the fourth overlay marks are patterned on the second to the fourth thin film layers, respectively. The first to the fourth overlay marks are aligned within different gratings of the mark frame.

Description

Semiconductor integrated circuit device

1 is a front view and a partially enlarged view of an overlay mark pattern of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line AA ′ and BB ′ of FIG. 1.

3 to 5 are diagrams for describing an overlay mark pattern of a semiconductor integrated circuit device according to an exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating coordinates for calculating misregistration of a semiconductor integrated circuit device according to an exemplary embodiment of the present inventive concept.

FIG. 7 is a diagram for describing a second and third embodiment of an overlay mark pattern of a semiconductor integrated circuit device according to an example embodiment. Referring to FIG.

8 is a front view and a partially enlarged view of an overlay mark pattern of the semiconductor integrated circuit device according to the second embodiment of the present invention.

9 is a front view and a partially enlarged view of an overlay mark pattern of the semiconductor integrated circuit device according to the third embodiment of the present invention.

10 is a front view and a partially enlarged view of an overlay mark pattern of the semiconductor integrated circuit device according to the fourth embodiment of the present invention.

11 is a front view and a partially enlarged view of an overlay mark pattern of a semiconductor integrated circuit device according to a fifth embodiment of the present invention.

12 is a front view and a partially enlarged view of an overlay mark pattern of the semiconductor integrated circuit device according to the sixth embodiment of the present invention.

13 is a front view and a partially enlarged view of an overlay mark pattern of the semiconductor integrated circuit device according to the seventh embodiment of the present invention.

14 is a front view and a partially enlarged view of an overlay mark pattern of the semiconductor integrated circuit device according to the eighth embodiment of the present invention.

15 is a front view and a partially enlarged view of an overlay mark pattern of the semiconductor integrated circuit device according to the ninth embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

50: semiconductor substrate 52: first thin film layer

54: second thin film layer 56: third thin film layer

58: fourth thin film layer

100, 101, 102, 103, 104, 105, 200, 202, 204: overlay mark pattern

110: mark frame

120, 123, 124, 125: first overlay mark

130, 133, 134, 135: second overlay mark

140, 143, 144, and 145: third overlay mark

150, 153, 154, and 155: fourth overlay mark

111, 112: protrusions

210, 212, and 214: first overlay mark group

220, 222, and 224: second overlay mark group

The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device using a newer overlay mark pattern.

In a manufacturing process of a semiconductor integrated circuit device, an exposure process is performed to form a fine pattern on a semiconductor substrate. Such an exposure process generally includes applying a photoresist on a semiconductor substrate, baking a photoresist-coated semiconductor substrate, and partially transmitting light after matching a pattern formed on a mask with a pattern on the surface of the semiconductor substrate. Exposing the photoresist of the corresponding area, spraying the developer after the exposure process, and removing the light-transmitted portion or the non-light-transmitted portion by chemical action after forming the pattern on the semiconductor substrate. This is done by measuring alignment and inspecting for defects.

At this time, in the overlay process, which is a process of measuring alignment of the patterns on the semiconductor substrate and inspecting defects, is the lower thin film layer pattern formed on the semiconductor substrate and the upper thin film layer pattern formed on the lower film pattern aligned correctly? Check it.

In order to measure the alignment state of the pattern on the semiconductor substrate, the overlay mark pattern is formed on the upper thin film layer and the lower thin film layer, and the alignment state is measured by comparing the positions of the overlay mark patterns of the upper thin film layer and the lower thin film layer. In this case, the alignment state of the two thin film layers may be checked using an overlay mark pattern in the form of a box in box or a frame in frame. However, in the semiconductor manufacturing process, it is necessary to confirm not only two thin film layers but also alignment states of three or more thin film layers. In such a case, as many overlay mark patterns are needed as the number of thin film layers to be aligned, and more space is occupied on the wafer to form a plurality of overlay mark patterns. Therefore, the design of the overlay mark pattern that can utilize the space more efficiently is required.

In addition, while the design rule of the semiconductor device is several tens of nm, the overlay mark pattern has a size of several tens of μm. In this case, the asymmetry and the critical size of the critical dimension of the pattern of the memory cell and the overlay mark pattern are different due to the aberration of the exposure illumination system.

On the other hand, when performing a process such as CMP (Chemical Mechanical Polishing), the slurry may be caught between the overlay mark pattern may cause defects that cause particles, which may lower the process stability.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor integrated circuit device using a new overlay mark design.

The technical problem of the present invention is not limited to the technical problem mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor integrated circuit device according to an embodiment of the present invention for achieving the technical problem is a plurality of thin film layers and a mark frame formed on the first thin film layer including a first thin film layer formed on a semiconductor substrate and the grid and the mark It includes an overlay mark pattern is formed to be aligned within the grid of the frame and can measure the alignment of the plurality of thin film layers at a time including a plurality of overlay marks formed for each of the plurality of layers.

According to another aspect of the present invention, a semiconductor integrated circuit device includes a first overlay formed in a scribe area formed by crossing a first direction and a second direction, and formed at an angle of 45 degrees with the first direction. Eight overlay mark groups including eight mark groups, each overlay mark group includes an overlay mark pattern formed by rotating the first overlay mark group by 90 degrees.

According to another aspect of the present invention, a semiconductor integrated circuit device may be formed in a scribe area formed by crossing a first direction and a second direction, and may include a first overlay mark group formed in the first direction. And including eight overlay mark groups, each overlay mark group including an overlay mark pattern formed by rotating the first overlay mark group by 45 degrees.

Other specific details of the invention are included in the detailed description and drawings.

Advantages and features of the present invention, and methods of achieving the same will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Thus, well-known device structures and well-known techniques in some embodiments are not described in detail in order to avoid obscuring the present invention.

Like reference numerals refer to like elements throughout the specification. And / or include each and all combinations of one or more of the items mentioned.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, including and / or comprising the components, steps, operations and / or elements mentioned exclude the presence or addition of one or more other components, steps, operations and / or elements. I never do that.

Hereinafter, a semiconductor integrated circuit device according to an exemplary embodiment will be described with reference to FIGS. 1 to 5.

1 is a front view of an overlay mark pattern of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line AA ′ and BB ′ of FIG. 1. 3 to 5 are diagrams for explaining an overlay mark pattern of a semiconductor integrated circuit device according to an embodiment of the present invention.

1 to 5, a semiconductor integrated circuit device according to an embodiment of the present invention includes an overlay mark pattern 100 formed in a plurality of thin film layers, and the overlay mark pattern 100 includes a mark frame 110 and First to fourth overlay marks 120, 130, 140, and 150.

A plurality of thin film layers, for example, the first to fourth thin film layers 52, 54, 56, and 58, are formed on the semiconductor substrate 50, and the first to fourth thin film layers 52, 54, 56, and 58 are overlayed. The mark pattern 100 is formed.

The mark frame 110 is formed in the first thin film layer 52 and may be formed in a lattice shape. The mark frame 110 is formed in the first thin film layer 52 in order to quantify the degree of misalignment due to the process change, that is, the Mis Registration (MS). Therefore, the mark frame 110 is formed in the first thin film layer 52 together with the first overlay mark 120. Here, the size of the mark frame 110 may be, for example, about 20 ~ 40μm.

The first overlay mark 120 is formed in one of the gratings of the mark frame 110 and is formed in the first thin film layer 52. Thus, the first overlay mark 120 is patterned like the mark frame 110. 3 illustrates an overlay mark formed on the first thin film layer 52.

The second overlay mark 130 is formed on the second thin film layer 54. The second overlay mark 130 is formed to be aligned within one of the lattice of the mark frame 110 formed in the first thin film layer 52. At this time, the first overlay mark 120 is formed inside the grating other than the grating formed. 4 simultaneously shows overlay marks formed on the first and second thin film layers 54.

Likewise, referring to FIGS. 1 and 5, the third and fourth overlay marks 150 are formed on the third and fourth thin film layers 58 and are arranged to be aligned with one of the gratings of the mark frame 110. . 5 illustrates overlay marks formed on the first to third thin film layers 56, and FIG. 1 illustrates overlay mark patterns 100 formed on the first to fourth thin film layers 52, 54, 56, and 58. have.

 Therefore, when the overlay mark pattern 100 is projected and viewed from the front, as shown in FIG. 1, the first to fourth overlay marks 120, 130, 140, and 150 are disposed inside the grid of the mark frame 110. It becomes the shape which is entered one by one. Here, the first to fourth overlay marks 120, 130, 140, and 150 are formed on the first to fourth thin film layers 52, 54, 56, and 58, respectively.

In addition, a fine pattern according to the design rule of the cell pattern may be formed on the overlay mark pattern 100. For example, if the design rule is about 90 nm, a fine pattern of about 90 nm may be formed on the overlay mark pattern 100. In this case, the cell pattern and the overlay mark pattern 100 may be equally affected by the aberration of the exposure illumination system.

Hereinafter, referring to FIG. 6, the calculation of the alignment state of the thin film layer of the semiconductor integrated circuit device according to an exemplary embodiment will be described.

FIG. 6 is a diagram illustrating coordinates for calculating misregistration of a semiconductor integrated circuit device according to an exemplary embodiment of the present inventive concept.

For example, when X1 and X4 are X coordinates in the grid of the mark frame 110 and X2 and X3 are X coordinates of the second overlay mark 130, the calculation of misregistration of the X axis is as follows.

0.5 * {(X2 + X3)-{X1 + X4}}

When Y1 and Y4 are X coordinates inside the grid of the mark frame 110 and Y2 and Y3 are Y coordinates of the second overlay mark 130, the calculation of misregistration of the Y axis is as follows.

0.5 * {(Y2 + Y3)-{Y1 + Y4}}

In the same manner, when the misregistration between the third overlay mark 140 and the fourth overlay mark 150 and the mark frame 110 is calculated using the above equation, the first to fourth thin film layers 52, 54, and 56 are obtained. , 58) can be calculated.

The overlay mark pattern 100 of the semiconductor integrated circuit device according to the exemplary embodiment of the present invention may simultaneously check the alignment of the plurality of thin film layers 52, 54, 56, and 58. Therefore, it is possible to shorten the time required to calculate to confirm the alignment of the plurality of thin film layers 52, 54, 56, 58.

In addition, the overlay mark pattern 100 of the semiconductor integrated circuit device according to an exemplary embodiment of the present invention may use a conventional formula as it is to measure misregistration, and thus may be easily applied to the current process.

The size of the overlay mark pattern 100 of the semiconductor integrated circuit device according to an embodiment of the present invention is the size of the overlay mark pattern in the form of a box in box or a frame in frame. Similar to However, although the overlay mark pattern in the form of a box in a box or a frame in a frame could only confirm the alignment state of two thin film layers, the overlay mark pattern 100 of the semiconductor integrated circuit device according to an exemplary embodiment may include a plurality of thin film layers 52. , 54, 56, 58) can be confirmed. Therefore, as the space utilization increases, the degree of integration of the semiconductor integrated circuit device may increase.

On the other hand, by forming a fine pattern according to the design rule of the cell pattern on the overlay mark pattern 100 of the semiconductor integrated circuit device according to an embodiment of the present invention, the effect of the aberration of the exposure illumination system to the cell pattern and the overlay mark pattern ( 100) can be equally received. Therefore, the influence of the aberration of the exposure illumination system affects the cell pattern and the overlay mark pattern 100 differently, thereby preventing the alignment state of the cell pattern and the alignment state of the overlay mark pattern 100 from changing. Therefore, the alignment state of the thin film layer can be measured more precisely.

In addition, when a subsequent process such as etching after the photolithography process, CMP, etc., the fine patterns of the semiconductor integrated circuit device may have additional misregistration under the influence of the subsequent process. This is called wafer induced shift (WIS). According to the semiconductor integrated circuit device according to the exemplary embodiment of the present disclosure, the correction value may be calculated by directly measuring the WIS. Therefore, there is no need to use a mask separately for calculating the WIS, so that productivity can be increased.

Hereinafter, a semiconductor integrated circuit device according to second and third embodiments of the present invention will be described with reference to FIGS. 7 to 9. FIG. 7 is a diagram for describing a second and third embodiment of an overlay mark pattern of a semiconductor integrated circuit device according to an example embodiment. Referring to FIG. 8 is a front view of an overlay mark pattern of the semiconductor integrated circuit device according to the second embodiment of the present invention. 9 is a front view of an overlay mark pattern of the semiconductor integrated circuit device according to the third embodiment of the present invention.

Here, the same reference numerals are used for components substantially the same as in FIG. 1, and detailed description of the components will be omitted.

7 to 8, the semiconductor integrated circuit device according to the second embodiment of the present invention is different from the semiconductor integrated circuit device according to the embodiment of the overlay mark pattern 101 of the semiconductor integrated circuit device. The protrusion 111 is included in the corner region of the mark frame 110.

One or a plurality of protrusions 111 are included in the corner region of the mark frame 110 of the overlay mark pattern 101 of the semiconductor integrated circuit device according to the second embodiment of the present invention. That is, the overlay mark pattern 101 may have a unique feature by forming one or a plurality of protrusions 111 on the mark frame 110. When using a plurality of overlay mark patterns 101, when using the overlay mark pattern 101 having a unique feature as in the second embodiment of the present invention, it is easy to distinguish between the overlay mark patterns 101, the overlay mark pattern 101 may be positioned closer to each other. Therefore, the space utilization of the scribe area on the wafer on which the overlay mark pattern 101 is located is increased, and the degree of integration of the semiconductor integrated circuit device may be increased.

The protrusion 111 is formed at the corner region of the mark frame 110. The dotted box area of FIG. 7 is actually the effective area used to calculate the misregistration. Therefore, by forming the protrusion 111 in the corner region of the mark frame 110, it is possible to prevent the protrusion 111 from affecting the overlay measurement.

7 and 9, the semiconductor integrated circuit device according to the third embodiment of the present invention differs from the semiconductor integrated circuit device according to the second embodiment of the present invention because the protrusion 112 of the overlay mark pattern 102 is different. ) Is different. The protrusions 112 may be arranged in various locations to be distinguished from other overlay mark patterns, so that the overlay mark patterns 102 may have unique characteristics.

Hereinafter, a semiconductor integrated circuit device according to fourth to sixth embodiments of the present invention will be described with reference to FIGS. 10 to 12. 10 is a front view of an overlay mark pattern of the semiconductor integrated circuit device according to the fourth embodiment of the present invention. 11 is a front view of an overlay mark pattern of the semiconductor integrated circuit device according to the fifth embodiment of the present invention. 12 is a front view of an overlay mark pattern of the semiconductor integrated circuit device according to the sixth embodiment of the present invention.

Here, the same reference numerals are used for components substantially the same as in FIG. 1, and detailed description of the components will be omitted.

Referring to FIG. 10, the semiconductor integrated circuit device according to the fourth embodiment of the present invention differs from the semiconductor integrated circuit device according to an embodiment of the present invention in that the first to the first to first layers of the overlay mark pattern 103 of the semiconductor integrated circuit device are formed. 4 overlay marks 123, 133, 143, and 153 are formed in a group of divided sub-patterns.

If the first to fourth overlay marks 123, 133, 143, and 153 are formed of a group of divided subpatterns, in order to calculate misregistration, values of the X and Y coordinates of the respective subpatterns are necessary. do. As the overlay mark pattern 103 is formed, a pattern may not be formed accurately or may be partially crushed in a process. In this case, if the misregistration is calculated with only one value, the alignment state of the thin film layer may be incorrectly calculated. According to the fourth embodiment of the present invention, since the miss registration is calculated by combining the values of the respective sub-patterns, more accurate values can be measured.

In addition, since a unique characteristic may occur in the pattern according to the arrangement of the groups of the sub-patterns, the plurality of overlay mark patterns 103 may be adjacent to each other. Therefore, the space utilization of the scribe region on the wafer on which the overlay mark pattern 103 is located may be increased, and the integration degree of the semiconductor integrated circuit device may be increased.

Referring to FIG. 11, the semiconductor integrated circuit device according to the fifth embodiment of the present invention differs from the semiconductor integrated circuit device according to the fourth embodiment of the present invention by removing the mark frame from the overlay mark pattern 104. The arrangement of the first to fourth overlay marks 124, 134, 144, and 154 is changed. That is, by varying the arrangement of the first to fourth overlay marks 124, 134, 144, and 154, the plurality of overlay mark patterns 104 may be formed to have unique characteristics. Therefore, the space utilization of the scribe area on the wafer on which the overlay mark pattern 104 is located is increased, and the integration degree of the semiconductor integrated circuit device may be increased.

12, the semiconductor integrated circuit device according to the sixth embodiment of the present invention differs from the semiconductor integrated circuit device according to the fifth embodiment of the present invention in that the overlay mark pattern 105 includes the first to third overlays. The marks 125, 135, and 145 are arranged in this manner. That is, the sixth embodiment is the overlay mark pattern 105 that can confirm the alignment state of the three thin film layers.

Hereinafter, the semiconductor integrated circuit device according to the seventh to ninth embodiments of the present invention will be described with reference to FIGS. 13 to 15. 13 is a front view of the overlay mark pattern of the semiconductor integrated circuit device according to the seventh embodiment of the present invention. 14 is a front view of the overlay mark pattern of the semiconductor integrated circuit device according to the eighth embodiment of the present invention. 15 is a front view of an overlay mark pattern of the semiconductor integrated circuit device according to the ninth embodiment of the present invention.

Referring to FIG. 13, the semiconductor integrated circuit device according to the seventh exemplary embodiment includes an overlay mark pattern 200.

The overlay mark pattern 200 includes first and second overlay mark groups 210 and 220. The first overlay mark group 210 is an overlay mark group formed on the first thin film layer, and the second overlay mark group 220 is an overlay mark group formed on the second thin film layer.

In this case, the overlay mark pattern 200 is formed in a scribe area formed by crossing the first direction and the second direction, and includes four overlays including a first overlay mark group formed at an angle of 45 degrees with the first direction of the scribe area. And mark groups 210 and 220. In addition, each overlay mark group is formed by rotating the first overlay mark group by 90 degrees.

According to the overlay mark pattern 200 of the semiconductor integrated circuit device according to the seventh embodiment of the present invention, when a process such as CMP is performed, slurry or the like is sandwiched between the overlay mark patterns 200, thereby generating particles. Can be prevented. That is, since the overlay mark pattern 200 is formed to have a circular shape, it is possible to prevent particles from being generated in a process such as CMP having a circular shape in a clockwise or counterclockwise direction, thereby increasing process stability. have.

Referring to FIG. 14, the semiconductor integrated circuit device according to the eighth embodiment of the present invention differs from the semiconductor integrated circuit device according to the seventh embodiment of the present invention in that the first and second overlays of the overlay mark pattern 202 are provided. The design of the mark group 212 is different.

Referring to FIG. 15, the semiconductor integrated circuit device according to the ninth embodiment includes the overlay mark pattern 204.

In this case, the overlay mark pattern 204 is formed in a scribe area formed by crossing the first direction and the second direction, and includes eight overlay mark groups 214 including a first overlay mark group formed in the first direction of the scribe area. , 224). In addition, each overlay mark group is formed by rotating the first overlay mark group by 45 degrees.

Meanwhile, in the present invention, only the overlay mark patterns 200, 202, and 204 in which four overlay mark groups are separated by 90 degrees or eight overlay mark groups are separated by 45 degrees are described. However, the overlay marks may be formed to have a circular shape as a whole. Any overlay mark pattern that is present can be included.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the semiconductor integrated circuit device as described above has one or more of the following effects.

First, since the alignment of the plurality of thin film layers can be checked at the same time, it is possible to shorten the time taken to calculate the alignment of the plurality of thin film layers.

Second, as the space utilization increases, the degree of integration of the semiconductor integrated circuit device may increase.

Third, by forming a fine pattern according to the design rule of the cell pattern on the overlay mark pattern of the semiconductor integrated circuit device, it is possible to more accurately measure the alignment state of the thin film layer.

Fourth, since there is no need to use a mask to calculate the WIS, productivity can be increased.

Claims (7)

A plurality of thin film layers formed on the semiconductor substrate and including a first thin film layer; And An overlay that can measure the alignment state of the plurality of thin film layers at once, including a mark frame formed in the lattice shape and a plurality of overlay marks formed in the lattice of the mark frame and formed in the lattice of the mark frame. A semiconductor integrated circuit device comprising a mark pattern. The method of claim 1, The plurality of thin film layers includes second to fourth thin film layers on the first thin film layer, the overlay mark includes first to fourth overlay marks, and the first overlay mark is the mark frame on the first thin film layer. And the second to fourth overlay marks are patterned on the second to fourth thin film layers, respectively, and the first to fourth overlay marks are formed to be aligned inside different grids of the mark frame. . The method of claim 1, The mark frame includes one or a plurality of protrusions formed in the corner region of the mark frame. The method of claim 1, The overlay mark pattern is a semiconductor integrated circuit device formed with a fine pattern according to the design rule of the cell pattern. The method of claim 1, And the plurality of overlay marks are each formed of a group of sub patterns. And a plurality of overlay mark groups formed in the scribe area formed by crossing the first direction and the second direction, the eight overlay mark groups including a first overlay mark group formed at an angle of 45 degrees with the first direction, wherein each overlay mark group includes: And an overlay mark pattern formed by rotating the first overlay mark group by 90 degrees. A plurality of overlay mark groups formed in a scribe area formed by crossing a first direction and a second direction, the plurality of overlay mark groups including a first overlay mark group formed in the first direction, wherein each overlay mark group includes the first overlay A semiconductor integrated circuit device including an overlay mark pattern formed by rotating a mark group by a predetermined angle.

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