CN112582324A - Mark and manufacturing method thereof - Google Patents
Mark and manufacturing method thereof Download PDFInfo
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- CN112582324A CN112582324A CN201910925745.1A CN201910925745A CN112582324A CN 112582324 A CN112582324 A CN 112582324A CN 201910925745 A CN201910925745 A CN 201910925745A CN 112582324 A CN112582324 A CN 112582324A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
- H01L21/682—Mask-wafer alignment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
Abstract
The utility model relates to a mark figure and preparation method thereof, the mark includes the combined graph of being made by first version figure and second layout figure, utilizes first version figure with the whole size difference of second layout figure and first version figure with the great one of whole size covers the other party completely in the second layout figure, makes the whole boundary profile and the whole size of combined graph with first version figure with the less one of whole size is the same in the second layout figure. And when the first layout graph and the second layout graph have position deviation in the process, the integral size of the combined graph is ensured to be unchanged, and the accurate identification of the combined graph is further ensured.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a mark and a manufacturing method thereof.
Background
With the development of scientific technology, the structure of semiconductor devices becomes more and more complex, and the number of devices included in integrated circuits is gradually increasing. With the increasing integration level, the number of functional layers provided in the vertical direction of a semiconductor device is increasing to avoid further expansion of the device size. Therefore, the alignment precision between the photolithography processes of each layer becomes very important, and if the position deviation occurs between adjacent layers, the connection of the device will be seriously affected, which leads to the problems of short circuit of the connecting lines, increased failure rate and the like.
With the continuous shrinking of the process dimensions, the fabrication of a single layer pattern may require the use of multiple photomasks, for example, each photomask of three adjacent photolithography processes may be provided with an alignment pattern, the alignment patterns are formed on the wafer through the two photolithography processes, and the alignment pattern is aligned during the third photolithography process. However, if the first two layers of photomasks have a certain position deviation during exposure, the shape and size of the alignment mark change, which may lead to the alignment system of the lithography machine being unable to recognize the alignment mark and the third layer of photomasks being unable to be aligned effectively. Similarly, the measurement patterns have similar problems, and therefore, in order to accurately perform alignment and measurement between adjacent layers of a multi-layer mask, it is necessary to provide a new alignment mark and measurement mark and a method for manufacturing the same.
Disclosure of Invention
Accordingly, it is desirable to provide a new alignment mark and measurement mark and a method for manufacturing the same, which can solve the problems of alignment between layers of a multi-layer mask and insufficient measurement accuracy.
In order to realize the purpose of the invention, the invention adopts the following technical scheme:
a method of making a marking pattern, comprising:
providing a first layout graph;
providing a second layout graph, wherein the overall size of the second layout graph is not equal to that of the first layout graph;
and manufacturing a combined graph by utilizing the first layout graph and the second layout graph, wherein the larger overall size of the first layout graph and the second layout graph completely covers the other overall size, and the overall boundary outline and the overall size of the combined graph are the same as the smaller overall size of the first layout graph and the second layout graph.
In one embodiment, the combination pattern includes an alignment mark pattern or a metrology mark pattern.
In one embodiment, the overall outline of the first layout pattern and/or the second layout pattern is rectangular.
In one embodiment, the first version of the graphic comprises a plurality of first version of sub-graphics; the second layout pattern includes a plurality of second layout sub-patterns.
In one embodiment, the first layout pattern comprises a plurality of linear first layout sub-patterns which are arranged in parallel and equidistantly, and the first layout sub-patterns extend along a first direction; the second layout graph comprises a plurality of linear second layout sub-graphs which are arranged in parallel and at equal intervals, the second layout sub-graphs extend along a second direction, and the second direction is different from the first direction.
In one embodiment, the first pattern is fabricated onto a first reticle; manufacturing the second layout pattern on a second mask; respectively manufacturing the first layout graph and the second layout graph on a wafer by using the first mask and the second mask; and the overlapping region of the first layout graph and the second layout graph forms the combined graph.
In one embodiment, the minimum distance between the boundary lines of the first layout pattern and the second layout pattern is greater than 5 nm.
In one embodiment, the distance between the first layout graph and the second layout graph boundary line is larger than 5nm and smaller than 100nm, and dummy patterns are added on the periphery of the layout graph with the larger overall size.
A method of making a marking pattern, comprising: providing a plurality of layout graphs, wherein the plurality of layout graphs have at least one layout graph with the minimum overall size; and manufacturing a combined graph by using the plurality of layout graphs, wherein the overall boundary outline and the overall size of the combined graph are the same as those of the layout graph with the minimum overall size.
A marking pattern formed by the method for forming a composite pattern as described in any of the above embodiments.
The mark comprises a combined graph made of a first layout graph and a second layout graph, and the integral size difference of the first layout graph and the second layout graph and the integral size larger one of the first layout graph and the second layout graph completely cover the other one of the first layout graph and the second layout graph, so that the integral boundary outline and the integral size of the combined graph are the same as those of the first layout graph and the second layout graph which are smaller in the integral size. And when the first layout graph and the second layout graph have position deviation in the process, the integral size of the combined graph is ensured to be unchanged, and the accurate identification of the combined graph is further ensured.
Drawings
FIG. 1 is a schematic diagram illustrating the formation of a composite pattern in one embodiment;
FIG. 2 is a schematic diagram illustrating the formation of a composite pattern according to an embodiment;
FIG. 3 is a schematic diagram illustrating the variation of the combination pattern in one embodiment;
fig. 4(a) is an overlay schematic diagram when there is no deviation in overlay between the first layout pattern and the second layout pattern when the first layout pattern and the second layout pattern are fabricated on a wafer according to an embodiment;
fig. 4(b) is an overlay schematic diagram when overlay of the first layout pattern and the second layout pattern has a deviation when the first layout pattern and the second layout pattern are manufactured on a wafer according to an embodiment;
FIG. 4(c) is a graph of a metrology mark in the Y-direction in an OVL AIM mark in one embodiment.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Alternative embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
FIG. 1 is a diagram of a combined graph according to an embodiment of the invention.
In the present embodiment, as shown in fig. 1, a first layout graphic 110 is provided; providing a second layout graph 120, wherein the overall size of the second layout graph 120 is not equal to the overall size of the first layout graph 110. And manufacturing a combined graph 130 by using the first layout graph 110 and the second layout graph 120, wherein the larger overall size of the first layout graph 110 and the second layout graph 120 completely covers the other overall size, and the overall boundary outline and the overall size of the combined graph 130 are the same as the smaller overall size of the first layout graph and the second layout graph.
In one embodiment, the combination pattern includes an alignment mark pattern or a metrology mark pattern. The alignment mark pattern includes any one of SPM-AH32, SPM-AH53, SPM-AH74 and VSPMs. As shown in fig. 1, the combined pattern is an alignment mark. In other embodiments, the combined pattern is a pattern of metrology marks including any of OVL AIM, OVL box-in-box and OVL bar-in-bar.
In one embodiment, the overall outline of the first layout drawing 110 and/or the second layout drawing 120 is rectangular. As shown in fig. 1, the overall outline of the first layout pattern 110 is rectangular, and the overall outline of the second layout pattern 120 is rectangular. Specifically, the first layout pattern 110 includes six symmetrically distributed stripe structures and a cross 112 at the center of the symmetric point, and the stripe structures are aligned in the transverse direction. The overall outline is a rectangle surrounded by two outermost strip-shaped structures. The second layout graph 120 is a single rectangular graph, and the overall outline of the second layout graph 120 is rectangular.
In an embodiment, the first layout pattern 110 includes a plurality of first layout sub-patterns 111, and the first layout pattern 110 includes a plurality of linear first layout sub-patterns 111 arranged in parallel and at equal intervals, and the first layout sub-patterns 111 extend along a first direction. The second layout graph 120 comprises a plurality of second layout sub-graphs 121, the second layout graph 120 comprises a plurality of linear second layout sub-graphs 121 which are arranged in parallel and at equal intervals, the second layout sub-graphs 121 extend along a second direction, and the second direction is different from the first direction. As an example, the overall size of the second layout pattern 120 is larger than the overall size of the first layout pattern 110. Optionally, an included angle between the first direction and the second direction is 30 ° to 90 °, and by setting a proper included angle, the first layout pattern 110 and the second layout pattern 120 may be effectively overlapped in actual use, so as to form a combined pattern on the wafer for alignment or overlay error detection of a subsequent current layer.
In one embodiment, the first layout is fabricated on a first reticle; manufacturing the second layout pattern on a second mask; respectively manufacturing the first layout graph and the second layout graph on a wafer by using the first mask and the second mask; and the overlapping region of the first layout graph and the second layout graph forms the combined graph. By way of example, as shown in FIG. 1, a first layout 110 is fabricated on a first reticle and a second layout 120 is fabricated on a second reticle; exposing the wafer by using the first mask, and manufacturing a first pattern graph 110 on the wafer through processes of etching, cleaning and the like; exposing the wafer by using a second mask, and manufacturing a second layout graph 120 on the wafer through processes of etching, cleaning and the like; the overall size of the second layout graph 120 is greater than the overall size of the first layout graph 110, the second layout graph 120 completely covers the first layout graph 110, a combined graph 130 is manufactured by utilizing an overlapping area of the first layout graph 110 and the second layout graph 120, and the overall boundary contour and the overall size of the combined graph 130 are the same as those of the first layout graph 110. Specifically, the first layout pattern 110 is composed of 6 symmetrical stripe structures and a central cross 112, and in the formed combined pattern 130, the overall edge profile and the overall size of the combined pattern 130 are the same as those of the first layout pattern 130, and the combined pattern 130 is also composed of 6 symmetrical stripe structures and a central cross.
In an embodiment, the mask is a rectangle, one side of the rectangle is defined as the X direction, and the other side perpendicular to the one side is defined as the Y direction, and the distance between the boundary line of the first layout pattern and the boundary line of the second layout pattern in the X direction or the Y direction is greater than 5nm, such as 10nm, 20nm, 30nm, and the like. Specifically, as shown in fig. 2, the distance between the outermost boundary line of the first layout pattern and the outermost boundary line of the second layout pattern in the X direction is X, the distance in the y direction is y, and both X and y are greater than 5nm, so that when the first layout pattern and the second layout pattern are offset on the wafer, the finally formed combined pattern does not change. As shown in fig. 3, when the distance between the boundary lines of the first layout pattern and the second layout pattern is insufficient, and when the first layout pattern and the second layout pattern are offset on the wafer, the size of the finally formed combined pattern changes, which affects the subsequent processes. In this embodiment, the combined pattern is an alignment mark pattern, and when the size of the alignment mark pattern changes, an abnormal alignment process may be caused. Preferably, the distance between the boundary line of the first layout pattern and the boundary line of the second layout pattern is greater than 5nm and less than 100 nm. Meanwhile, dummy patterns (dummy patterns) are added to the periphery of the second layout graph, and in a chemical mechanical polishing process (CMP), due to the fact that material polishing rates are different, a concave shape can be formed, surface planarization and control of uniformity of a subsequent film layer are not facilitated, pattern density can be improved due to the addition of the dummy patterns, and therefore depression caused by pattern density difference during CMP is prevented, and a photoetching process window is increased.
In one embodiment, the combined pattern is a metrology mark pattern. FIG. 4(c) shows the pattern of the metrology marks in the Y-direction in OVL AIM. The measurement mark graph in the Y direction is formed by manufacturing a first layout graph and a second layout graph, the manufacturing method can refer to the manufacturing method of the alignment mark in the previous embodiment, the size of the first layout graph is larger than that of the second layout graph, and when the first layout graph and the second layout graph are overlapped and deviated during manufacturing on a wafer, a finally formed combined graph, namely the measurement mark graph cannot be changed, so that the measurement result is ensured. Fig. 4(a) is a measurement mark pattern finally formed when there is no deviation in the overlay of the first layout pattern and the second layout pattern when manufactured on a wafer; fig. 4(b) is a measurement mark pattern finally formed when the overlay of the first layout pattern and the second layout pattern has a deviation during the fabrication on the wafer. In one example, the distance between the boundary lines of the first layout pattern and the second layout pattern is greater than 5nm in both the Y direction and the X direction perpendicular to the Y direction, such as 10nm, 20nm, 30nm, and the like. When the overlay of the first layout graph and the second layout graph has deviation during the manufacturing on the wafer, the finally formed measurement mark graph cannot be changed. Preferably, first layout figure with the distance of second layout figure boundary line is greater than 5nm and is less than 100nm, simultaneously, the peripheral dummy pattern that adds of second layout figure, the addition of dummy pattern can increase photoetching process window and prevent the sunken that pattern density difference leads to when CMP.
In one embodiment, a plurality of layout patterns are provided, and at least one layout pattern with the minimum overall size is provided; and manufacturing a combined graph by using the plurality of layout graphs, wherein the overall boundary outline and the overall size of the combined graph are the same as those of the layout graph with the minimum overall size. The number of the layout graphs is more than or equal to 3. As an example, a first layout graph, a second layout graph, a third layout graph and a fourth layout graph are provided, the overall size of the second layout graph is the minimum, a combined graph is manufactured by using the first layout graph, the second layout graph, the third layout graph and the fourth layout graph, and the overall boundary outline and the overall size of the combined graph are the same as those of the second layout graph.
In one embodiment, the first reticle further comprises a first chip region pattern; the first chip region pattern comprises a plurality of linear first chip region sub-patterns, and the extending direction of the first chip region sub-patterns is the same as that of the first version sub-patterns; the second mask further comprises a second chip area graph; the second chip area graph comprises a plurality of linear second chip area sub-graphs, and the extending direction of the second chip area sub-graphs is the same as that of the second layout sub-graphs. And performing a double pattern (double pattern) process on the wafer by using the first mask and the second mask, and forming a combined pattern and a chip area pattern on the wafer. Specifically, the combined pattern includes an alignment mark pattern or a measurement mark pattern, and the alignment mark pattern or the measurement mark pattern and the chip region pattern are formed in the same process, so that the alignment mark pattern or the measurement mark can better reflect the process quality of the chip region pattern.
The application provides a marking pattern, comprising:
a marking pattern formed by the marking pattern forming method of any one of the above.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for making a marking pattern, comprising:
providing a first layout graph;
providing a second layout graph, wherein the overall size of the second layout graph is not equal to that of the first layout graph;
and manufacturing a combined graph by utilizing the first layout graph and the second layout graph, wherein the larger overall size of the first layout graph and the second layout graph completely covers the other overall size, and the overall boundary outline and the overall size of the combined graph are the same as the smaller overall size of the first layout graph and the second layout graph.
2. The method for producing a marking pattern as claimed in claim 1,
the combined pattern comprises an alignment mark pattern or a measurement mark pattern.
3. The method for making a mark pattern according to claim 2, wherein the overall outline of the first layout pattern and/or the second layout pattern is rectangular.
4. The method for producing a marking pattern as claimed in claim 1,
the first version of the graph comprises a plurality of first version of sub-graphs;
the second layout pattern includes a plurality of second layout sub-patterns.
5. The method for producing a marking pattern as claimed in claim 4,
the first layout graph comprises a plurality of linear first layout sub-graphs which are arranged in parallel at equal intervals, and the first layout sub-graphs extend along a first direction;
the second layout graph comprises a plurality of linear second layout sub-graphs which are arranged in parallel and at equal intervals, the second layout sub-graphs extend along a second direction, and the second direction is different from the first direction.
6. The method for making a marking pattern according to claim 1, comprising:
manufacturing the first version pattern on a first mask;
manufacturing the second layout pattern on a second mask;
respectively manufacturing the first layout graph and the second layout graph on a wafer by using the first mask and the second mask; and the overlapping region of the first layout graph and the second layout graph forms the combined graph.
7. The method for making a marking pattern according to claim 1, comprising:
and the minimum distance between the boundary lines of the first layout graph and the second layout graph is more than 5 nm.
8. The method for making a marking pattern according to claim 1, comprising:
the distance between the first layout graph and the second layout graph boundary line is greater than 5nm and less than 100nm, and simultaneously dummy patterns are added to the periphery of the layout graph with the large overall size.
9. A method for making a marking pattern, comprising:
providing a plurality of layout graphs, wherein the plurality of layout graphs have at least one layout graph with the minimum overall size;
and manufacturing a combined graph by using the plurality of layout graphs, wherein the overall boundary outline and the overall size of the combined graph are the same as those of the layout graph with the minimum overall size.
10. A graphic marking, comprising:
formed using the combinatorial patterning process of any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910925745.1A CN112582324B (en) | 2019-09-27 | 2019-09-27 | Mark and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910925745.1A CN112582324B (en) | 2019-09-27 | 2019-09-27 | Mark and manufacturing method thereof |
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| CN112582324A true CN112582324A (en) | 2021-03-30 |
| CN112582324B CN112582324B (en) | 2022-11-11 |
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| US20080032205A1 (en) * | 2006-08-04 | 2008-02-07 | Nanya Technology Corporation | Overlay mark |
| US20090246891A1 (en) * | 2008-03-25 | 2009-10-01 | Takashi Sato | Mark forming method and method for manufacturing semiconductor device |
| CN102866576A (en) * | 2012-08-27 | 2013-01-09 | 京东方科技集团股份有限公司 | Mask plate group and method for determining alignment precision range by using mask plate group |
| CN203084413U (en) * | 2013-01-07 | 2013-07-24 | 北京京东方光电科技有限公司 | Mask plate group and mark entity platform |
| US20190081005A1 (en) * | 2017-09-14 | 2019-03-14 | Toshiba Memory Corporation | Semiconductor device manufacturing method and semiconductor wafer |
| CN109870876A (en) * | 2017-12-05 | 2019-06-11 | 长鑫存储技术有限公司 | A kind of alignment pattern production method |
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2019
- 2019-09-27 CN CN201910925745.1A patent/CN112582324B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080032205A1 (en) * | 2006-08-04 | 2008-02-07 | Nanya Technology Corporation | Overlay mark |
| US20090246891A1 (en) * | 2008-03-25 | 2009-10-01 | Takashi Sato | Mark forming method and method for manufacturing semiconductor device |
| CN102866576A (en) * | 2012-08-27 | 2013-01-09 | 京东方科技集团股份有限公司 | Mask plate group and method for determining alignment precision range by using mask plate group |
| CN203084413U (en) * | 2013-01-07 | 2013-07-24 | 北京京东方光电科技有限公司 | Mask plate group and mark entity platform |
| US20190081005A1 (en) * | 2017-09-14 | 2019-03-14 | Toshiba Memory Corporation | Semiconductor device manufacturing method and semiconductor wafer |
| CN109870876A (en) * | 2017-12-05 | 2019-06-11 | 长鑫存储技术有限公司 | A kind of alignment pattern production method |
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