CN117577633B - Overlay mark and measurement method - Google Patents
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- 238000005259 measurement Methods 0.000 claims abstract description 51
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- 238000000034 method Methods 0.000 claims description 31
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- 238000013461 design Methods 0.000 description 9
- 230000002093 peripheral effect Effects 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 7
- 238000012512 characterization method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
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- 238000005516 engineering process Methods 0.000 description 1
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Abstract
The application relates to an overlay mark and a measurement method, wherein the overlay mark is positioned in a cutting channel and used for obtaining overlay precision, and the overlay mark comprises a front layer overlay mark and a current layer overlay mark. The front layer overlay mark comprises a first sub-mark and a second sub-mark which are mirror symmetrical along a first direction, and a third sub-mark and a fourth sub-mark which are mirror symmetrical along a second direction; the first current layer mark is surrounded by a first sub mark, a second sub mark, a third sub mark and a fourth sub mark in front projection on the upper surface of the layer where the previous layer overlay mark is positioned; the second current layer mark is positioned on one side of the first current layer mark, which is far away from the current layer pattern, along the first direction; the size of the second current layer mark is larger than that of the first current layer mark, and the distance between the first current layer mark and the second current layer mark is related to measurement accuracy, so that the shape symmetry of the overlay mark is improved, the measurement accuracy is further improved, and the yield of the semiconductor device is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to an overlay mark and a measurement method.
Background
With the increasing improvement of chip performance, the alignment Overlay accuracy of photolithography is one of the key parameters for measuring the photolithography process, and the Overlay accuracy refers to the offset between the upper layer pattern and the lower layer pattern in the wafer, and is realized by measuring the offset between the Overlay Mark (Overlay Mark) of the current layer and the front layer. If the overlay offset exceeds the design tolerance, problems such as leakage, disconnection, short circuit and the like occur in the semiconductor device, and the product yield is seriously affected.
However, in the related thick photoresist lithography process, since the density of the peripheral pattern of the overlay mark is uneven and the photoresist contains a large amount of solvent, the photoresist is inclined after exposure and baking, and thus the morphology of the overlay mark is asymmetric, resulting in measurement errors. Therefore, how to improve the morphology of the overlay mark to improve the measurement accuracy is a problem to be solved.
Disclosure of Invention
Based on this, it is necessary to provide an overlay mark and a measurement method for solving the problem of the overlay mark with asymmetric morphology, avoiding measurement errors, improving measurement accuracy, and further improving yield and overall performance of the semiconductor device.
To achieve the above and other related objects, an aspect of the present application provides an overlay mark, which is located in a scribe line and used for obtaining overlay accuracy, where the overlay mark includes a front layer overlay mark and a current layer overlay mark. The front layer overlay mark comprises a first sub-mark and a second sub-mark which are mirror symmetrical along a first direction, and a third sub-mark and a fourth sub-mark which are mirror symmetrical along a second direction; wherein the first direction is perpendicular to the second direction; the first current layer mark is surrounded by a first sub mark, a second sub mark, a third sub mark and a fourth sub mark in front projection on the upper surface of the layer where the previous layer overlay mark is positioned; the second current layer mark is positioned on one side of the first current layer mark, which is far away from the current layer pattern, along the first direction; the size of the second current layer mark is larger than that of the first current layer mark, and the distance between the first current layer mark and the second current layer mark is related to measurement accuracy.
In the above embodiment, the overlay mark includes a first current layer mark and a second current layer mark, wherein the second current layer mark is located at a side of the first current layer mark away from the current layer pattern along the first direction, and the size of the second current layer mark is larger than the size of the first current layer mark. Therefore, the gas generated in the photoresist after exposure and baking can be expanded and released, and the unexpected effect of the method is that the first current layer mark is positioned between the second current layer mark and the current layer pattern, and the size of the second current layer mark is larger than that of the first current layer mark, so that the density of the peripheral pattern of the first current layer mark is more uniform, the distribution of the gas released in the photoresist is balanced, the expansion force generated by the gas has uniform influence degree on the profile of the first current layer mark, and the shape symmetry of the first current layer mark is ensured. In the thick photoresist photoetching process in the related art, the pattern density around the overlay mark is not uniform, and the photoresist contains a large amount of solvent, so that the gas in the photoresist is expanded and released after exposure and baking, and the outline of the photoresist pattern is inclined to one side; after the inclination, the overlay mark is asymmetric in shape, and when the overlay mark with the asymmetric shape is used for overlay measurement, a measurement error is introduced, so that the measurement accuracy obtained by measurement is low, and the yield of the device is seriously affected. The overlay mark can solve the problem that the overlay mark is asymmetric in appearance when the pattern density around the overlay mark is uneven in the related art, and the appearance of the first overlay mark is improved by using the second overlay mark, so that the appearance symmetry of the first overlay mark is better, and the measurement accuracy is improved. In addition, because the distance between the first current layer mark and the second current layer mark is related to the measurement precision, the shape symmetry of the first current layer mark is better by adjusting the distance between the first current layer mark and the second current layer mark, and the yield of the semiconductor device is further ensured.
In some of these embodiments, the maximum length of the second current layer mark in the second direction is greater than the maximum length of the first current layer mark in the second direction.
In some embodiments, no pattern is provided in the layer where the overlay mark is located, in which the second overlay mark is located away from the first overlay mark in the first direction, outside the predetermined range of the scribe line.
In some embodiments, the second current layer mark is provided with a current layer environment graph within a preset range outside the cutting path at one side far away from the first current layer mark along the first direction; when the cutting path where the layer overlay mark is positioned comprises a symmetry axis extending along the second direction; the coverage area of the symmetrical pattern of the layer pattern relative to the symmetry axis is not overlapped with the environment pattern of the layer, or the overlapped area is smaller than a preset value.
In some embodiments, the first current layer mark and the second current layer mark have a predetermined distance along the first direction; the preset interval is an interval which enables the appearance symmetry of the first current layer mark after the baking process to be within a preset precision range.
In some of these embodiments, the measurement accuracy of the layer pattern is positively correlated with the target topography symmetry of the first layer mark; the target morphology symmetry is the morphology symmetry of the first current layer mark after the baking process.
In some embodiments, the relationship between the spacing of the layer pattern from the first layer mark and the predetermined spacing is a positive correlation.
In some of these embodiments, the second current layer mark is an auxiliary graphic mark.
In some of these embodiments, the first current layer indicia is rectangular in shape.
In some of these embodiments, the second current layer indicia is rectangular in shape.
Another aspect of the present application also provides a measurement method, which is implemented based on the overlay mark according to any one of the embodiments of the present application; the measuring method comprises the following steps: acquiring an initial offset of a central point of the first current layer mark compared with a central point of the previous layer overlay mark; and calculating a target offset according to a preset rule according to the initial offset, wherein the target offset is the actual offset of the layer where the first current layer mark is positioned relative to the layer where the previous layer overlay mark is positioned.
In the measurement method in the above embodiment, the measurement method is used for detecting the overlay accuracy of the current layer pattern and the previous layer pattern, and the unexpected effect of the present application is that, because the overlay mark provided by the present application is adopted, the peripheral pattern density of the first current layer mark is more uniform, so as to ensure the shape symmetry of the first current layer mark, improve the problem that the photoresist is inclined to one side due to the uneven peripheral pattern density of the overlay mark in the related art, further avoid the shape asymmetry of the overlay mark, and avoid introducing measurement errors, thereby ensuring that the shape symmetry of the first current layer mark is better, and aim at improving the measurement accuracy; the method and the device can further reduce measurement errors when the overlay accuracy measurement is carried out on the layer graph by using the measurement method provided by the application, so that the yield and the overall performance of the semiconductor device are improved.
Drawings
For a better description and illustration of embodiments and/or examples of those applications disclosed herein, reference may be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be construed as limiting the scope of any of the disclosed applications, the presently described embodiments and/or examples, and the presently understood best mode of carrying out these applications.
FIG. 1 is a schematic cross-sectional view of a related art wafer provided with overlay marks according to one embodiment of the present disclosure;
FIG. 2 is a schematic cross-sectional view of a related art wafer provided with overlay marks according to another embodiment of the present disclosure;
FIG. 3 is a vector diagram showing the alignment result in the related art according to an embodiment of the present application;
FIG. 4 is a vector diagram showing the alignment result in the related art according to another embodiment of the present application;
FIG. 5 is a schematic cross-sectional view of a semiconductor structure according to one embodiment of the present disclosure;
fig. 6 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present disclosure;
FIG. 7 is a schematic cross-sectional view of an overlay mark according to an embodiment of the present disclosure;
FIG. 8 is a schematic cross-sectional view of an overlay mark according to another embodiment of the present disclosure;
fig. 9 (a) is a schematic cross-sectional view showing a semiconductor structure according to another embodiment of the present application;
FIG. 9 (b) is a plot of a scattered point plot of overlay bias versus band for an embodiment of the present application;
FIG. 10 is a plot of scattered points of the overlay mark morphology symmetry characterization quantity versus overlay bias provided in an embodiment of the present application;
FIG. 11 (a) is a schematic diagram of a wafer with an overlay result according to an embodiment of the present application;
FIG. 11 (b) is a vector diagram showing the overlay results of FIG. 11 (a) provided in one embodiment of the present application;
FIG. 12 is a schematic view of a wafer with an overlay result according to another embodiment of the present application;
FIG. 12 (b) is a vector diagram showing the overlay results of FIG. 12 (a) provided in one embodiment of the present application;
fig. 13 (a) is a schematic view of a wafer with an overlay result according to another embodiment of the present application;
FIG. 13 (b) is a vector diagram showing the overlay results of FIG. 13 (a) provided in one embodiment of the present application;
FIG. 14 (a) is a schematic view of a wafer with an overlay result according to another embodiment of the present application;
FIG. 14 (b) is a vector diagram showing the overlay results of FIG. 14 (a) provided in one embodiment of the present application;
fig. 15 is a flow chart of a measurement method according to an embodiment of the present application.
Reference numerals illustrate:
1. a wafer; 10. a chip; 101. designing a graph; 11. a first mark point; 12. a second mark point; 13. a third mark point; 14. a fourth mark point; 15. a fifth mark point; 20. a substrate; 21. overlay mark; 22. a photomask; 231. a first thick photoresist layer; 232. a second thick photoresist layer; 30. patterning the layer; 31. cutting the channel; 32. the front layer is sleeved with a mark; 321. a first sub-label; 322. a second sub-label; 323. a third sub-label; 324. a fourth sub-label; 33. when the layers are overlapped, marking; 331. a first layer is marked; 332. and marking the second layer.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing, the regions illustrated in the figures being schematic in nature, and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
Please refer to fig. 1-15. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concepts of the application by way of illustration, and only the components related to the application are shown in the illustration, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
With the increasing performance of chips, the design and manufacturing requirements for more various photolithography patterns are further increased, and the overlay accuracy of photolithography is one of the key parameters for measuring the photolithography process, which represents the offset between two adjacent stacked patterns in a wafer. In order to ensure the overlay accuracy of the current layer pattern and the front layer pattern, the Alignment process with the front layer is realized by searching the Alignment Mark (Alignment Mark) of the front layer in the exposure process of the current layer, and the current layer pattern is formed by exposure and development. Overlay accuracy is achieved by measuring the offset of overlay marks of the current layer and the previous layer relative to each other. Thus, the alignment and overlay process of lithography requires the use of front layer alignment and overlay marks, respectively, whose quality will directly affect the alignment and measurement accuracy of the lithography. In a common semiconductor device manufacturing process, a resist pattern of alignment and overlay marks is formed first, and then a final alignment and overlay mark is formed by etching a wafer, and the final alignment and overlay mark is used for alignment and overlay measurement in a subsequent photolithography step.
It should be noted that, in the following embodiments of the present application, the first direction may be an ox direction in the drawing, and the second direction may be an oy direction in the drawing.
As an example, referring to fig. 1, a wafer 1 includes a plurality of chips 10 separated by scribe lines arranged in an array along a first direction and a second direction, where the chips 10 are provided with different circuit design patterns 101, and when the scribe lines of the layer are provided with overlay marks, since the scribe lines of the layer 101 are not provided at some positions in the chip 10, the density of the design patterns 101 on both sides of the scribe line positions where some overlay marks are located is asymmetric. In fig. 1, the first mark point 11 and the second mark point 12 are located at one side of the cutting path position with the design pattern 101, and the other side is not provided with the design pattern 101, so that the density of the design pattern 101 around the first mark point 11 and the second mark point 12 is asymmetric; the densities of the design patterns 101 on the opposite sides of the cutting track positions where the third mark point 13, the fourth mark point 14 and the fifth mark point 15 are located are symmetrical.
As an example, referring to fig. 1 to 4, fig. 2 shows measurement positions of the respective mark points when overlay deviation measurement is performed based on the first mark point 11, the second mark point 12, the third mark point 13, the fourth mark point 14, and the fifth mark point 15 in the wafer map. As can be seen from the vector diagrams of the overlay results shown in fig. 3 and 4, the arrows shown in fig. 3 and 4 represent the overlay offset vectors, and the overlay deviation of the first mark point 11 and the second mark point 12 is significantly larger than the overlay deviation of the third mark point 13, the fourth mark point 14 and the fifth mark point 15, so that it can be explained that the density asymmetry of the design pattern 101 around the overlay mark has a significant influence on the overlay measurement accuracy.
As an example, referring to fig. 5 and 6, as the number of layers of the circuit stack in the integrated circuit chip 10 increases, a photoresist with a larger thickness is required to be used in the lamination process in the photolithography process due to the process requirement, which increases the difficulty in detecting the overlay accuracy. In the thick photoresist lithography process in the related art, the substrate 20 includes the alignment marks arranged at intervals, the mask 22 is disposed above the alignment marks, the first thick photoresist layer 231 is disposed between adjacent alignment marks, the first thick photoresist layer 231 is exposed and baked by the ultraviolet light based on the mask 22, the gas is expanded and released after exposure and baking, and the photoresist contains a large amount of solvent due to uneven density of the surrounding pattern of the alignment marks, so that the profile of the first thick photoresist layer 231 is inclined to one side, and the inclined second thick photoresist layer 232 is formed. The oblique expansion force of the second thick photoresist layer 232 can cause the morphology of the overlay mark to change, so as to form an asymmetric morphology, and the measured position is different from the actual position when the overlay mark is used for overlay measurement, so that the measurement error shown in fig. 3 or fig. 4 can be introduced, the accuracy of the measurement data is affected, the measured measurement accuracy is poor, and the yield of the device is finally affected. Therefore, how to improve the morphology of the overlay mark to improve the measurement accuracy is a problem to be solved.
Based on the problems in the background art, the overlay mark and the measurement method are provided to solve the problem of asymmetry of the overlay mark morphology, avoid measurement errors, improve measurement accuracy, and further improve the yield and the overall performance of the semiconductor device.
As an example, referring to fig. 7, an aspect of the present application provides an overlay mark, which is located in a scribe line 31 for obtaining overlay accuracy, and the overlay mark includes a front layer overlay mark 32 and a current layer overlay mark 33. The front overlay mark 32 includes a first sub-mark 321 and a second sub-mark 322 that are mirror-symmetrical in a first direction, and a third sub-mark 323 and a fourth sub-mark 324 that are mirror-symmetrical in a second direction; wherein the first direction is perpendicular to the second direction; the overlay mark 33 includes a first overlay mark 331 and a second overlay mark 332, and the front projection of the first overlay mark 331 on the upper surface of the layer where the overlay mark 32 is located is surrounded by a first sub-mark 321, a second sub-mark 322, a third sub-mark 323 and a fourth sub-mark 324; the second current layer mark 332 is located at a side of the first current layer mark 331 away from the current layer pattern 30 along the first direction; the size of the second current layer mark 332 is larger than the size of the first current layer mark 331, and the distance between the first current layer mark 331 and the second current layer mark 332 is related to the measurement accuracy.
In the above embodiment, the overlay mark 33 includes a first overlay mark 331 and a second overlay mark 332, wherein the second overlay mark 332 is located on a side of the first overlay mark 331 away from the overlay pattern 30 along the first direction, and the size of the second overlay mark 332 is larger than the size of the first overlay mark 331. Therefore, the gases generated in the photoresist after exposure and baking will be expanded and released, and the unexpected effect of the present application is that, since the first current layer mark 331 is located between the second current layer mark 332 and the current layer pattern 30, and the size of the second current layer mark 332 is larger than that of the first current layer mark 331, the density of the peripheral pattern of the first current layer mark 331 can be more uniform, the distribution of the gases released in the photoresist is balanced, the expansion force generated by the gases has uniform influence on the profile of the first current layer mark 331, thereby ensuring the shape symmetry of the first current layer mark 331. In the thick photoresist photoetching process in the related art, the pattern density around the overlay mark is not uniform, and the photoresist contains a large amount of solvent, so that the gas in the photoresist is expanded and released after exposure and baking, and the outline of the photoresist pattern is inclined to one side; after the inclination, the overlay mark is asymmetric in shape, and when the overlay mark with the asymmetric shape is used for overlay measurement, a measurement error is introduced, so that the measurement accuracy obtained by measurement is low, and the yield of the device is seriously affected. The overlay mark provided by the application can solve the problem of the asymmetry of the overlay mark morphology generated when the pattern density around the overlay mark is uneven in the related art, and the morphology of the first overlay mark 331 is improved by using the second overlay mark 332, so that the morphology symmetry of the first overlay mark 331 is better, and the measurement accuracy is improved. In addition, since the distance between the first current layer mark 331 and the second current layer mark 332 is related to the measurement accuracy, the shape symmetry of the first current layer mark 331 can be better by adjusting the distance between the first current layer mark 331 and the second current layer mark 332, and the yield of the semiconductor device can be further ensured.
As an example, referring to fig. 8, the maximum length L2 of the second current layer mark 332 along the second direction is greater than the maximum length L1 of the first current layer mark 331 along the second direction. Since the first layer-present mark 331 has the second layer-present mark 332 and the layer-present pattern 30 on opposite sides thereof along the first direction, and the maximum length of the layer-present pattern 30 along the second direction is greater than the maximum length L1 of the first layer-present mark 331 along the second direction, the maximum length L2 of the second layer-present mark 332 along the second direction is set to be greater than the maximum length L1 of the first layer-present mark 331 along the second direction, so that the pattern densities on opposite sides of the first layer-present mark 331 along the first direction are uniformly symmetrical, so as to improve the shape symmetry of the first layer-present mark 331, and further improve the measurement accuracy.
As an example, referring to fig. 8, in the layer where the overlay mark 33 is located, the second overlay mark 332 is far from the scribe line 31 on the side of the first overlay mark 331 along the first direction (for example, ox direction), and no pattern is provided in a predetermined range. For another example, the second overlay mark 332 is provided with an overlay environment pattern (not shown) within a predetermined range outside the scribe line 31 on the side far from the first overlay mark 331 along the first direction, the scribe line where the overlay mark 33 is located includes a symmetry axis extending along the second direction (for example, the oy direction), and when the coverage area of the symmetry pattern of the overlay mark 30 with respect to the symmetry axis does not overlap with the overlay environment pattern, or the overlapping area is smaller than the predetermined value, a symmetrical optical environment cannot be formed around the front overlay mark 32. When the patterns on the opposite sides of the position of the scribe line 31 where the first layer mark 331 is located are symmetrically arranged, the second layer mark 332 need not be arranged; when the pattern arrangement states of the two opposite sides of the position of the scribe line 31 where the first current layer mark 331 is located are asymmetric, the second current layer mark 332 may be disposed in the scribe line 31 where the first current layer mark 331 is close to the side where no pattern is disposed, so as to improve the pattern density of the two sides of the first current layer mark 331. According to the method, the asymmetric second current layer marks 332 are added in the cutting channel 31 in a targeted manner based on the asymmetric condition of the patterns on the two sides of the first current layer marks 331, so that the pattern density can be symmetrical and uniform, the shape of the overlay marks is more symmetrical, and the shape symmetry of the first current layer marks 331 is improved.
As an example, with continued reference to fig. 8, the first layer mark 331 and the second layer mark 332 have a predetermined distance d along the first direction; the preset distance d is a distance that enables the shape symmetry of the first current layer mark 331 after the baking process to be within a preset precision range. Specifically, the preset precision range may be 95% -100%. By way of example, the preset precision may be 95%, 96%, 98%, 99% or 100%, etc.
As an example, with continued reference to fig. 8, when the relationship between the distance between the layer pattern 30 and the first current layer mark 331 and the preset distance d is positive, that is, when the distance between the layer pattern 30 and the first current layer mark 331 increases, the preset distance d also increases correspondingly; similarly, when the distance between the layer pattern 30 and the first layer mark 331 is reduced, the preset distance d is also reduced correspondingly, so as to ensure that the morphology of the first layer mark 331 is not damaged after the exposure and baking process.
As an example, with continued reference to fig. 8, the second current layer mark 332 is an auxiliary graphic mark, and since the second current layer mark 332 is to improve the shape symmetry of the first current layer mark 331, the second current layer mark 332 is an auxiliary graphic mark in the current layer that assists the first current layer mark 331 in performing overlay measurement.
As an example, with continued reference to fig. 8, the first current layer mark 331 is rectangular in shape. In other embodiments, the first current layer mark 331 may have other shapes.
As an example, with continued reference to fig. 8, the second current layer mark 332 is rectangular in shape. In other embodiments, the second current layer mark 332 may have other shapes, but it is necessary to ensure that the shape type of the second current layer mark 332 is consistent with the shape type of the current layer pattern 30, so that the pattern density of the two opposite sides of the first current layer mark 331 along the first direction is more uniform.
As an example, referring to fig. 9 (a) and (b), in the related art, the substrate 20 is provided with overlay marks arranged at intervals, and the topography of the overlay marks is asymmetric due to the influence of gas expansion imbalance in the photoresist after exposure and baking processes. Illustratively, the angle α above one side of the overlay mark cross-section is 90 ° and the angle β above the other side is greater than 90 °. As can be seen from the graph of the relationship between overlay deviation measurement and the wavelength band of the graph (b) in fig. 9, the overlay deviation when the topography of the overlay mark is asymmetric is significantly larger than the overlay deviation when the topography of the overlay mark is symmetric, and the higher the topography asymmetry is, the larger the overlay deviation is. Illustratively, the overlay bias at β=106° is greater than the overlay bias at β=98°, both of which are greater than the overlay bias at β=90°.
As an example, please continue to refer to fig. 8 and 9, when the relationship between the measurement accuracy of the layer pattern 30 and the shape symmetry of the first layer-present mark 331 after the baking process is positive, that is, the better the shape symmetry of the first layer-present mark 331 after the baking process, the better the measurement accuracy of the layer pattern 30; likewise, the poorer the topography symmetry of the first overlay mark 331 after the bake process, the poorer the measurement accuracy of the overlay pattern 30.
As an example, referring to fig. 10, the relationship between the absolute value of the feature symmetry characterization quantity (Qmerit) and the absolute value of the overlay bias after the baking process is positive correlation for the first current layer mark 331. The feature symmetry characterization quantity of the overlay mark represents the feature symmetry of the overlay mark, and can be obtained through measurement, wherein the expected value of the feature symmetry characterization quantity of the overlay mark is 0, which represents that the feature symmetry is 100%.
For example, please continue to refer to fig. 8, the preset spacing d ranges from 8 μm to 10 μm. Illustratively, the preset spacing d may be 8 μm, 8.5 μm, 9 μm, 9.5 μm, 10 μm, or the like.
As an example, referring to fig. 8, 11-14, the arrow shown in fig. 11 (b) represents an overlay shift vector, the arrow shown in fig. 12 (b) represents an overlay shift vector, the arrow shown in fig. 13 (b) represents an overlay shift vector, the arrow shown in fig. 14 (b) represents an overlay shift vector, and fig. 11-14 are wafer diagrams and vector diagrams of the overlay results when the preset pitches provided in the present application are different, wherein the comparison group is the overlay result without the second current layer mark 332. It can be seen that, among the four different overlay results, the overlay deviation of each overlay mark in the control group is the largest, and the overlay deviation of each overlay mark in the first-time layer mark 331 and the second-time layer mark 332 with a distance d2=9μm along the first direction is the smallest. The overlay deviation of each overlay mark in the comparison group is greater than the overlay deviation of each overlay mark in the first time layer mark 331 and the second time layer mark 332 with a distance d1=12μm in the first direction, and the overlay deviation of each overlay mark in the first time layer mark 331 and the second time layer mark 332 with a distance d1=12μm in the first direction is greater than the overlay deviation of each overlay mark in the first time layer mark 331 and the second time layer mark 332 with a distance d3=6μm in the first direction. It can be seen that when the pitch between the first time layer mark 331 and the second time layer mark 332 along the first direction is at the preset pitch d, the measurement accuracy is better, and the yield of the semiconductor device is higher.
As an example, referring to fig. 15, another aspect of the present application further provides a measurement method, which is implemented based on the overlay mark according to any one of the embodiments of the present application; the measuring method comprises the following steps:
step S2: acquiring an initial offset of a central point of the first current layer mark compared with a central point of the previous layer overlay mark;
step S4: and calculating a target offset according to a preset rule according to the initial offset, wherein the target offset is the actual offset of the layer where the first current layer mark is positioned relative to the layer where the previous layer overlay mark is positioned.
In the measurement method in the above embodiment, the measurement method is used for detecting the overlay accuracy of the current layer pattern and the previous layer pattern, and because the overlay mark provided by the application is adopted, the unexpected effect of the application is that the peripheral pattern density of the first current layer mark is more uniform, so as to ensure the shape symmetry of the first current layer mark, improve the problem that the photoresist is inclined to one side due to the uneven peripheral pattern density of the overlay mark in the related art, further avoid the shape asymmetry of the overlay mark, and avoid introducing measurement errors, thereby ensuring that the shape symmetry of the first current layer mark is better, and aim at improving the measurement accuracy. The method and the device can further reduce the measurement error of the overlay accuracy when the overlay accuracy is measured on the layer graph by using the measurement method provided by the application, so that the yield and the overall performance of the semiconductor device are improved.
As an example, with continued reference to step S2 in fig. 15, in step S2, the morphology symmetry of the first overlay mark is improved, so that when the initial offset of the center point of the first overlay mark is obtained compared to the center point of the previous overlay mark, the obtained initial offset data has smaller error, or even no error. Therefore, the measurement accuracy based on the overlay mark can be improved.
As an example, please continue to refer to step S4 in fig. 15, in step S4, after the actual offset is obtained, the overlay deviation of the current layer pattern relative to the previous layer pattern is obtained.
Note that the above embodiments are for illustrative purposes only and are not meant to limit the present application.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. An overlay mark, located in a scribe line, for obtaining overlay accuracy, the overlay mark comprising:
the front layer overlay mark comprises a first sub-mark and a second sub-mark which are mirror symmetrical along a first direction, and a third sub-mark and a fourth sub-mark which are mirror symmetrical along a second direction; wherein the first direction is perpendicular to the second direction;
the front projection of the first current layer mark on the upper surface of the layer where the front layer overlay mark is located is surrounded by the first sub-mark, the second sub-mark, the third sub-mark and the fourth sub-mark; the second current layer mark is positioned on one side of the first current layer mark far away from the current layer graph along the first direction;
the size of the second current layer mark is larger than that of the first current layer mark, and the distance between the first current layer mark and the second current layer mark is related to measurement accuracy.
2. The overlay mark of claim 1, wherein a maximum length of the second overlay mark in the second direction is greater than a maximum length of the first overlay mark in the second direction.
3. The overlay mark of claim 2, wherein in the layer where the overlay mark is located, the second overlay mark is not provided with a pattern within a predetermined range outside the scribe line on a side of the second overlay mark away from the first overlay mark in the first direction.
4. The overlay mark of claim 2, wherein the second overlay mark is provided with an overlay environment graphic within a predetermined range outside the scribe line on a side of the second overlay mark that is away from the first overlay mark in the first direction;
the cutting path where the overlay mark of the current layer is positioned comprises a symmetry axis extending along the second direction;
and the coverage area of the symmetrical graph of the current layer graph relative to the symmetrical axis is not overlapped with the current layer environment graph, or the overlapped area is smaller than a preset value.
5. The overlay mark of any one of claims 1-4, wherein the first overlay mark and the second overlay mark have a predetermined spacing along the first direction; the preset interval is an interval which enables the shape symmetry of the first current layer mark after the baking process to be within a preset precision range.
6. The overlay mark of claim 5, wherein the measurement accuracy of the overlay pattern is positively correlated with the target topography symmetry of the first overlay mark;
the target morphology symmetry is morphology symmetry of the first current layer mark after the baking process.
7. The overlay mark of claim 5, wherein a relationship between a spacing of the overlay pattern and the first overlay mark and the predetermined spacing is a positive correlation.
8. The overlay mark of any one of claims 1-4, wherein the second overlay mark is an auxiliary graphic mark.
9. The overlay mark as set forth in any one of claims 1 to 4,
the shape of the first current layer mark is rectangular; and/or
The second current layer mark is rectangular in shape.
10. A measurement method, characterized in that it is realized based on the overlay mark according to any one of claims 1-9; the measuring method comprises the following steps:
acquiring an initial offset of the center point of the first current layer mark compared with the center point of the front layer overlay mark;
and calculating a target offset according to the initial offset and a preset rule, wherein the target offset is the actual offset of the layer where the first current layer mark is positioned relative to the layer where the previous layer overlay mark is positioned.
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