CN116560193A - Mask and chip forming method - Google Patents

Mask and chip forming method Download PDF

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Publication number
CN116560193A
CN116560193A CN202210109341.7A CN202210109341A CN116560193A CN 116560193 A CN116560193 A CN 116560193A CN 202210109341 A CN202210109341 A CN 202210109341A CN 116560193 A CN116560193 A CN 116560193A
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CN
China
Prior art keywords
exposure
area
mark
splicing
areas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210109341.7A
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Chinese (zh)
Inventor
康吉祥
王雪梅
韦亚婷
陈福刚
陈文甫
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN202210109341.7A priority Critical patent/CN116560193A/en
Publication of CN116560193A publication Critical patent/CN116560193A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70475—Stitching, i.e. connecting image fields to produce a device field, the field occupied by a device such as a memory chip, processor chip, CCD, flat panel display
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70691—Handling of masks or workpieces
    • G03F7/70775—Position control, e.g. interferometers or encoders for determining the stage position
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7088—Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

A mask and a method for forming a chip, wherein the mask comprises the following steps: a plurality of central exposure areas, the central exposure areas including a plurality of central circuit patterns; the device comprises a plurality of peripheral exposure areas, a plurality of first splicing exposure areas and a plurality of second splicing exposure areas, wherein each peripheral exposure area comprises a cutting channel exposure area and a first splicing exposure area surrounding the cutting channel exposure area, and the first splicing exposure area comprises a first splicing exposure side area and a second splicing exposure side area which are respectively positioned at two opposite sides of the cutting channel exposure area; the first mark is arranged in the first spliced exposure side area, the second mark is arranged in the second spliced exposure side area, the second mark and the first mark correspond to each other, the size of the formed chip is not limited by the size of a mask, the manufacturing capacity of a large-size chip is improved, and complete and regularly distributed alignment marks can be formed in a cutting channel area of the formed chip and used for detecting alignment precision of devices and improving alignment level.

Description

Mask and chip forming method
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a mask and a chip.
Background
As the current chip application needs are diversified, the application fields of large-area chips, such as large-area array CMOS image sensors, are becoming wider, and the demands of large-area array CMOS image sensors are increasing in high-end applications such as medical and industrial X-ray flat panel detectors, scientific researches and the like.
When the chip size exceeds the maximum reticle size (i.e., the single maximum exposure size of the lithography machine, typically less than 3cm x 3 cm), it cannot be obtained by conventional single-step lithography processes, which require multiple split-area lithography stitching processes. The splicing process refers to partitioning the related graph in the manufacturing process of the chip, performing multiple step exposure by using a plurality of smaller-size masks, and finally splicing to form a larger-size chip.
However, the existing technology of forming large-sized chips using a stitching process needs to be further improved.
Disclosure of Invention
The invention solves the technical problem of providing a mask and a chip forming method to improve the performance of the formed chip.
In order to solve the technical problems, the technical scheme of the invention provides a mask plate, which comprises the following components: a plurality of central exposure areas, the central exposure areas including a plurality of central circuit patterns; the device comprises a plurality of peripheral exposure areas, a plurality of first splicing exposure areas and a plurality of second splicing exposure areas, wherein each peripheral exposure area comprises a cutting channel exposure area and a first splicing exposure area surrounding the cutting channel exposure area, and the first splicing exposure area comprises a first splicing exposure side area and a second splicing exposure side area which are respectively positioned at two opposite sides of the cutting channel exposure area; the first mark is arranged in the first spliced exposure side area, the second mark is arranged in the second spliced exposure side area, and the second mark and the first mark correspond to each other.
Optionally, the method further comprises: and the shading belt is positioned between the adjacent two central exposure areas, the adjacent two peripheral exposure areas and the adjacent central exposure areas and the peripheral exposure areas.
Optionally, the material of the masking tape comprises chromium.
Optionally, the width of the light shielding tape ranges from 750 μm to 1500 μm.
Optionally, the peripheral exposure area further includes a peripheral circuit exposure area, the peripheral circuit exposure area is located at two sides of the dicing street exposure area and located between the dicing street exposure area and the first stitching exposure area, and the peripheral circuit exposure area includes a plurality of peripheral circuit patterns.
Optionally, each central exposure area further includes a second stitching exposure area located around the plurality of central circuit patterns, where the second stitching exposure area includes a third stitching exposure edge area and a fourth stitching exposure edge area that are opposite to each other; the third mark is arranged in the third spliced exposure side area, the fourth mark is arranged in the fourth spliced exposure side area, and the fourth mark and the third mark correspond to each other.
Correspondingly, the technical scheme of the invention also provides a chip forming method, which comprises the following steps: providing a wafer to be processed, wherein the wafer to be processed comprises a plurality of chip areas, each chip area comprises a plurality of core circuit setting areas which are repeatedly distributed and a plurality of outer circuit setting areas which are repeatedly distributed, each outer circuit setting area comprises a cutting channel area, and a first splicing area is arranged between every two adjacent cutting channel areas; providing a mask, the mask comprising: a plurality of central exposure areas, the central exposure areas including a plurality of central circuit patterns; the device comprises a plurality of peripheral exposure areas, a plurality of first splicing exposure areas and a plurality of second splicing exposure areas, wherein each peripheral exposure area comprises a cutting channel exposure area and a first splicing exposure area positioned around the cutting channel exposure area, and the first splicing exposure area comprises a first splicing exposure side area and a second splicing exposure side area which are respectively positioned on two opposite sides of the cutting channel exposure area; the first mark is arranged in the first spliced exposure side area, the second mark is arranged in the second spliced exposure side area, and the second mark and the first mark correspond to each other; and performing multiple exposure treatment on the wafer to be treated by adopting the mask, forming a central circuit pattern in the core circuit setting region, forming a peripheral circuit pattern in the outer circuit setting region, and forming a first alignment mark in the first splicing region.
Optionally, the forming method of the first alignment mark in the first splicing area includes: forming a first mark pattern in the first splicing area after the first exposure treatment; and after the second exposure treatment, forming a second mark pattern in the first splicing area, wherein the second mark pattern is overlapped with the first mark pattern.
Optionally, the method for forming the first alignment mark in the first splicing area includes: forming a first mark pattern in the first splicing area after the first exposure treatment; after the second exposure process, a second mark pattern is formed in the first stitching region, the second mark pattern being adjacent to the first mark pattern.
Optionally, the mask further includes: the peripheral circuit exposure area further comprises peripheral circuit exposure areas, the peripheral circuit exposure areas are located on two sides of the cutting channel exposure area and located between the cutting channel exposure areas and the first splicing exposure areas, and the peripheral circuit exposure areas comprise a plurality of peripheral circuit patterns.
Optionally, the mask further includes: each central exposure area further comprises a second spliced exposure area positioned around the plurality of central circuit patterns, and the second spliced exposure area comprises a third spliced exposure side area and a fourth spliced exposure side area which are opposite; the third mark is arranged in the third spliced exposure side area, the fourth mark is arranged in the fourth spliced exposure side area, and the fourth mark and the third mark correspond to each other.
Optionally, a second splicing area is provided between adjacent core circuit setting areas, and the method further comprises: and after the multiple exposure treatment, forming a second alignment mark in the second splicing region.
Optionally, the method for forming the second overlay alignment mark in the second splicing region includes: forming a third mark pattern in the second splicing area after the third exposure treatment; and after the fourth exposure treatment, forming a fourth mark pattern in the second splicing area, wherein the third mark pattern is overlapped with the fourth mark pattern.
Optionally, the method for forming the second overlay alignment mark in the second splicing region includes: forming a third mark pattern in the second splicing area after the third exposure treatment; after the fourth exposure process, a fourth mark pattern is formed in the second stitching region, the fourth mark pattern being adjacent to the third mark pattern.
Optionally, the width of the first splicing area ranges from 0.1 μm to 0.5 μm.
Optionally, the central circuit pattern is formed by the plurality of central exposure areas of the mask plate, and the peripheral circuit pattern is formed by the plurality of peripheral exposure areas of the mask plate.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the mask provided by the technical scheme of the invention, on one hand, the mask is divided into a plurality of central exposure areas and a plurality of peripheral exposure areas, one mask is used, different exposure areas are selected to expose the wafer respectively, one area of the target chip is formed, and finally, a large-size chip is formed, the size of the formed chip is not limited by the size of the mask, and the manufacturing capacity of the large-size chip is improved; on the other hand, the first splicing exposure area comprises a first splicing exposure side area and a second splicing exposure side area which are respectively positioned at two opposite sides of the cutting channel exposure area, a first mark is arranged in the first splicing exposure side area, a second mark is arranged in the second splicing exposure side area, the second mark and the first mark correspond to each other, after the mask plate is adopted for multiple exposure, complete and regularly distributed alignment marks can be formed in the cutting channel area of the formed chip and used for detecting alignment precision of devices and improving alignment level.
Furthermore, the arrangement of the shading belt can reduce the occurrence of the condition that the non-exposure area is exposed due to light diffraction generated at the edge of the baffle plate above the mask plate in the exposure process.
Further, each central exposure area further comprises a second spliced exposure area positioned around the plurality of central circuit patterns, and the second spliced exposure area comprises a third spliced exposure side area and a fourth spliced exposure side area which are opposite; the third mark is arranged in the third spliced exposure side area, the fourth mark is arranged in the fourth spliced exposure side area, and the fourth mark and the third mark correspond to each other. The third mark and the fourth mark may form a second overlay alignment mark of a core circuit arrangement region of the chip.
In the chip forming method provided by the technical scheme of the invention, one mask plate is used, different exposure areas are selected to expose the wafer respectively to form one area of the target chip, and finally, a large-size chip is formed, the size of the formed chip is not limited by the size of the mask plate, and the manufacturing capacity of the large-size chip is improved; in addition, after the mask is adopted for multiple exposure, first alignment marks which are completely and regularly distributed can be formed in the cutting channel region of the formed chip and used for detecting alignment precision of the device and improving alignment level.
Further, the method for forming the second alignment mark in the second splicing region comprises the following steps: forming a third mark pattern in the second splicing area after the third exposure treatment; after the fourth exposure treatment, a fourth mark pattern is formed in the second splicing region, the third mark pattern is overlapped with the fourth mark pattern, and the second splicing region adopts a twice exposure forming mode, so that connection of circuits in two adjacent core circuit setting regions is improved, and the occurrence of wire breakage caused by poor splicing is avoided.
Drawings
FIG. 1 is a flow chart of steps of a method for forming a chip according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a chip according to an embodiment of the invention;
fig. 3 to 7 are schematic structural views illustrating steps of a method for forming a chip according to an embodiment of the invention;
fig. 8 to 9 are schematic structural views illustrating steps of a method for forming a second alignment mark according to another embodiment of the present invention.
Detailed Description
Note that "surface", "upper", as used herein, describes a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
As described in the background art, the existing technology of forming large-sized chips by using a splicing process needs to be further improved.
According to the method for forming the mask neutralization chip, on one hand, the mask is divided into a plurality of central exposure areas and a plurality of peripheral exposure areas, one mask is used, different exposure areas are selected to expose the wafer respectively, one area of the target chip is formed, a large-size chip is finally formed, the size of the formed chip is not limited by the size of the mask, and the manufacturing capacity of the large-size chip is improved; on the other hand, the first splicing exposure area comprises a first splicing exposure side area and a second splicing exposure side area which are respectively positioned at two opposite sides of the cutting channel exposure area, a first mark is arranged in the first splicing exposure side area, a second mark is arranged in the second splicing exposure side area, the second mark and the first mark correspond to each other, after the mask plate is adopted for multiple exposure, complete and regularly distributed alignment marks can be formed in the cutting channel area of the formed chip and used for detecting alignment precision of devices and improving alignment level.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 is a flowchart illustrating steps of a method for forming a chip according to an embodiment of the present invention.
Referring to fig. 1, the method for forming the chip includes the following steps:
step S101, providing a wafer to be processed, wherein the wafer to be processed comprises a plurality of chip areas, each chip area comprises a plurality of core circuit setting areas which are repeatedly distributed and a plurality of outer circuit setting areas which are repeatedly distributed, and each outer circuit setting area comprises a cutting channel area and a first splicing area which is positioned around the cutting channel area;
step S102, providing a mask plate, wherein the mask plate comprises: a plurality of central exposure areas, each of the central exposure areas including a plurality of central circuit patterns; the device comprises a plurality of peripheral exposure areas, a plurality of first splicing exposure areas and a plurality of second splicing exposure areas, wherein each peripheral exposure area comprises a cutting channel exposure area and a first splicing exposure area surrounding the cutting channel exposure area, and the first splicing exposure area comprises a first splicing exposure side area and a second splicing exposure side area which are respectively positioned at two opposite sides of the cutting channel exposure area; the first mark is arranged in the first spliced exposure side area, the second mark is arranged in the second spliced exposure side area, and the second mark and the first mark correspond to each other;
and step S103, performing multiple exposure treatment on the wafer to be treated by adopting the mask, forming a central circuit pattern in the core circuit setting area, forming a peripheral circuit pattern in the outer circuit setting area, and forming a first alignment mark in the first splicing area.
The following detailed description will be given with reference to the accompanying drawings.
Fig. 2 is a schematic structural diagram of a chip according to an embodiment of the invention.
Referring to fig. 2, and continuing to refer to fig. 1, a wafer to be processed is provided, where the wafer to be processed includes a plurality of chip areas, each chip area includes a plurality of core circuit setting areas 301 that are repeatedly distributed, and a plurality of outer circuit setting areas 302 that are repeatedly distributed, each outer circuit setting area 302 includes a scribe line area 303, and a first splicing area 304 between adjacent scribe line areas 303.
The technical scheme of the invention can manufacture chips with the size larger than that of the mask plate, and can maximally achieve the wafer-level large-size chips.
Specifically, the chip area shown in this embodiment includes four core circuit setting areas 301 located in the middle of the chip area and twelve outer circuit setting areas 302 surrounding the core circuit setting areas 301, where the twelve outer circuit setting areas 302 may be divided into three repeating units located in a long side area I, a corner area II and a short side area III according to different position distributions. The division of each region of each chip region is performed according to the actual repeating unit category, the division method is not limited thereto, and in other embodiments, the division may be performed according to actual requirements.
In this embodiment, the width of the first splicing region 304 ranges from 0.1 μm to 0.5 μm.
In this embodiment, each of the external circuit setting areas 302 includes an external circuit 305, and the external circuit 305 is located at two sides of the dicing street area 303. Specifically, a third splicing section 307 is further provided between the peripheral circuit 305 and the core circuit setting section 301.
In this embodiment, the third splicing region 307 has a width in the range of 0.1 μm to 0.5 μm.
In this embodiment, a second splicing section 306 is provided between adjacent core circuit arrangement sections 301.
In this embodiment, the width of the second splicing area 306 is in the range of 0.1 μm to 0.5 μm.
It should be noted that only one chip area is shown in this embodiment, and the chip area is used to form the image sensor.
Fig. 3 to fig. 7 are schematic structural diagrams illustrating steps of a method for forming a chip according to an embodiment of the invention.
Referring to fig. 3 to 5, with continued reference to fig. 1, fig. 3 is a schematic diagram of a mask, fig. 4 is a partial schematic diagram at a dashed line 11 in fig. 3, and fig. 5 is a partial schematic diagram at a dashed line 22 in fig. 3, a mask is provided, the mask includes: a plurality of center exposure areas 200, the center exposure areas 200 including a plurality of center circuit patterns 201; the device comprises a plurality of peripheral exposure areas 202, wherein each peripheral exposure area 202 comprises a cutting-channel exposure area 203 and a first spliced exposure area 204 positioned around the cutting-channel exposure area 203, and the first spliced exposure area 204 comprises a first spliced exposure side area 205a and a second spliced exposure side area 205b which are respectively positioned on two opposite sides of the cutting-channel exposure area 203; the first splicing exposure side area 205a is provided with a first mark A, the second splicing exposure side area 205B is provided with a second mark B, and the second mark B and the first mark A correspond to each other.
The second mark B and the first mark a correspond to each other, which means that the second mark B and the first mark a may form a complete overlay alignment mark.
In this embodiment, the mask plate includes a central exposure area 200 and three peripheral exposure areas 202, wherein the three peripheral exposure areas 202 include a peripheral exposure area I ', a peripheral exposure area II' and a peripheral exposure area III ', the central exposure area 200 is used to form a core circuit arrangement area 301 of the chip area, and the peripheral exposure area I', the peripheral exposure area II 'and the peripheral exposure area III' are distributed to form an outer circuit arrangement area 302 of a long side area I, a corner area II and a short side area III of the chip area.
In this embodiment, the mask further includes: the peripheral exposure area 202 further includes a peripheral circuit exposure area 206, the peripheral circuit exposure area 206 is located at two sides of the dicing street exposure area 203 and between the dicing street exposure area 203 and the first stitching exposure area 204, and the peripheral circuit exposure area 206 includes a plurality of peripheral circuit patterns (not shown in the figure).
In this embodiment, the mask further includes: each central exposure area 200 further includes a second stitching exposure area 207 located around the plurality of central circuit patterns, the second stitching exposure area 207 including opposing third and fourth stitching exposure side areas 208a, 208b; the third splicing exposure side area 208a is provided with a third mark C, the fourth splicing exposure side area 208b is provided with a fourth mark D, and the fourth mark D and the third mark C correspond to each other.
Specifically, in this embodiment, there is only one central exposure area 200. The number of center exposure areas is used to form a core circuit arrangement area, and in other embodiments, the number of center exposure areas is not limited thereto.
The fourth mark D and the third mark C correspond to each other, which means that the fourth mark D and the third mark C may form a complete overlay alignment mark.
In this embodiment, the mask includes: a light shielding band 209 is positioned between two adjacent central exposure areas 200, two adjacent peripheral exposure areas 202, and two adjacent central exposure areas 200 and peripheral exposure areas 202.
When a certain area of the mask is used for exposing the wafer, a baffle plate is required to be added above the area which does not need to be exposed for shielding, and the light shielding belt 209 can reduce the occurrence of the condition that the non-exposure area is exposed due to light diffraction generated at the edge of the baffle plate above the mask in the exposure process.
The material of the masking tape 209 comprises chromium.
The light shielding tape 209 has a width ranging from 750 μm to 1500 μm.
With continued reference to fig. 1 and 2, the wafer to be processed is subjected to multiple exposure processes using the reticle, a central circuit pattern (not shown) is formed in the core circuit arrangement region 301, a peripheral circuit pattern (not shown) is formed in the outer circuit arrangement region 302, and a first overlay alignment mark 308 is formed in the first stitching region 304.
Specifically, the mask plate is used to perform multiple exposure processing on each chip region, a central circuit pattern (not shown in the figure) is formed in the core circuit setting region 301, a peripheral circuit pattern (not shown in the figure) is formed in the outer circuit setting region 302, the central circuit pattern is formed by the plurality of central exposure regions 200 of the mask plate, and the peripheral circuit pattern is formed by the plurality of peripheral exposure regions 202 of the mask plate.
The mask is divided into a plurality of central exposure areas 200 and a plurality of peripheral exposure areas 202, one mask is used, different exposure areas are selected to expose the wafer respectively, a region of the target chip is formed, a large-size chip is finally formed, the size of the formed chip is not limited by the size of the mask, and the manufacturing capacity of the large-size chip is improved.
After multiple exposure, a complete and regularly distributed first alignment mark can be formed in the cutting channel region of the formed chip, and the alignment mark is used for detecting the alignment precision of the device and improving the alignment level.
In this embodiment, the forming method of the first overlay alignment mark 308 in the first splicing region 304 includes: forming a first mark pattern in the first stitching region 304 after the first exposure process; after the second exposure process, a second mark pattern is formed in the first stitching region 304, the second mark pattern overlapping the first mark pattern.
In another embodiment, a method for forming the first overlay alignment mark in the first stitching region includes: forming a first mark pattern in the first splicing area after the first exposure treatment; after the second exposure process, a second mark pattern is formed in the first stitching region, the second mark pattern being adjacent to the first mark pattern.
In this embodiment, after the multiple exposure process, a second overlay alignment mark 309 is also formed in the second stitching region 306.
In this embodiment, the method for forming the second overlay alignment mark in the second splicing region 306 includes: forming a third mark pattern in the second stitching region 306 after the third exposure process; after the fourth exposure process, a fourth mark pattern is formed in the second stitching region 306, the third mark pattern overlapping the fourth mark pattern.
The second splicing area 306 adopts a twice exposure forming mode, which is favorable for improving the connection of the circuits in the two adjacent core circuit setting areas and avoiding the occurrence of the wire breakage condition caused by poor splicing.
In another embodiment, the method for forming the second overlay alignment mark in the second splicing region includes: forming a third mark pattern in the second splicing area after the third exposure treatment; after the fourth exposure process, a fourth mark pattern is formed in the second stitching region, the fourth mark pattern being adjacent to the third mark pattern.
Correspondingly, the embodiment of the invention also provides a mask plate for forming the chip, referring to fig. 3, including: a plurality of center exposure areas 200, the center exposure areas 200 including a plurality of center circuit patterns 201; a plurality of peripheral exposure areas 202, wherein each peripheral exposure area 202 comprises a dicing street exposure area 203 and a first splicing exposure area 204 surrounding the dicing street exposure area 203, and the first splicing exposure area 204 comprises a first splicing exposure side area 205a and a second splicing exposure side area 205b which are respectively positioned at two opposite sides of the dicing street exposure area 203; the first splicing exposure side area 205a is provided with a first mark A, the second splicing exposure side area 205B is provided with a second mark B, and the second mark B and the first mark A correspond to each other.
On the one hand, the mask is divided into a plurality of central exposure areas 200 and a plurality of peripheral exposure areas 202, one mask is used, different exposure areas are selected to expose the wafer respectively to form a region of the target chip, and finally a large-size chip is formed, the size of the formed chip is not limited by the size of the mask, and the manufacturing capacity of the large-size chip is improved; on the other hand, after the mask is adopted for multiple exposure, first alignment marks which are completely and regularly distributed can be formed in the cutting channel region of the formed chip and used for detecting alignment precision of the device and improving alignment level.
In this embodiment, the mask includes: a light shielding band 209 is positioned between two adjacent central exposure areas 200, two adjacent peripheral exposure areas 202, and two adjacent central exposure areas 200 and peripheral exposure areas 202.
The arrangement of the light shielding belt 209 can reduce the occurrence of the condition that the non-exposure area is exposed due to light diffraction generated at the edge of the baffle plate above the mask plate in the exposure process.
The material of the masking tape 209 comprises chromium.
The light shielding tape 209 has a width ranging from 750 μm to 1500 μm.
In this embodiment, the peripheral exposure area 202 further includes a peripheral circuit exposure area 206, the peripheral circuit exposure area 206 is located at two sides of the dicing street exposure area 203 and between the dicing street exposure area 203 and the first stitching exposure area 204, and the peripheral circuit exposure area 206 includes a plurality of peripheral circuit patterns (not shown in the figure).
In this embodiment, the mask further includes: each central exposure area 200 further includes a second stitching exposure area 207 located around the plurality of central circuit patterns, the second stitching exposure area 207 including opposing third and fourth stitching exposure side areas 208a, 208b; the third splicing exposure side area 208a is provided with a third mark C, the fourth splicing exposure side area 208b is provided with a fourth mark D, and the fourth mark D and the third mark C correspond to each other.
The third mark and the fourth mark can form a second alignment mark of the core circuit setting area of the chip, which is beneficial to alignment detection near the circuit.
Fig. 8 to 9 are schematic structural views illustrating steps of a method for forming a second alignment mark according to another embodiment of the present invention.
This embodiment differs from the previous embodiment in that: in the provided mask, the fourth mark and the third mark are different in corresponding modes; and forming methods of the second alignment mark in the second splicing region are different.
Referring to fig. 8, a mask is provided, including: the second stitching exposure region includes a third stitching exposure border region 408a and a fourth stitching exposure border region 408b that are opposite; the third mark E is located in the third stitching exposure edge area 408a, the fourth mark F is located in the fourth stitching exposure edge area 408b, and the fourth mark F and the third mark E correspond to each other.
The present embodiment shows only a logo of one shape, which may not be limited to practical use.
The differences between the present embodiment and the previous embodiment further include: the mutual correspondence manners of the first identifier and the second identifier are different, and reference is made to the mutual correspondence manner of the fourth identifier F and the third identifier E for the mutual correspondence manner of the first identifier and the second identifier, which is not described herein.
With continued reference to fig. 9 on the basis of fig. 2, a method for forming the second overlay alignment mark 500 in the second stitching region 306 includes: forming a third mark pattern in the second stitching region 306 after the third exposure process; after the fourth exposure process, a fourth mark pattern is formed in the second stitching region 306, the fourth mark pattern being adjacent to the third mark pattern.
In this embodiment, for the method of forming the first alignment mark in the first splicing region, please refer to the method of forming the second alignment mark, and details are not described here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (16)

1. A reticle, comprising:
a plurality of central exposure areas, the central exposure areas including a plurality of central circuit patterns;
the device comprises a plurality of peripheral exposure areas, a plurality of first splicing exposure areas and a plurality of second splicing exposure areas, wherein each peripheral exposure area comprises a cutting channel exposure area and a first splicing exposure area surrounding the cutting channel exposure area, and the first splicing exposure area comprises a first splicing exposure side area and a second splicing exposure side area which are respectively positioned at two opposite sides of the cutting channel exposure area;
the first mark is arranged in the first spliced exposure side area, the second mark is arranged in the second spliced exposure side area, and the second mark and the first mark correspond to each other.
2. The reticle of claim 1, further comprising: and the shading belt is positioned between the adjacent two central exposure areas, the adjacent two peripheral exposure areas and the adjacent central exposure areas and the peripheral exposure areas.
3. The reticle of claim 2, wherein the material of the light-blocking strip comprises chromium.
4. The reticle of claim 2, wherein the light-blocking strip has a width in the range of 750 μm to 1500 μm.
5. The reticle of claim 1, wherein the peripheral exposure area further comprises peripheral circuit exposure areas located on both sides of the scribe line exposure area and between the scribe line exposure area and the first stitching exposure area, the peripheral circuit exposure areas comprising a plurality of peripheral circuit patterns.
6. The reticle of claim 1, wherein each center exposure region further comprises a second stitching exposure region located about the plurality of center circuit patterns, the second stitching exposure region comprising opposing third and fourth stitching exposure side regions; the third mark is arranged in the third spliced exposure side area, the fourth mark is arranged in the fourth spliced exposure side area, and the fourth mark and the third mark correspond to each other.
7. A method of forming a chip, comprising:
providing a wafer to be processed, wherein the wafer to be processed comprises a plurality of chip areas, each chip area comprises a plurality of core circuit setting areas which are repeatedly distributed and a plurality of outer circuit setting areas which are repeatedly distributed, each outer circuit setting area comprises a cutting channel area, and a first splicing area is arranged between every two adjacent cutting channel areas; providing a mask, the mask comprising: a plurality of central exposure areas, the central exposure areas including a plurality of central circuit patterns; the device comprises a plurality of peripheral exposure areas, a plurality of first splicing exposure areas and a plurality of second splicing exposure areas, wherein each peripheral exposure area comprises a cutting channel exposure area and a first splicing exposure area positioned around the cutting channel exposure area, and the first splicing exposure area comprises a first splicing exposure side area and a second splicing exposure side area which are respectively positioned on two opposite sides of the cutting channel exposure area; the first mark is arranged in the first spliced exposure side area, the second mark is arranged in the second spliced exposure side area, and the second mark and the first mark correspond to each other;
and performing multiple exposure treatment on the wafer to be treated by adopting the mask, forming a central circuit pattern in the core circuit setting region, forming a peripheral circuit pattern in the outer circuit setting region, and forming a first alignment mark in the first splicing region.
8. The method of forming a chip of claim 7, wherein the method of forming the first overlay alignment mark in the first stitching region comprises: forming a first mark pattern in the first splicing area after the first exposure treatment; and after the second exposure treatment, forming a second mark pattern in the first splicing area, wherein the second mark pattern is overlapped with the first mark pattern.
9. The method of forming a chip of claim 7, wherein forming the first overlay alignment mark in the first stitching region comprises: forming a first mark pattern in the first splicing area after the first exposure treatment; after the second exposure process, a second mark pattern is formed in the first stitching region, the second mark pattern being adjacent to the first mark pattern.
10. The method of forming a chip of claim 7, wherein the reticle further comprises: the peripheral circuit exposure area further comprises peripheral circuit exposure areas, the peripheral circuit exposure areas are located on two sides of the cutting channel exposure area and located between the cutting channel exposure areas and the first splicing exposure areas, and the peripheral circuit exposure areas comprise a plurality of peripheral circuit patterns.
11. The method of forming a chip of claim 10, wherein the reticle further comprises: each central exposure area further comprises a second spliced exposure area positioned around the plurality of central circuit patterns, and the second spliced exposure area comprises a third spliced exposure side area and a fourth spliced exposure side area which are opposite; the third mark is arranged in the third spliced exposure side area, the fourth mark is arranged in the fourth spliced exposure side area, and the fourth mark and the third mark correspond to each other.
12. The method of forming a chip of claim 11, wherein adjacent core circuit placement areas have a second stitching area therebetween, the method further comprising: and after the multiple exposure treatment, forming a second alignment mark in the second splicing region.
13. The method of forming a chip of claim 12, wherein forming the second overlay alignment mark in the second stitching region comprises: forming a third mark pattern in the second splicing area after the third exposure treatment; and after the fourth exposure treatment, forming a fourth mark pattern in the second splicing area, wherein the third mark pattern is overlapped with the fourth mark pattern.
14. The method of forming a chip of claim 12, wherein forming the second overlay alignment mark in the second stitching region comprises: forming a third mark pattern in the second splicing area after the third exposure treatment; after the fourth exposure process, a fourth mark pattern is formed in the second stitching region, the fourth mark pattern being adjacent to the third mark pattern.
15. The method of forming a chip of claim 7, wherein the first stitching region has a width in the range of 0.1 μm to 0.5 μm.
16. The method of claim 7, wherein the central circuit pattern is formed by the plurality of central exposed areas of the reticle and the peripheral circuit pattern is formed by the plurality of peripheral exposed areas of the reticle.
CN202210109341.7A 2022-01-28 2022-01-28 Mask and chip forming method Pending CN116560193A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117406545A (en) * 2023-12-14 2024-01-16 合肥晶合集成电路股份有限公司 Semiconductor mask and manufacturing method thereof
CN117577633A (en) * 2024-01-15 2024-02-20 合肥晶合集成电路股份有限公司 Overlay mark and measurement method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117406545A (en) * 2023-12-14 2024-01-16 合肥晶合集成电路股份有限公司 Semiconductor mask and manufacturing method thereof
CN117406545B (en) * 2023-12-14 2024-03-01 合肥晶合集成电路股份有限公司 Semiconductor mask and manufacturing method thereof
CN117577633A (en) * 2024-01-15 2024-02-20 合肥晶合集成电路股份有限公司 Overlay mark and measurement method
CN117577633B (en) * 2024-01-15 2024-04-05 合肥晶合集成电路股份有限公司 Overlay mark and measurement method

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