CN117406545A - Semiconductor mask and manufacturing method thereof - Google Patents
Semiconductor mask and manufacturing method thereof Download PDFInfo
- Publication number
- CN117406545A CN117406545A CN202311715543.7A CN202311715543A CN117406545A CN 117406545 A CN117406545 A CN 117406545A CN 202311715543 A CN202311715543 A CN 202311715543A CN 117406545 A CN117406545 A CN 117406545A
- Authority
- CN
- China
- Prior art keywords
- region
- areas
- area
- buffer
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000005520 cutting process Methods 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 34
- 238000005259 measurement Methods 0.000 claims description 22
- 230000008569 process Effects 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 238000011161 development Methods 0.000 claims description 9
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 6
- 239000011521 glass Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 description 7
- 238000012986 modification Methods 0.000 description 7
- 230000004048 modification Effects 0.000 description 7
- 238000012360 testing method Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 5
- 239000011651 chromium Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 238000012938 design process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
The invention relates to the field of semiconductors, in particular to a semiconductor mask and a manufacturing method thereof. The semiconductor mask plate comprises a plurality of exposure units, and each exposure unit comprises: the device frame areas are in a rectangular array and comprise a chip area and a first buffer area, and the first buffer area surrounds the chip area; the plurality of cutting channel areas are positioned between two adjacent device frame areas, part of the cutting channel areas are provided with measuring device areas or alignment mark areas, and the rest of the cutting channel areas are not provided with the measuring device areas and the alignment mark areas; the ratio of the size of the device frame area to the size precision of the semiconductor mask is 10N, and N is a positive integer. The invention improves the alignment precision of each device region in the mask after merging under the condition of not increasing the cost of the mask.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a semiconductor mask and a manufacturing method thereof.
Background
During the fabrication of integrated circuits, new process nodes may be formed by die shrinking (die shrink). Semiconductor fabrication forms active chips (chips) on a wafer, typically in a minimum unit of exposure (shot) exposure. During the design of the exposure unit of the mask, the contracted chips are separated from each other by dicing streets (Scribe lines). After the exposure unit of the mask is shrunk, there is a case that a Mark (Mark) placed in the exposure unit does not match an actual coordinate, which affects the precision of the placement of the Mark and the chip in the exposure unit of the mask. Therefore, there is a need for improvement.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor mask and a method for manufacturing the same, which are used for solving the problem of low precision of placement of the existing marks and chips in the exposure unit of the photomask.
To achieve the above and other related objects, the present invention provides a semiconductor reticle including a plurality of exposure units, each of the exposure units including:
the device comprises a plurality of device frame areas, a plurality of first buffer areas and a plurality of second buffer areas, wherein the device frame areas are in a rectangular array and comprise chip areas and the first buffer areas surround the chip areas; and
the plurality of cutting channel areas are positioned between two adjacent device frame areas, part of the cutting channel areas are provided with measuring device areas or alignment mark areas, and the rest of the cutting channel areas are not provided with the measuring device areas and the alignment mark areas;
the ratio of the size of the device frame area to the size precision of the semiconductor mask plate is 10N, and N is a positive integer.
In one embodiment of the invention, the measuring device region or the alignment mark region is located at an intermediate position of the scribe line region.
In one embodiment of the present invention, a second buffer area is disposed in the scribe line area, the second buffer area surrounding the measuring device area, the second buffer area being used to mark the position of the measuring device area.
In one embodiment of the invention, the scribe line region and the first buffer region are fabricated by chrome fill to perform photolithographic development of a wafer front end process.
In one embodiment of the invention, the scribe line region and the first buffer region are fabricated by glass filling to perform photolithographic development of the wafer metal layer.
The invention also provides a manufacturing method of the semiconductor mask, which comprises the following steps:
a plurality of exposure units are arranged on the mask body;
in each exposure unit, a plurality of device frame areas and a plurality of dicing street areas are arranged, and the dicing street areas are arranged between two adjacent device frame areas;
arranging a measuring device region or an alignment mark region in part of the dicing street region;
setting the ratio of the size of the device frame area to the size precision of the semiconductor mask plate to 10N, wherein N is a positive integer;
in the device frame region, a chip region and a first buffer region are arranged, and the first buffer region is arranged at the periphery of the chip region.
In one embodiment of the present invention, the step of disposing a measuring device region or an alignment mark region in a part of the scribe line region includes:
and setting the position of the measuring device region or the alignment mark region to be positioned at the middle position of the cutting path region.
In one embodiment of the present invention, the step of disposing a measuring device region or an alignment mark region in a part of the scribe line region includes:
a second buffer area is arranged in the cutting channel area;
the second buffer area is set to surround the measuring device area and used for marking the position of the measuring device area.
In one embodiment of the invention, the scribe line region and the first buffer region are fabricated by chrome fill during photolithographic development of a wafer front end process.
In one embodiment of the invention, the scribe line region and the first buffer region are fabricated by glass filling during photolithographic development of the wafer metal layer.
As described above, the semiconductor mask and the manufacturing method thereof have the following beneficial effects: the unexpected technical effects of the invention are: according to the method and the device, the size of the chip area is appropriately expanded by setting the first buffer area, so that the ratio of the size of the device frame area to the size precision of the semiconductor mask is an integral multiple of 10, and the size of the device frame area can still be kept on the size precision of the semiconductor mask after chip shrinkage process treatment, and the precision of the chip area in an exposure unit is improved. Under the condition of not increasing the cost of the mask, the alignment precision of each device region in the mask after merging is improved.
Drawings
Fig. 1 is a schematic layout diagram of a semiconductor mask according to the present invention.
Fig. 2 is a schematic structural diagram of a semiconductor mask according to the present invention.
Fig. 3 is a schematic cross-sectional view of fig. 2 illustrating the present invention.
Fig. 4 shows a method for fabricating a semiconductor mask according to the present invention.
Fig. 5 is a schematic flow chart of step S40 in fig. 4 according to the present invention.
Description of element reference numerals
10. An exposure unit; 110. a device frame region; 111. a chip region; 112. a first buffer;
120. cutting the road area; 121. measuring the device region; 122. an alignment mark region;
1210. an actual device region; 1211. a second buffer;
20. a wafer; 210. a front-end-of-line process zone; 220. a contact hole region; 230. a metal layer region; 240. a via region; 250. a metal foot region; 260. an insulating ring region.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. It is also to be understood that the terminology used in the examples of the invention is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the invention. The test methods in the following examples, in which specific conditions are not noted, are generally conducted under conventional conditions or under conditions recommended by the respective manufacturers.
It should be understood that the structures, proportions, sizes, etc. shown in the drawings are for illustration purposes only and should not be construed as limiting the invention to the extent that it can be practiced, since modifications, changes in the proportions, or otherwise, used in the practice of the invention, are not intended to be critical to the essential characteristics of the invention, but are intended to fall within the spirit and scope of the invention. Also, the terms such as "upper," "lower," "left," "right," "middle," and "a" and the like recited in the present specification are merely for descriptive purposes and are not intended to limit the scope of the invention, but are intended to provide relative positional changes or modifications without materially altering the technical context in which the invention may be practiced.
Referring to fig. 1 to 5, in some embodiments of the present invention, a semiconductor mask and a method for manufacturing the same are provided, which can be applied to the field of photolithography development of semiconductor chips. For example, it can be applied to the process of forming the minimum unit (shot) exposure of the wafer 20. By arranging the positions and the sizes of the device frame region 110 and the scribe line region 120 in one exposure unit 10, the accuracy of the alignment mark region 122, the chip region 111, and the measurement device region 121 in the exposure unit 10 can be improved. The following is a detailed description of specific embodiments.
Referring to fig. 1 and 2, in some embodiments of the present invention, a semiconductor mask is provided, which may include a plurality of exposure units (shots) 10, where each exposure unit 10 may include a plurality of device frame regions 110 and a plurality of scribe line regions 120. Wherein the plurality of device frame regions 110 may be arranged in a rectangular array shape. A chip region 111 and a first buffer region 112 may be included in each device frame region 110. The chip region 111 may have a rectangular shape, the first buffer region 112 may have a rectangular ring shape, and the first buffer region 112 may surround the chip region 111. The ratio of the size of the device frame region 110 to the size accuracy of the semiconductor mask is 10n, where n is a positive integer. I.e., the ratio of the size of the device frame region 110 to the dimensional accuracy of the semiconductor reticle is an integer multiple of 10. After the chip shrink (die shrink) process, the size of the device frame area 110 can still be kept on the dimensional accuracy of the semiconductor mask, and the size of the device frame area 110 does not have decimal points, so that the problem of insufficient accuracy of the alignment mark area 122, the chip area 111 and the measurement device area 121 can not occur. In one aspect, the first buffer 112 functions to mark the chip area 111. On the other hand, when the size of the chip region 111 is not tens times larger than the size accuracy of the semiconductor mask, it is equivalent to appropriately expanding the size of the chip region 111 by the first buffer region 112. The ratio of the size of the device frame area 110 to the size precision of the semiconductor mask is an integer multiple of 10, so that the size of the device frame area 110 can still be kept at the size precision of the semiconductor mask after the chip shrink (die shrink) process treatment, so as to improve the precision of the chip area 111 in the exposure unit 10.
Referring to fig. 1 and 2, in some embodiments of the present invention, a plurality of scribe line regions 120 may be located between two adjacent device frame regions 110. The scribe line region 120 is a line that cuts the chip from the wafer 20 and serves to split the chip, where it is fed during the actual process. A measurement device region (testkey) 121 or a alignment Mark region (Mark) 122 may be disposed in the partial scribe line region 120, and the measurement device region 121 and the alignment Mark region 122 are not disposed in the remaining scribe line region 120. I.e., the measurement device region 121 is not disposed in the remaining scribe line region 120, nor is the alignment mark region 122 disposed. The measurement device region 121 is disposed at a peripheral location of each integrated circuit chip on the wafer 20 and functions as a test on integrated circuit chip wafer (WAT, wafer Acceptance Test). In the design process of the semiconductor mask, the alignment mark region 122 is used for alignment between the film layers on the wafer 20. Alignment mark regions 122 are respectively delineated on the semiconductor reticle and the substrate for determining the relative position and orientation between the semiconductor reticle and the substrate.
Referring to fig. 1 and 2, in some embodiments of the present invention, in the case where the measuring device region 121 is disposed within the scribe line region 120, the measuring device region 121 may be located at an intermediate position of the scribe line region 120. The device region 121 is tested for electrical parameters on the scribe line region 120 to more accurately measure the critical dimension of the chip. In the case of disposing the alignment mark region 122 in the scribe line region 120, the alignment mark region 122 may be located at a middle position of the scribe line region 120. The alignment mark region 122 is disposed at a location intermediate the scribe line region 120 to better align between the layers of the wafer 20 for determining the relative position and orientation between the semiconductor reticle and the substrate.
Referring to fig. 1, 2 and 3, in some embodiments of the present invention, a second buffer region 1211 and an actual device region 1210 may be disposed in the measurement device region 121, and the second buffer region 1211 may surround the actual device region 1210. In one aspect, the second buffer region 1211 functions to mark the actual device region 1210. On the other hand, in the case where the size of the actual device region 1210 is not tens times as large as the size accuracy of the semiconductor mask, it is equivalent to appropriately expanding the size of the actual device region 1210 by the second buffer region 1211. The ratio of the overall dimension of the measurement device region 121 to the dimension precision of the semiconductor mask is an integer multiple of 10, so that the overall dimension of the measurement device region 121 can still be maintained on the dimension precision of the semiconductor mask after the chip shrinkage (die shrink) process treatment, so as to improve the precision of the measurement device region 121 in the exposure unit 10.
Referring to fig. 3, in some embodiments of the present invention, the measuring device area 121 of the exposure unit 10 corresponds to a measuring device (Testkey) on the wafer 20 for electrically testing a test structure on the wafer 20, and the analysis of WAT data can effectively monitor the problems in the semiconductor process, which is beneficial to the adjustment and optimization of the process. For the Testkey (measurement device) on the wafer 20, the front-end-of-line process (FEoL structures) is performed to form the front-end-of-line region 210 in the measurement device (Testkey), and the scribe line region 120 does not require Ion Implantation (IMP). Thus, a first semiconductor mask may be fabricated in which the scribe line region 120, the first buffer region 112, are fabricated by chromium (Cr) filling. In a subsequent process, a Contact (CT) 220, a Metal layer (Metal) 230, a Via (Via) 240, a Metal foot 250, and an insulating ring 260 are formed in the measurement device (Testkey). The top of the contact hole region 220 may be connected to the first metal layer region 230, and the top of the first metal layer region 230 may be connected to the first via hole region 240. The top of the first via region 240 may be connected to the second metal layer region 230, and the top of the second metal layer region 230 may be connected to the second via region 240. One Metal layer region 230 corresponds to one via region 240, and after the mth via region 240 is connected to the top of the mth Metal layer region 230, the top of the mth via region 240 may be connected to the top Metal layer region (TM) 230. Each Metal layer 230 may be electrically connected to a Metal pad 250. The top metal layer region 230 may be connected to an insulating ring region (PV ring) 260, the insulating ring region 260 serving as a guard for the measurement devices (testkeys) on the wafer 20. And, since the second buffer region 1211 can surround the actual device region 1210, the dimensions of the metal foot region 250 and the insulating ring region 260 can be kept at the dimensional accuracy of the semiconductor mask without being affected by chip shrinkage.
Referring to fig. 4, in some embodiments of the present invention, a method for manufacturing a semiconductor mask may be provided, which includes the following steps.
Step S10, a plurality of exposure units are arranged on the mask body.
Step S20, arranging a plurality of device frame regions and a plurality of scribe line regions in each exposure unit, and arranging the scribe line regions between two adjacent device frame regions.
And step S30, arranging a measuring device area or an alignment mark area in part of the cutting channel area.
And step S40, setting the ratio of the size of the device frame area to the size precision of the semiconductor mask plate to 10N, wherein N is a positive integer.
In the step S50, a chip area and a first buffer area are arranged in the device frame area, and the first buffer area is arranged at the periphery of the chip area.
Step S10, a plurality of exposure units are arranged on the mask body.
In some embodiments, the semiconductor mask may include a plurality of exposure units (shots) 10, where the exposure units 10 are the minimum units of exposure, the exposure units (shots) may include one or more chip areas (Die) 111, and peripheral test circuits may be further disposed in the exposure units 10.
Step S20, arranging a plurality of device frame regions and a plurality of scribe line regions in each exposure unit, and arranging the scribe line regions between two adjacent device frame regions.
In some embodiments, the plurality of device frame regions 110 may be arranged in a rectangular array shape. A chip region 111 and a first buffer region 112 may be included in each device frame region 110. The chip region 111 may have a rectangular shape, the first buffer region 112 may have a rectangular ring shape, and the first buffer region 112 may surround the chip region 111.
And step S30, arranging a measuring device area or an alignment mark area in part of the cutting channel area.
In some embodiments, a measurement device region (testkey) 121 or a alignment Mark region (Mark) 122 may be disposed in a portion of the scribe line region 120, and the measurement device region 121 and the alignment Mark region 122 are not disposed in the remaining scribe line region 120. I.e., the measurement device region 121 is not disposed in the remaining scribe line region 120, nor is the alignment mark region 122 disposed. The measurement device region 121 is disposed at a peripheral location of each integrated circuit chip on the wafer 20 and functions as a test on integrated circuit chip wafer (WAT, wafer Acceptance Test). In the design process of the semiconductor mask, the alignment mark region 122 is used for alignment between the film layers on the wafer 20. Alignment mark regions 122 are respectively delineated on the semiconductor reticle and the substrate for determining the relative position and orientation between the semiconductor reticle and the substrate.
And step S40, setting the ratio of the size of the device frame area to the size precision of the semiconductor mask plate to 10N, wherein N is a positive integer.
In some embodiments, the ratio of the size of the device frame region 110 to the dimensional accuracy of the semiconductor reticle is 10n, where n is a positive integer. I.e., the ratio of the size of the device frame region 110 to the dimensional accuracy of the semiconductor reticle is an integer multiple of 10. After the chip shrink (die shrink) process, the size of the device frame area 110 can still be kept on the dimensional accuracy of the semiconductor mask, and the size of the device frame area 110 does not have decimal points, so that the problem of insufficient accuracy of the alignment mark area 122, the chip area 111 and the measurement device area 121 can not occur.
In the step S50, a chip area and a first buffer area are arranged in the device frame area, and the first buffer area is arranged at the periphery of the chip area.
In some embodiments, on the one hand, the first buffer 112 functions to mark the chip area 111. On the other hand, when the size of the chip region 111 is not tens times larger than the size accuracy of the semiconductor mask, it is equivalent to appropriately expanding the size of the chip region 111 by the first buffer region 112. The ratio of the size of the device frame area 110 to the size precision of the semiconductor mask is an integer multiple of 10, so that the size of the device frame area 110 can still be kept at the size precision of the semiconductor mask after the chip shrink (die shrink) process treatment, so as to improve the precision of the chip area 111 in the exposure unit 10.
Referring to fig. 1, 2, 3 and 4, in some embodiments of the present invention, first, in an exposure unit, a device frame region 110 that needs to be merged (merge) may be pre-arranged, where the size of the device frame region 110 is on the order of 10nm, and the size accuracy of a semiconductor mask is on the order of 1 nm. Secondly, masks of different materials can be selected in different manufacturing processes. For example, in the front-end-of-line process, a mask made of chromium (Cr) material may be used, and in the subsequent process, a mask made of glass (glass) material may be used. Then, after the exposure unit 10 pieces of the device frame area 110 are pre-arranged, a chip area (main chip) 111 of an actual device is put in. Since the measuring device region 121 and the alignment mark region 122 are incorporated into one exposure unit 10 by coordinates and the chip region 111 size (CAD window), the coordinates are determined by the exposure unit 10 and the chip region 111 size. At this time, the size and coordinates of the chip region 111 corresponding to the actual device are set to the exposure unit 10, forming the final semiconductor mask. The precision of the semiconductor mask after the chip shrinking process is improved, the coordinates of the alignment mark areas 122 on different film layers (layers) are consistent with the actual coordinates, the alignment accuracy of each film layer during exposure is improved, and the cost of the mask is not increased.
Referring to fig. 4 and 5, in some embodiments of the present invention, the step S30 may include a step S310, a step S320, and a step S330. Step S310 may be represented by setting the position of the measuring device region 121 or the alignment mark region 122 to be located at the middle position of the scribe line region 120. Step S320 may be represented by providing a second buffer 1211 within the scribe line region 120. Step S330 may be represented by setting a second buffer 1211 surrounding the device frame area 110, the second buffer 1211 being used to mark the location of the device frame area 110.
In summary, the invention provides a semiconductor mask and a manufacturing method thereof, and the unexpected technical effects are as follows: according to the method and the device, the size of the chip area is appropriately expanded by setting the first buffer area, so that the ratio of the size of the device frame area to the size precision of the semiconductor mask is an integral multiple of 10, and the size of the device frame area can still be kept on the size precision of the semiconductor mask after chip shrinkage process treatment, and the precision of the chip area in an exposure unit is improved. Under the condition of not increasing the cost of the mask, the alignment precision of each device region in the mask after merging is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
In the description herein, numerous specific details are provided, such as examples of components and/or methods, to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that an embodiment of the invention can be practiced without one or more of the specific details, or with other apparatus, systems, components, methods, components, materials, parts, and so forth. In other instances, well-known structures, materials, or operations are not specifically shown or described in detail to avoid obscuring aspects of embodiments of the invention.
Reference throughout this specification to "one embodiment," "an embodiment," or "a particular embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment, and not necessarily all embodiments, of the present invention. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," or "in a specific embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics of any specific embodiment of the present invention may be combined in any suitable manner with one or more other embodiments. It will be appreciated that other variations and modifications of the embodiments of the invention described and illustrated herein are possible in light of the teachings herein and are to be considered as part of the spirit and scope of the invention.
As used in the description herein and throughout the claims that follow, unless otherwise indicated, "a", "an", and "the" include plural references. Also, as used in the description herein and throughout the claims that follow, unless otherwise indicated, the meaning of "in …" includes "in …" and "on …".
The above description of illustrated embodiments of the invention, including what is described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. Although specific embodiments of, and examples for, the invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention, as those skilled in the relevant art will recognize and appreciate. As noted, these modifications can be made to the present invention in light of the foregoing description of illustrated embodiments of the present invention and are to be included within the spirit and scope of the present invention.
The systems and methods have been described herein in general terms as being helpful in understanding the details of the present invention. Furthermore, various specific details have been set forth in order to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that an embodiment of the invention can be practiced without one or more of the specific details, or with other apparatus, systems, assemblies, methods, components, materials, parts, and/or the like. In other instances, well-known structures, materials, and/or operations are not specifically shown or described in detail to avoid obscuring aspects of embodiments of the invention.
Claims (10)
1. A semiconductor reticle, the semiconductor reticle comprising a plurality of exposure units, each of the exposure units comprising:
the device comprises a plurality of device frame areas, a plurality of first buffer areas and a plurality of second buffer areas, wherein the device frame areas are in a rectangular array and comprise chip areas and the first buffer areas surround the chip areas; and
the plurality of cutting channel areas are positioned between two adjacent device frame areas, part of the cutting channel areas are provided with measuring device areas or alignment mark areas, and the rest of the cutting channel areas are not provided with the measuring device areas and the alignment mark areas;
the ratio of the size of the device frame area to the size precision of the semiconductor mask plate is 10N, and N is a positive integer.
2. The semiconductor reticle of claim 1, wherein the measurement device region or the alignment mark region is located at a middle position of the scribe line region.
3. The semiconductor mask according to claim 1, wherein a second buffer area is provided in the scribe line area, the second buffer area surrounding the measurement device area, the second buffer area being used to mark a position of the measurement device area.
4. The semiconductor reticle of claim 1, wherein the scribe line region and the first buffer region are fabricated by chrome fill for photolithographic development of a wafer front end process.
5. The semiconductor reticle of claim 1, wherein the scribe line region and the first buffer region are fabricated by glass filling for photolithographic development of a wafer metal layer.
6. The manufacturing method of the semiconductor mask plate is characterized by comprising the following steps of:
a plurality of exposure units are arranged on the mask body;
in each exposure unit, a plurality of device frame areas and a plurality of dicing street areas are arranged, and the dicing street areas are arranged between two adjacent device frame areas;
arranging a measuring device region or an alignment mark region in part of the dicing street region;
setting the ratio of the size of the device frame area to the size precision of the semiconductor mask plate to 10N, wherein N is a positive integer; and
in the device frame region, a chip region and a first buffer region are arranged, and the first buffer region is arranged at the periphery of the chip region.
7. The method of fabricating a semiconductor reticle according to claim 6, wherein the step of disposing a measuring device region or an alignment mark region in a portion of the scribe line region comprises:
and setting the position of the measuring device region or the alignment mark region to be positioned at the middle position of the cutting path region.
8. The method of fabricating a semiconductor reticle according to claim 6, wherein the step of disposing a measuring device region or an alignment mark region in a portion of the scribe line region comprises:
a second buffer area is arranged in the cutting channel area;
the second buffer area is set to surround the measuring device area and used for marking the position of the measuring device area.
9. The method of claim 6, wherein the scribe line region and the first buffer region are fabricated by chrome filling during photolithographic development of a wafer front end process.
10. The method of claim 6, wherein the scribe line region and the first buffer region are fabricated by glass filling during photolithographic development of the wafer metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311715543.7A CN117406545B (en) | 2023-12-14 | 2023-12-14 | Semiconductor mask and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311715543.7A CN117406545B (en) | 2023-12-14 | 2023-12-14 | Semiconductor mask and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117406545A true CN117406545A (en) | 2024-01-16 |
| CN117406545B CN117406545B (en) | 2024-03-01 |
Family
ID=89500316
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311715543.7A Active CN117406545B (en) | 2023-12-14 | 2023-12-14 | Semiconductor mask and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117406545B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117631437A (en) * | 2024-01-25 | 2024-03-01 | 合肥晶合集成电路股份有限公司 | Mask structure and method for placing alignment marks of semiconductor wafer |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001035776A (en) * | 1999-07-22 | 2001-02-09 | Seiko Epson Corp | Method for manufacturing semiconductor device, and reticle |
| JP2007310048A (en) * | 2006-05-17 | 2007-11-29 | Sharp Corp | Photomask, wafer and semiconductor chip |
| CN102156392A (en) * | 2010-02-11 | 2011-08-17 | 中芯国际集成电路制造(上海)有限公司 | Device and method for detecting alignment parameter of photoetching machine |
| CN102436151A (en) * | 2011-12-22 | 2012-05-02 | 上海宏力半导体制造有限公司 | Forming method of photoetching layout |
| CN102809895A (en) * | 2012-07-23 | 2012-12-05 | 上海宏力半导体制造有限公司 | Photoetching layout, photoresist graph and method for measuring exposure error of photoresist graph |
| CN107315320A (en) * | 2017-05-10 | 2017-11-03 | 株洲中车时代电气股份有限公司 | Power semiconductor chip, the reticle and its exposure method of the chip |
| CN112071824A (en) * | 2020-09-18 | 2020-12-11 | 上海华虹宏力半导体制造有限公司 | Grating device mask and manufacturing method |
| CN113534601A (en) * | 2020-04-13 | 2021-10-22 | 长鑫存储技术有限公司 | Layout method and device of mask and mask |
| CN214623293U (en) * | 2021-04-29 | 2021-11-05 | 合肥晶合集成电路股份有限公司 | Overlay alignment mark and mask plate assembly |
| CN115079510A (en) * | 2022-08-23 | 2022-09-20 | 深圳芯能半导体技术有限公司 | Photomask and photomask design method |
| CN115729030A (en) * | 2021-08-31 | 2023-03-03 | 无锡华润上华科技有限公司 | Mask plate with photoetching self-alignment precision measurement structure and photoetching method |
| CN116068844A (en) * | 2023-03-10 | 2023-05-05 | 合肥晶合集成电路股份有限公司 | Mask plate and preparation method of wafer |
| CN116107154A (en) * | 2023-04-13 | 2023-05-12 | 长鑫存储技术有限公司 | Mask data generation method, device, equipment and medium |
| CN116560193A (en) * | 2022-01-28 | 2023-08-08 | 中芯国际集成电路制造(上海)有限公司 | Mask and chip forming method |
-
2023
- 2023-12-14 CN CN202311715543.7A patent/CN117406545B/en active Active
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001035776A (en) * | 1999-07-22 | 2001-02-09 | Seiko Epson Corp | Method for manufacturing semiconductor device, and reticle |
| JP2007310048A (en) * | 2006-05-17 | 2007-11-29 | Sharp Corp | Photomask, wafer and semiconductor chip |
| CN102156392A (en) * | 2010-02-11 | 2011-08-17 | 中芯国际集成电路制造(上海)有限公司 | Device and method for detecting alignment parameter of photoetching machine |
| CN102436151A (en) * | 2011-12-22 | 2012-05-02 | 上海宏力半导体制造有限公司 | Forming method of photoetching layout |
| CN102809895A (en) * | 2012-07-23 | 2012-12-05 | 上海宏力半导体制造有限公司 | Photoetching layout, photoresist graph and method for measuring exposure error of photoresist graph |
| CN107315320A (en) * | 2017-05-10 | 2017-11-03 | 株洲中车时代电气股份有限公司 | Power semiconductor chip, the reticle and its exposure method of the chip |
| CN113534601A (en) * | 2020-04-13 | 2021-10-22 | 长鑫存储技术有限公司 | Layout method and device of mask and mask |
| CN112071824A (en) * | 2020-09-18 | 2020-12-11 | 上海华虹宏力半导体制造有限公司 | Grating device mask and manufacturing method |
| CN214623293U (en) * | 2021-04-29 | 2021-11-05 | 合肥晶合集成电路股份有限公司 | Overlay alignment mark and mask plate assembly |
| CN115729030A (en) * | 2021-08-31 | 2023-03-03 | 无锡华润上华科技有限公司 | Mask plate with photoetching self-alignment precision measurement structure and photoetching method |
| CN116560193A (en) * | 2022-01-28 | 2023-08-08 | 中芯国际集成电路制造(上海)有限公司 | Mask and chip forming method |
| CN115079510A (en) * | 2022-08-23 | 2022-09-20 | 深圳芯能半导体技术有限公司 | Photomask and photomask design method |
| CN116068844A (en) * | 2023-03-10 | 2023-05-05 | 合肥晶合集成电路股份有限公司 | Mask plate and preparation method of wafer |
| CN116107154A (en) * | 2023-04-13 | 2023-05-12 | 长鑫存储技术有限公司 | Mask data generation method, device, equipment and medium |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117631437A (en) * | 2024-01-25 | 2024-03-01 | 合肥晶合集成电路股份有限公司 | Mask structure and method for placing alignment marks of semiconductor wafer |
| CN117631437B (en) * | 2024-01-25 | 2024-05-07 | 合肥晶合集成电路股份有限公司 | Method for placing alignment marks of semiconductor wafer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117406545B (en) | 2024-03-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI463246B (en) | Semiconductor device and manufacturing method thereof, mask for manufacturing semiconductor and processing method of optical proximity | |
| CN117406545B (en) | Semiconductor mask and manufacturing method thereof | |
| US8592107B2 (en) | Method and apparatus of providing overlay | |
| US7642103B2 (en) | Method of fabricating semiconductor device | |
| US9177878B2 (en) | Method for indexing dies comprising integrated circuits | |
| JP3708058B2 (en) | Photomask manufacturing method and semiconductor device manufacturing method using the photomask | |
| CN103853870A (en) | Distinguishable IC Patterns with Encoded Information | |
| US7432605B2 (en) | Overlay mark, method for forming the same and application thereof | |
| US6737205B2 (en) | Arrangement and method for transferring a pattern from a mask to a wafer | |
| US7745067B2 (en) | Method for performing place-and-route of contacts and vias in technologies with forbidden pitch requirements | |
| CN111128829B (en) | Alignment method and calibration method | |
| CN116203808B (en) | Overlay error measurement method and overlay mark | |
| US6489067B2 (en) | Reticle for manufacturing semiconductor integrated circuit | |
| US6727989B1 (en) | Enhanced overlay measurement marks for overlay alignment and exposure tool condition control | |
| JP2006332177A (en) | Semiconductor wafer, manufacturing method thereof and mask | |
| US8031329B2 (en) | Overlay mark, and fabrication and application of the same | |
| US6379848B1 (en) | Reticle for use in photolithography and methods for inspecting and making same | |
| CN115824036A (en) | Self-alignment precision measurement structure and method for measuring overlay deviation of same-layer exposure pattern | |
| US20030232253A1 (en) | Techniques to characterize iso-dense effects for microdevice manufacture | |
| US9978625B2 (en) | Semiconductor method and associated apparatus | |
| KR960011264B1 (en) | Contact hole type confirmation method of semiconductor device | |
| Cresswell et al. | New test structure for nanometer-level overlay and feature-placement metrology | |
| US9318399B2 (en) | Semiconductor wafers employing a fixed-coordinate metrology scheme and methods for fabricating integrated circuits using the same | |
| CN113985710A (en) | Overlay measuring method and manufacturing method of semiconductor device | |
| CN117970739A (en) | Photomask of large-size spliced product and on-line measuring and positioning method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |