CN214623293U - Overlay alignment mark and mask plate assembly - Google Patents
Overlay alignment mark and mask plate assembly Download PDFInfo
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- CN214623293U CN214623293U CN202120925351.9U CN202120925351U CN214623293U CN 214623293 U CN214623293 U CN 214623293U CN 202120925351 U CN202120925351 U CN 202120925351U CN 214623293 U CN214623293 U CN 214623293U
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- alignment mark
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Abstract
The utility model provides an overlay alignment mark, include front alignment mark, deformation buffer zone and work as the layer alignment mark, front alignment mark with the deformation buffer zone is located same front layer material, the deformation buffer zone is located the front layer alignment mark outside, work as the layer alignment mark and be located on the front layer material, just work as the layer alignment mark and be located the front layer alignment mark is inboard perhaps work as the layer alignment mark with the crisscross setting of front layer alignment mark. Through setting up deformation buffer zone around the outside of front layer alignment mark, when the wafer passes through thermal treatment process, deformation buffer zone is as the buffer zone, can reduce the thermal expansion deformation of front layer alignment mark to can solve the alignment mark of yellow light volume time measurement front layer and produce deformation and lead to measuring the problem of distortion.
Description
Technical Field
The utility model relates to the field of semiconductor technology, in particular to alignment mark and mask plate subassembly are carved to overlap.
Background
The overlay accuracy (OVL) is a basic measurement index of the photolithography process, and the overlay accuracy ensures the alignment degree between lines of different layers. Briefly, the OVL is the alignment accuracy between the current layer and the previous layer in the photolithography process, and if the alignment accuracy of the photolithography process exceeds the error tolerance, the interlayer design circuit may be broken or shorted due to displacement, thereby affecting the yield of the product.
The wafer comprises a plurality of semiconductor chips and cutting lines for separating the semiconductor chips. To achieve accurate alignment, one or more sets of test patterns are typically made in the scribe line as a marker for alignment deviation of two or more lithography processes before and after inspection by a technician during the manufacturing process to monitor the process quality.
And between every two photoetching processes, a plurality of materials are stacked, the thermal expansion coefficients of all the materials are different, and in the heat treatment process, the front layer material deforms due to thermal expansion, so that the overlay mark of the front layer is deformed during yellow light measurement, and the measurement distortion is caused.
Disclosure of Invention
An object of the utility model is to provide an alignment mark and mask blank subassembly are carved to solve the front layer material and warp because of the thermal expansion, cause the alignment mark of the time measuring front layer of the amount of yellow light to produce deformation and lead to the problem of measuration distortion.
In order to solve the above technical problem, the utility model provides an overlay alignment mark, include: front alignment mark, deformation buffer zone and when layer alignment mark, the front alignment mark with the deformation buffer zone is located same front layer material, the deformation buffer zone is located the front layer alignment mark outside, when layer alignment mark is located on the front layer material, just when layer alignment mark is located the front layer alignment mark is inboard or when layer alignment mark with the staggered arrangement of front layer alignment mark.
Optionally, the deformation buffer area includes two lateral sub-deformation buffer areas parallel to the first direction and two lateral longitudinal sub-deformation buffer areas parallel to the second direction, and the first direction is perpendicular to the second direction.
Optionally, each side of the deformation buffer area includes at least two sub-deformation buffer areas.
Optionally, the shape buffer region is a groove or a hole.
Optionally, the material of the current layer alignment mark is photoresist.
Optionally, the pattern of the overlay alignment mark includes one or a combination of an inner and outer strip shape, an inner and outer box shape, and an advanced image measurement type.
The utility model also provides a mask plate subassembly for form the alignment mark of alignment mark, include, first mask plate includes front alignment mark figure and deformation buffer zone figure, deformation buffer zone figure is located around the front alignment mark figure outside.
Optionally, the deformation buffer area pattern includes a lateral sub-deformation buffer area pattern on two sides parallel to the first direction and a longitudinal sub-deformation buffer area pattern on two sides parallel to the second direction, and the first direction is perpendicular to the second direction.
Optionally, each side of the deformation buffer area graph includes at least two sub-deformation buffer area graphs.
Optionally, the mask plate assembly further includes a second mask plate, and the second mask plate includes a current layer alignment mark pattern.
The utility model provides a pair of alignment mark and mask plate subassembly are carved to overlay sets up the deformation buffer all around through the outside at front layer alignment mark, when the wafer passes through thermal treatment process, the deformation buffer is as the buffer, can reduce the thermal energy deformation of front layer alignment mark to the overlay mark that can solve the yellow light volume time measurement front layer produces deformation and leads to the problem of measurationing the distortion.
Drawings
Fig. 1 is a schematic structural diagram of an overlay alignment mark according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a first mask plate according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a second mask plate according to an embodiment of the present invention;
in the figure, the position of the upper end of the main shaft,
10-alignment mark alignment; 11-front layer alignment mark; 12-a deformation cache area; 13-current layer alignment mark; 20-a first mask plate; 21-front layer alignment mark pattern; 22-deformation buffer zone graph; 23-a non-graphic area; 30-a second mask plate; 31-when layer alignment mark pattern; 32-non-graphic area.
Detailed Description
The overlay alignment mark and the mask plate assembly according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.
As used in this specification, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally employed in its sense including "and/or," the terms "a" and "an" are generally employed in their sense including "at least one," the terms "at least two" are generally employed in their sense including "two or more," and the terms "first", "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", "third" may explicitly or implicitly include one or at least two of the features. The specific meanings of the above terms in the present specification can be understood by those of ordinary skill in the art as appropriate.
[ EXAMPLES one ]
Fig. 1 is a schematic structural diagram of an alignment mark for overlay according to an embodiment of the present invention, as shown in fig. 1, the present invention provides an alignment mark for overlay 10, including: front alignment mark 11, deformation buffer 12 and current layer alignment mark 13, front alignment mark 11 with deformation buffer 12 is in same front layer material, deformation buffer is located the front layer alignment mark 11 outside, current layer alignment mark 13 is located on the front layer material, just current layer alignment mark 13 is located front layer alignment mark 11 is inboard or current layer alignment mark 13 with front layer alignment mark 11 sets up alternately.
Referring to fig. 1, in the present embodiment, the deformation buffer 12 includes two lateral sub-deformation buffers parallel to a first direction and two longitudinal sub-deformation buffers parallel to a second direction, and the first direction is perpendicular to the second direction. Each side of the deformation buffer 12 includes at least two sub-deformation buffers, and in this embodiment, the number of the sub-deformation buffers on each side is, for example, 3.
In this embodiment, the deformation buffer area 12 is a groove or a hole, a plurality of holes are arranged in a row, which is equivalent to a groove, and a plurality of holes can also be arranged in other shapes, so that the design is more flexible and convenient.
In this embodiment, the current layer alignment mark 13 coincides with the center of the previous layer alignment mark 11. The current layer alignment mark is made of photoresist.
The pattern of the overlay alignment mark comprises one or a combination of an inner and outer strip (Bar in Bar), an inner and outer Box (Box in Box) and an advanced image measurement model (AIM). In this embodiment, the pattern of the overlay alignment mark is, for example, an AIM (Advanced Imaging Metrology) pattern, as shown in fig. 1, the current layer alignment mark 13 and the front layer alignment mark 11 are alternately arranged, the current layer alignment mark 13 and the front layer alignment mark 11 are rectangular grooves or protrusions with the same shape and number, the front layer alignment mark 11 is divided into four parts, the first part is 6 rectangular grooves or protrusions arranged in parallel, the first part may also be 7 or more rectangles, which is not limited in this embodiment; the first portion of the front layer alignment mark 11 and the second portion and the third portion adjacent to the first portion are vertically disposed, the first portion of the front layer alignment mark 11 and the fourth portion not adjacent to the first portion are disposed in parallel, similarly, the current layer alignment mark 13 is also divided into four portions, the first portion is 6 parallel rectangular grooves or protrusions, the first portion may also be 7 or more rectangles, which is not limited in this embodiment; the first portion of the current-layer alignment mark 13 and the second portion and the third portion adjacent to the first portion are vertically arranged, the first portion of the current-layer alignment mark 13 and the fourth portion not adjacent to the first portion are arranged in parallel, the first portion of the current-layer alignment mark 13 and the first portion of the previous-layer alignment mark 11 are arranged in parallel side by side, and the second portion, the third portion and the fourth portion of the current-layer alignment mark 13 are respectively arranged in parallel side by side adjacent to the second portion, the third portion and the fourth portion of the previous-layer alignment mark 11.
Fig. 2 is a schematic structural diagram of a first mask plate according to an embodiment of the present invention; referring to fig. 2, an embodiment of the present invention further provides a mask plate assembly for forming an overlay alignment mark, including a first mask plate 20, where the first mask plate 20 includes a front layer alignment mark pattern 21 and a deformation buffer pattern 22, and the deformation buffer pattern 22 is located around the outer side of the front layer alignment mark pattern 21.
In this embodiment, the front layer alignment mark pattern 21 is divided into four portions, the first portion is 6 rectangles arranged in parallel, and the first portion may also be 7 or more rectangles, which is not limited in this embodiment; the first portion of the front layer alignment mark pattern 21 and the second and third portions adjacent thereto are vertically disposed, and the first portion of the front layer alignment mark pattern 21 and the fourth portion not adjacent thereto are disposed in parallel.
In this embodiment, the deformation buffer graphics 22 include two lateral sub-deformation buffer graphics parallel to the first direction and two lateral longitudinal sub-deformation buffer graphics parallel to the second direction, and the first direction is perpendicular to the second direction. Each side of the deformation buffer area graph 22 includes at least two sub-deformation buffer area graphs, and in this embodiment, the number of the sub-deformation buffer area graphs on each side is, for example, 3.
In this embodiment, when the front layer alignment mark 11 is a rectangular groove, the front layer alignment mark pattern 21 and the deformation buffer region pattern 22 are transmissive regions, and the non-pattern region 23 is a blocking region. When the front layer alignment mark 11 is a rectangular protrusion, the front layer alignment mark pattern 21 and the deformation buffer region pattern 22 are shielding regions, and the non-pattern region 23 is a transmission region.
Fig. 3 is a schematic structural diagram of a second mask plate according to an embodiment of the present invention; referring to fig. 3, the mask plate assembly further includes a second mask plate 30, and the second mask plate 30 includes a current layer alignment mark pattern 31.
In this embodiment, the layer-specific alignment mark pattern 31 is divided into four portions, the first portion is 6 rectangles arranged in parallel, and the first portion may also be 7 or more rectangles, which is not limited in this embodiment; the first portion of the current-layer alignment mark pattern 31 and the second and third portions adjacent thereto are vertically disposed, and the first portion of the current-layer alignment mark pattern 31 and the fourth portion not adjacent thereto are disposed in parallel.
In this embodiment, when the layer alignment mark 12 is a rectangular groove, the layer alignment mark pattern 31 is a transmissive region, and the non-pattern region 32 is a blocking region. When the current layer alignment mark pattern 31 is a rectangular protrusion, the current layer alignment mark pattern 31 is a shielding region, and the non-pattern region 32 is a projection region.
The embodiment also provides a method for forming an overlay alignment mark, which includes:
step S1: a wafer is provided, the wafer including a front layer material.
In step S1, the wafer may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a Silicon On Insulator (SOI) substrate, a Germanium On Insulator (GOI) substrate, a glass substrate, or other III-V compound substrate, and the material and structure of the wafer are not limited in this embodiment. In addition, a device structure may be formed in the wafer, and the device structure may be a device structure formed in a front-end semiconductor process, such as a MOS transistor.
The wafer is formed with a front layer material, which is a thin film material, such as TEOS.
Step S2: and coating a first photoresist layer on the front layer material, and transferring a front layer alignment mark pattern and a deformation buffer area pattern on the first mask plate to the first photoresist layer through exposure and development so as to define the front layer alignment mark pattern and the deformation buffer area pattern on the first photoresist layer.
Step S3: and forming a front layer alignment mark and a deformation buffer area in the front layer material by using the first photoresist as a mask through an etching process. And forming a front layer alignment mark and deformation buffer areas in the front layer material, wherein the deformation buffer areas are positioned on four sides of the periphery of the front layer mark.
The etching process may be a dry etching process or a wet etching process.
Step S4: and carrying out a heat treatment process on the wafer.
In step S4, the wafer may perform various intermediate process steps such as a thermal oxidation process, an annealing process, a CVD process, a TEOS process, etc. during the two photolithography processes, and the process temperature is greater than 900 ℃, for example, during the thermal treatment process, the thermal treatment process may cause thermal expansion deformation of the front layer material. Because the deformation buffer area is arranged on the periphery of the outer side of the front layer alignment mark, the deformation buffer area can be used as a buffer area when the heat treatment process is carried out, and the deformation of the front layer alignment mark is reduced.
Step S5: and coating a second photoresist layer on the front layer material, and transferring the current layer alignment mark pattern on the second mask plate to the second photoresist layer through exposure and development so as to define the current layer alignment mark pattern on the second photoresist layer.
In step S5, a current layer alignment mark is formed on the front layer material, and the current layer alignment mark is located in the front layer alignment mark or the current layer alignment mark and the front layer alignment mark are alternately arranged. In this embodiment, the current layer alignment mark material is photoresist.
After the current layer alignment mark and the front layer alignment mark are formed, the performance of photoetching current layer alignment precision is confirmed by using the central patterns of the current layer alignment mark and the front layer alignment mark based on the optical diffraction principle, and the diffraction spectrum of the current layer alignment mark and the diffraction spectrum of the front layer alignment mark can be distinguished due to the difference of pattern types and sizes.
The utility model provides a pair of alignment mark and mask plate subassembly are carved to overlay sets up the deformation buffer all around through the outside at front layer alignment mark, when the wafer passes through thermal treatment process, the deformation buffer is as the buffer, can reduce the thermal energy deformation of front layer alignment mark to the overlay mark that can solve the yellow light volume time measurement front layer produces deformation and leads to the problem of measurationing the distortion.
The above description is only for the preferred embodiment of the present invention and is not intended to limit the scope of the present invention, and any modification and modification made by those skilled in the art according to the above disclosure are all within the scope of the claims.
Claims (10)
1. The utility model provides an overlay alignment mark, its characterized in that includes front alignment mark, deformation buffer and when a layer alignment mark, front alignment mark with the deformation buffer is located same front layer material, the deformation buffer is located the front layer alignment mark outside, when a layer alignment mark is located on the front layer material, just when a layer alignment mark is located the front layer alignment mark is inboard or when a layer alignment mark with the staggered arrangement of front layer alignment mark.
2. The overlay alignment mark of claim 1 wherein the deformation buffer comprises two lateral sub-deformation buffers parallel to a first direction and two longitudinal sub-deformation buffers parallel to a second direction, the first direction and the second direction being perpendicular to each other.
3. The overlay alignment mark of claim 1 wherein each side of the deformation buffer comprises at least two sub-deformation buffers.
4. The overlay alignment mark of any of claims 1-3, wherein the deformation buffer is a trench or a hole.
5. The overlay alignment mark of any of claims 1-3, wherein the material of the current layer alignment mark is a photoresist.
6. The overlay alignment mark of any one of claims 1-3, wherein the pattern of the overlay alignment mark comprises one or a combination of inside and outside bars, inside and outside boxes, and advanced image metrology.
7. A mask plate assembly is used for forming an overlay alignment mark and is characterized by comprising a first mask plate, wherein the first mask plate comprises a front layer alignment mark pattern and a deformation cache region pattern, and the deformation cache region pattern is located on the periphery of the outer side of the front layer alignment mark pattern.
8. The reticle assembly of claim 7, wherein the deformation buffer pattern comprises two lateral sub-deformation buffer patterns parallel to a first direction and two longitudinal sub-deformation buffer patterns parallel to a second direction, the first direction and the second direction being perpendicular.
9. The reticle assembly of claim 8, wherein each side of the deformation buffer pattern comprises at least two sub-deformation buffer patterns.
10. The mask plate assembly of claim 7, further comprising a second mask plate comprising a current layer alignment mark pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202120925351.9U CN214623293U (en) | 2021-04-29 | 2021-04-29 | Overlay alignment mark and mask plate assembly |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202120925351.9U CN214623293U (en) | 2021-04-29 | 2021-04-29 | Overlay alignment mark and mask plate assembly |
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| CN214623293U true CN214623293U (en) | 2021-11-05 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114236984A (en) * | 2022-01-13 | 2022-03-25 | 长鑫存储技术有限公司 | Method for manufacturing overlay precision measurement pattern and overlay precision measurement pattern |
| CN114623787A (en) * | 2022-03-10 | 2022-06-14 | 长鑫存储技术有限公司 | Calibration mark for calibrating overlay measurement accuracy, measurement method and calibration method |
| CN117406545A (en) * | 2023-12-14 | 2024-01-16 | 合肥晶合集成电路股份有限公司 | Semiconductor mask and manufacturing method thereof |
-
2021
- 2021-04-29 CN CN202120925351.9U patent/CN214623293U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114236984A (en) * | 2022-01-13 | 2022-03-25 | 长鑫存储技术有限公司 | Method for manufacturing overlay precision measurement pattern and overlay precision measurement pattern |
| CN114623787A (en) * | 2022-03-10 | 2022-06-14 | 长鑫存储技术有限公司 | Calibration mark for calibrating overlay measurement accuracy, measurement method and calibration method |
| CN114623787B (en) * | 2022-03-10 | 2024-05-03 | 长鑫存储技术有限公司 | Calibration mark for calibrating overlay measurement accuracy, measurement method and calibration method |
| CN117406545A (en) * | 2023-12-14 | 2024-01-16 | 合肥晶合集成电路股份有限公司 | Semiconductor mask and manufacturing method thereof |
| CN117406545B (en) * | 2023-12-14 | 2024-03-01 | 合肥晶合集成电路股份有限公司 | Semiconductor mask and manufacturing method thereof |
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