CN114236984A

CN114236984A - Method for manufacturing overlay precision measurement pattern and overlay precision measurement pattern

Info

Publication number: CN114236984A
Application number: CN202210039422.4A
Authority: CN
Inventors: 邱少稳
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-01-13
Filing date: 2022-01-13
Publication date: 2022-03-25

Abstract

The embodiment of the disclosure relates to the field of semiconductors, and provides a manufacturing method of an overlay accuracy measurement graph and the overlay accuracy measurement graph, wherein the manufacturing method of the overlay accuracy measurement graph comprises the following steps: providing a wafer; providing a first photoresist layer, wherein the first photoresist layer is provided with a plurality of initial strip-shaped graphs which are arranged in parallel; patterning the wafer by taking the first photoresist layer as a mask to transfer the initial strip-shaped pattern onto the wafer to form a first target pattern; providing a second photoresist layer, wherein the second photoresist layer is provided with a plurality of first mark patterns and second mark patterns, the first mark patterns extend along a first direction, and the second mark patterns extend along a second direction; after the first target pattern is formed, the first target pattern is patterned by taking the second photoresist layer as a mask to form a second target pattern, so that the pattern precision of the overlay precision measurement pattern can be improved.

Description

Method for manufacturing overlay precision measurement pattern and overlay precision measurement pattern

Technical Field

The embodiment of the disclosure relates to the field of semiconductors, in particular to a manufacturing method of an overlay accuracy measurement graph and the overlay accuracy measurement graph.

Background

The development of semiconductor technology is generally limited to the development of photolithography, which is a process of transferring a mask pattern onto a wafer through a series of steps such as alignment and exposure, and the reduction of feature size imposes a stricter requirement on the alignment precision of a silicon wafer. If the overlay accuracy between the photo-etching layers does not meet the requirement of the design criteria, the failure of the function of the front-end device and the function of the back-end connecting line can be caused, and the loss of the product yield is directly caused.

In the fabrication of integrated circuits, the relative position between patterns on a wafer is typically measured using specialized equipment to determine overlay errors. The pattern on the wafer that is specifically used to measure overlay error is referred to as an overlay mark.

However, the existing overlay mark has the problem of abnormal pattern.

Disclosure of Invention

The embodiment of the disclosure provides a manufacturing method of an overlay accuracy measurement pattern and the overlay accuracy measurement pattern, which can at least improve the pattern accuracy of the overlay accuracy measurement pattern.

According to some embodiments of the present disclosure, in one aspect, the present disclosure provides a method for manufacturing an overlay accuracy measurement pattern, including: providing a wafer; providing a first photoresist layer, wherein the first photoresist layer is provided with a plurality of initial strip-shaped graphs which are arranged in parallel; patterning the wafer by taking the first photoresist layer as a mask to transfer the initial strip-shaped pattern onto the wafer to form a first target pattern; providing a second photoresist layer, wherein the second photoresist layer is provided with a plurality of first mark patterns and second mark patterns, the first mark patterns extend along a first direction, and the second mark patterns extend along a second direction; and after the first target pattern is formed, patterning the first target pattern by taking the second photoresist layer as a mask to form a second target pattern.

In some embodiments, the gaps between adjacent initial stripe patterns are equal in the arrangement direction along the initial stripe patterns.

In some embodiments, the number of the initial stripe patterns is greater than or equal to 6.

In some embodiments, an orthographic projection pattern of the initial stripe pattern on the surface of the wafer is rectangular, and an extending direction of the initial stripe pattern is perpendicular to an arrangement direction of the initial stripe pattern.

In some embodiments, the extending direction of the initial stripe patterns is the same as the first direction, and the arrangement direction of the plurality of initial stripe patterns is the same as the second direction.

In some embodiments, the extending direction of the initial stripe patterns is inclined with respect to the first direction, and the arrangement direction of the plurality of initial stripe patterns is inclined with respect to the second direction.

In some embodiments, the wafer includes a first grating area, a second grating area, a third grating area, and a fourth grating area, which are sequentially arranged clockwise; the method for forming the second target pattern comprises the following steps: and taking the second photoresist layer as a mask, cutting off the first target graphs of the first grating area and the third grating area along the first direction, and cutting off the first target graphs of the second grating area and the fourth grating area along the second direction to form the second target graph.

In some embodiments, the extending direction of the initial stripe patterns is inclined to the first direction by an angle in a range of 0 to 45 °, and the arrangement direction of the plurality of initial stripe patterns is inclined to the second direction by an angle in a range of 0 to 45 °.

And the orthographic projection graph of the initial strip graph on the surface of the wafer is in an annular runway shape.

In some embodiments, the second photoresist layer has a center point, and the first mark pattern and the second mark pattern are centrosymmetric along the center point.

In some embodiments, the second photoresist layer has a first grating unit, a second grating unit, a third grating unit and a fourth grating unit distributed clockwise around the central point, the first grating unit and the third grating unit are formed by a plurality of first mark patterns arranged at intervals, and the second grating unit and the fourth grating unit are formed by a plurality of second mark patterns arranged at intervals.

In some embodiments, the method of forming the second target pattern comprises: filling the first target pattern to form a flat area; and patterning the flat area by taking the second photoresist layer as a mask so as to transfer the first mark pattern and the second mark pattern to the flat area to form a second target pattern.

In some embodiments, the wafer includes functional regions and scribe line regions, the scribe line regions are located between adjacent functional regions, and the first target pattern and the second target pattern are formed in the scribe line regions.

In some embodiments, the first target pattern and the second target pattern are both bar patterns.

According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides an overlay accuracy measurement pattern, which is manufactured by the above method for manufacturing an overlay accuracy measurement pattern.

The technical scheme provided by the embodiment of the disclosure has at least the following advantages: the method for forming the second target graph by transferring the first photoresist layer with the plurality of initial strip graphs which are arranged in parallel to the wafer is favorable for improving the graph precision of the second target graph and etching the wafer with the first target graph by taking the second photoresist layer graph with the first mark graph and the second mark graph as a mask, and the total area of single etching or the etching graph density of single etching can be reduced by patterning for multiple times, so that the load effect in the etching process is reduced, and the graph precision of the overlay precision measurement graph is improved.

Drawings

One or more embodiments are illustrated by corresponding figures in the drawings, which are not to be construed as limiting the embodiments, unless expressly stated otherwise, the drawings are not to scale; in order to more clearly illustrate the embodiments of the present disclosure or technical solutions in the conventional art, the drawings required to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a flowchart illustrating a method for manufacturing an overlay accuracy measurement pattern according to an embodiment of the present disclosure;

fig. 2 to 5 are schematic structural diagrams corresponding to steps of a method for manufacturing an overlay accuracy measurement pattern according to an embodiment of the present disclosure;

fig. 6 to 9 are schematic structural diagrams corresponding to steps of a method for manufacturing an overlay accuracy measurement pattern according to another embodiment of the present disclosure;

fig. 10 to 13 are schematic structural diagrams corresponding to steps of a method for manufacturing an overlay accuracy measurement pattern according to yet another embodiment of the present disclosure.

Detailed Description

It can be known from the background art that, along with the continuous miniaturization of the integration level, the size of the corresponding overlay mark is also smaller and smaller, so that the density of the adjacent strip patterns in the overlay mark is relatively increased, and the etching load effect caused by the relative increase of the density of the strip patterns causes the deformation of the two ends of the strip patterns, which causes the abnormity of the finally formed overlay mark, thereby affecting the measurement of the overlay error.

The embodiment of the disclosure provides a manufacturing method of an overlay accuracy measurement graph, which comprises the steps of transferring an initial strip graph of a first photoresist layer onto a wafer to form a first target graph, patterning the first target graph by taking a first mark graph and a second mark graph of a second photoresist layer as masks to form a second target graph, and transferring the initial strip graph of the first photoresist layer, the first mark graph of the second photoresist layer and the second mark graph onto the wafer in sequence to reduce the total area of single etching or the density of etching graphs of the single etching, so that the graph accuracy of the overlay accuracy measurement graph is improved by reducing the load effect in the etching process, and a good process basis is further provided for subsequent overlay errors.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the embodiments of the disclosure, numerous technical details are set forth in order to provide a better understanding of the embodiments of the disclosure. However, the claimed embodiments of the present disclosure may be practiced without these specific details or with various changes and modifications based on the following embodiments.

Referring to fig. 1, fig. 1 is a flowchart illustrating a method for manufacturing an overlay accuracy measurement pattern according to an embodiment of the present disclosure.

In some embodiments, the method for manufacturing the overlay accuracy measurement pattern may include the following steps:

step S11: a wafer is provided.

The wafer refers to a silicon wafer used for manufacturing a silicon semiconductor integrated circuit, and is called a wafer because the shape is generally set to be circular; various circuit element structures can be fabricated on a silicon wafer, and thus, an integrated circuit product with specific electrical functions is called.

In some embodiments, the wafer may also be a germanium wafer, a gallium arsenide wafer, or a gallium nitride wafer, and the material of the wafer is not limited in the embodiments of the present disclosure, and a wafer of a suitable material may be selected according to actual requirements.

Step S12: providing a first photoresist layer, wherein the first photoresist layer is provided with a plurality of initial strip-shaped graphs which are arranged in parallel.

In some embodiments, using a photomask with a hollow area, the first initial photoresist layer is selectively exposed to light radiation, and the exposed first initial photoresist layer is baked at a high temperature to crack the exposed part of the first initial photoresist layer; then moving the cracked first initial photoresist layer to a developing tank, wherein the exposed first initial photoresist layer can be removed because the exposed part of the first initial photoresist layer can be dissolved in a developing solution; thus, a patterned first photoresist layer, i.e., a first photoresist layer having a plurality of initial stripe patterns arranged in parallel, can be obtained.

In some embodiments, the first initial photoresist layer is comprised of a positive photoresist, the exposed regions of the positive photoresist being developed away; in other embodiments, the first initial photoresist layer is comprised of a negative photoresist and the unexposed areas of the negative photoresist are developed away.

Step S13: in some embodiments, the wafer may be patterned with the first photoresist layer as a mask to transfer the initial stripe pattern onto the wafer to form a first target pattern. Specifically, taking the wafer as a silicon wafer as an example, the first target pattern may be formed on the wafer by forming the first photoresist layer on the surface of the wafer and etching a part of the wafer uncovered by the first photoresist layer through dry etching.

Step S14: and providing a second photoresist layer, wherein the second photoresist layer is provided with a plurality of first mark patterns and second mark patterns, the first mark patterns extend along the first direction, and the second mark patterns extend along the second direction.

In some embodiments, the second photoresist layer is formed by forming a protective layer on the second initial photoresist layer, selectively exposing the second initial photoresist layer, and baking the exposed second initial photoresist layer at a high temperature to crack the exposed portions of the second initial photoresist layer; then moving the cracked second initial photoresist layer to a developing tank, wherein the exposed part of the second initial photoresist layer can be removed because the exposed part of the second initial photoresist layer can be dissolved in a developing solution; thus, a patterned second photoresist layer, i.e., a second photoresist layer having a plurality of first mark patterns and second mark patterns, can be obtained.

Step S15: in some embodiments, after the first target pattern is formed, the first target pattern is patterned by using the second photoresist layer as a mask to form a second target pattern. In some embodiments, the second target pattern is formed by etching a portion of the first target pattern, so that the second target pattern can be formed by forming a second photoresist layer on the surface of the first target pattern, and etching the first target pattern by using the second photoresist layer as a mask to transfer the plurality of first mark patterns and the plurality of second mark patterns onto the first target pattern.

In some embodiments, the second target pattern may be formed by dry etching, and the plasma used for dry etching may be the same as the plasma used for forming the first target pattern.

The method for forming the second target pattern by transferring the first photoresist layer with the plurality of initial strip patterns which are arranged in parallel to the wafer is favorable for improving the pattern precision of the second target pattern by using the second photoresist layer with the first mark pattern and the second mark pattern as a mask to etch the wafer with the first target pattern, and the total area of single etching or the etching pattern density of single etching can be reduced by patterning for multiple times, so that the load effect in the etching process is reduced, and the pattern precision of the overlay precision measurement pattern is improved.

The following describes a method for manufacturing an overlay accuracy measurement pattern according to an embodiment of the present disclosure in more detail with reference to the accompanying drawings.

Referring to fig. 2 to 5, schematic structural diagrams corresponding to steps of a method for manufacturing an overlay accuracy measurement pattern according to an embodiment of the present disclosure are shown.

Referring to fig. 2, fig. 2 is a schematic top view of a first photoresist layer, providing a wafer (not shown) and a first photoresist layer 100, where the first photoresist layer 100 includes a plurality of initial stripe patterns 110 arranged in parallel.

In some embodiments, the gaps between adjacent initial bar patterns 110 may be equal in the arrangement direction along the initial bar patterns 110, the plurality of initial bar patterns 110 with equal gaps is favorable for subsequent measurement of overlay errors, and the plurality of initial bar patterns 110 with equal gaps may reduce measurement errors caused by different gaps between the initial bar patterns 110. In other embodiments, the gaps between adjacent initial stripe patterns 110 may also be different, and the distance between adjacent initial stripe patterns may be adjusted according to actual requirements.

In some embodiments, the gap between the initial stripe patterns 110 may be 0.1 to 10 μm, and it can be understood that, if the gap between the adjacent initial stripe patterns 110 is smaller than 0.1 μm, the process of forming the first photoresist layer 100 is not easy to be implemented, and the initial stripe patterns 110 with too small a gap are also not beneficial to the subsequent measurement of overlay error; if the gap between adjacent initial stripe patterns 110 is larger than 10 μm, the finally formed second target pattern is too large, which may reduce the area of the functional region on the wafer, and is not favorable for forming the integrated circuit on the wafer subsequently. The gap between the initial bar patterns 110 may be adjusted according to actual requirements, and the embodiment of the disclosure does not limit the gap between the initial bar patterns 110.

In some embodiments, the number of the initial bar patterns 110 may be greater than or equal to 6, such as 6, 9, or 10, etc.

It can be understood that, under the condition that the length and the width of the initial stripe pattern 110 are fixed, the larger the number of the initial stripe patterns 110 is, the larger the corresponding first target pattern to be subsequently formed is, the volume of the first target pattern to be subsequently formed can be controlled by controlling the number of the initial stripe patterns 110, when the number of the initial stripe patterns 110 is less than 6, the volume of the first target pattern to be formed may be smaller, which is not favorable for the subsequent patterning of the first target pattern to form the second target pattern, and the contingency of the subsequent overlay error measurement can be reduced by setting the number of the initial stripe patterns 110 to be greater than or equal to 6, and the contingency of the subsequent overlay error measurement can be improved by testing a plurality of different second target patterns formed by using the initial stripe patterns 110 as a mask.

In other embodiments, the number of the initial stripe patterns 110 may also be less than 6, and the number of the initial stripe patterns 110 may be adjusted according to actual requirements, and the number of the initial stripe patterns 110 is not limited in the embodiments of the disclosure.

In some embodiments, the orthographic projection of the initial stripe pattern 110 on the wafer surface is a rectangle, and the extending direction of the initial stripe pattern 110 may be perpendicular to the arrangement direction of the initial stripe pattern 110.

The initial strip-shaped graph 110 is set to be rectangular, so that the alignment error can be conveniently measured subsequently, the error between one side of the rectangle can be directly compared when the alignment error is measured, misjudgment is not easy to occur, the alignment error can be measured from different directions, and the reliability of the data of the alignment error is improved subsequently.

In some embodiments, the extending direction of the initial stripe patterns 110 may be the same as the first direction X, and the arrangement direction of the plurality of initial stripe patterns 110 is the same as the second direction Y.

In some embodiments, by controlling the extending direction of the initial stripe pattern 110 to be the same as the first direction X and the arrangement direction to be the same as the second direction Y, that is, the extending direction of the initial stripe pattern 110 is the same as the extending direction of the first mark pattern, and the arrangement direction of the initial stripe pattern 110 is the same as the extending direction of the second mark pattern, a process basis is provided for subsequently forming the second target pattern.

In some embodiments, the extending direction of the initial stripe pattern may be different from the first direction, the arrangement direction of the initial stripe pattern may be different from the second direction, and the extending direction and the arrangement direction of the initial stripe pattern may be adjusted according to a pattern shape of the second target pattern to be formed.

In other embodiments, the orthographic projection of the initial stripe pattern 110 on the wafer surface may also be a circular track type, wherein two ends of the circular track type are relatively smooth, so that the process stability is better when the initial stripe pattern 110 is formed.

In still other embodiments, the orthographic projection of the initial stripe pattern on the wafer surface may be other patterns, and the shape of the initial stripe pattern may be adjusted according to actual requirements without limitation to the shape of the initial stripe pattern in the embodiments of the present disclosure.

Referring to fig. 3, a first target pattern 160 is formed on a wafer 150.

The wafer 150 is etched using the first photoresist layer 100 (refer to fig. 1) as a mask, in some embodiments, a portion of the wafer 150 covered by the initial stripe pattern 110 is protected from etching, and the first target pattern 160 includes the initial stripe pattern 110 and a recessed portion between the initial stripe pattern 110.

In some embodiments, after forming the first target pattern 160, it may further include: the first photoresist layer 100 is removed. Referring to fig. 4 and 5, fig. 4 is a schematic structural diagram of a second photoresist layer according to an embodiment of the disclosure, and fig. 5 is a schematic structural diagram of a wafer including a second target pattern according to an embodiment of the disclosure, in which a second photoresist layer 120 is provided, the second photoresist layer 120 has a plurality of first mark patterns 130 and second mark patterns 140, the first mark patterns 130 extend along a first direction X, and the second mark patterns 140 extend along a second direction Y.

In some embodiments, the second photoresist layer 120 has a center point, and the first mark pattern 130 and the second mark pattern 140 may be centered symmetrically along the center point.

The alignment group may be set in subsequent measurement of overlay error by disposing the first and

second mark patterns

130 and 140 to be centrosymmetric along the second photoresist layer 120, and reliability of measurement data may be improved by separately measuring centrosymmetric patterns.

In some embodiments, the second photoresist layer 120 has a first grating unit 121, a second grating unit 122, a third grating unit 123 and a fourth grating unit 124 distributed clockwise around a central point, where the first grating unit 121 and the third grating unit 123 are both composed of a plurality of first mark patterns 130 arranged at intervals, and the second grating unit 122 and the fourth grating unit 124 are both composed of a plurality of second mark patterns 140 arranged at intervals.

The first and third

grating units

121 and 123 may include the same number of first mark patterns 130; the number of the second mark patterns 140 included in the second grating unit 122 and the fourth grating unit 124 may be the same, that is, the patterns of the first grating unit 121 and the third grating unit 123 may be completely the same, so that in the subsequent process of measuring overlay errors, the test parameters of the area corresponding to the first grating unit 121 may be compared with the test data of the area corresponding to the third grating unit 123, thereby facilitating subsequent error analysis and adjustment, and similarly, the second grating unit 122 and the fourth grating unit 124 are set to be the same, and the test data of the second grating unit 122 and the fourth grating unit 124 may also be compared, thereby facilitating subsequent error analysis and adjustment.

In some embodiments, the wafer 150 may include a first grating region 151, a second grating region 152, a third grating region 153, and a fourth grating region 154 arranged in sequence clockwise; the method of forming the second target pattern 170 includes: the second photoresist layer 120 is used as a mask to perform a cutting process on the first target patterns 160 (refer to fig. 2) of the first grating region 151 and the third grating region 153 along the first direction X, and perform a cutting process on the first target patterns 160 of the second grating region 152 and the fourth grating region 154 along the second direction Y to form the second target patterns 170.

In some embodiments, a gap exists between every two first mark patterns 130 in the first grating unit 121 and the third grating unit 123, when the wafer 150 is etched by using the second photoresist layer 120 as a mask, the gap space cuts off the first target pattern 160 (refer to fig. 2), and a gap exists between the second mark patterns 140 of the second grating unit 122 and the fourth grating unit 124, so that when the wafer 150 is etched by using the second photoresist layer 120 as a mask, the gap space cuts off the first target pattern 160 (refer to fig. 2) to form the second target pattern 170.

In some embodiments, there may be a gap between every three first mark patterns 130 in the first grating unit 121 and the third grating unit 123, and the gap between the first grating unit 121 and the third grating unit 123 may be adjusted according to actual requirements.

In some embodiments, the wafer 150 includes functional regions and scribe line regions, and the first target pattern 160 (refer to fig. 2) and the second target pattern 170 may be formed in the scribe line regions between adjacent functional regions.

The functional area, i.e., the area where the wafer 150 is used to form the integrated circuit, and the scribe lane area, i.e., the area where the wafer 150 is diced into chips, it is understood that the second target pattern 170 is usually a pattern for measuring overlay error, and does not have other functions, and forming the second target pattern 170 in the scribe lane area can prevent the second target pattern 170 from occupying a part of the functional area, thereby improving the utilization rate of the wafer 150.

In some embodiments, the first target patterns 160 (refer to fig. 3) and the second target patterns 170 may be both stripe patterns, and it is understood that the first photoresist layer 100 (refer to fig. 3) includes a plurality of initial stripe patterns 110 (refer to fig. 3) arranged in parallel, so that the first target patterns 160 formed by patterning the wafer 150 using the first photoresist layer 100 as a mask are stripe patterns, the first mark patterns 130 and the second mark patterns 140 of the second photoresist layer 120 are stripe patterns, and the second target patterns 170 formed by patterning the first target patterns 160 using the second photoresist layer 120 as a mask are also stripe patterns. The formation of the first target pattern 160 and the second target pattern 170 in a stripe pattern facilitates the subsequent measurement of the second target pattern 170.

In the embodiment of the disclosure, the initial stripe pattern 110 of the first photoresist layer 100 and the first mark pattern 130 and the second mark pattern 140 of the second photoresist layer 120 are sequentially transferred onto the wafer to form the second target pattern 170, and the method of forming the patterns in a graded manner can reduce the load effect in the etching process, thereby improving the pattern accuracy of the overlay accuracy measurement pattern.

Another embodiment of the present disclosure further provides a method for manufacturing an overlay accuracy measurement pattern, which is substantially the same as the embodiment shown in fig. 2 to 5, and the main differences include: the first mark pattern and the second mark pattern of the second photoresist layer are different, and a method for manufacturing an overlay accuracy measurement pattern according to another embodiment of the present disclosure will be described below with reference to the accompanying drawings, where it is to be noted that the same or corresponding portions in the foregoing embodiments may refer to corresponding descriptions in the foregoing embodiments, and further description will not be repeated below.

Referring to fig. 6 to 9, fig. 6 to 9 are schematic structural diagrams corresponding to steps of a method for manufacturing an overlay accuracy measurement pattern according to another embodiment of the present disclosure.

Specifically, referring to fig. 6, fig. 6 is a schematic structural diagram of a first photoresist layer according to an embodiment of the disclosure, and referring to fig. 7, fig. 7 is a schematic structural diagram of a wafer including a first target pattern according to an embodiment of the disclosure; referring to fig. 6 and 7, a wafer 250 is provided, and an initial stripe pattern 210 of a first photoresist layer 200 is transferred onto the wafer 250 to form a first target pattern 260.

Referring to fig. 8, a second photoresist layer 220 is provided, the second photoresist layer 220 having a plurality of first mark patterns 230 and second mark patterns 240, the first mark patterns 230 extending along a first direction, and the second mark patterns 240 extending along a second direction Y.

In some embodiments, the second photoresist layer 220 may include a first grating unit 221, a second grating unit 222, a third grating unit 223, and a fourth grating unit 224 which are distributed clockwise around the center point, and the second mark patterns 240 of the second grating unit 222 and the fourth grating unit 224 are continuous stripe patterns, the intervals between the first mark patterns 230 of the first grating unit 221 and the third grating unit 223 are equal, and the intervals between the first mark patterns 230 are equal to the intervals between the initial stripe patterns 210 (refer to fig. 7) of the first photoresist layer 200 (refer to fig. 7).

Referring to fig. 9, the adjacent first target pattern 260 is filled to form a flat region 280; the planarization region 280 is patterned using the second photoresist layer 220 as a mask to transfer the first mark pattern 230 and the second mark pattern 240 to the planarization region 280 to form the second target pattern 270.

The gap between the first target patterns 260 is filled to form the flat region 280, the second photoresist layer 220 is formed on the flat region 280, the flat region 280 is etched by using the second photoresist layer 220 as a mask to form the second target pattern 270, and the etching load effect during the formation of the second target pattern 270 can be reduced by forming the flat region 280 and then forming the second target pattern 270, thereby improving the pattern accuracy of forming the second target pattern 270.

It can be understood that, since the first photoresist layer is used as a mask to etch the wafer during the process of forming the first target pattern, if the flat region is not formed, the first target pattern is directly patterned, a portion of the wafer is etched twice, which results in an excessively high height difference between the top surface and the bottom surface of the second target pattern, and an excessively high height difference of the second target pattern results in an insufficient pattern stability of the second target pattern.

In some embodiments, the first target pattern may be etched directly using the second photoresist layer as a mask to form a second target pattern without forming the planarization region. In the embodiment of the present disclosure, before forming the second target pattern 270, a portion of the adjacent first target pattern 260 is filled to form a flat region 280, and then the flat region 280 is patterned to form the second target pattern 270, so that the height difference of the second target pattern 270 can be reduced by forming the flat region 280 and then forming the second target pattern 270, thereby improving the stability of the target pattern 270, and the etching load effect of forming the target pattern at a time can be reduced by forming the first target pattern 260 and the second target pattern 270 at different times, thereby improving the pattern accuracy of the formed overlay accuracy measurement pattern.

Another embodiment of the present disclosure further provides a method for manufacturing an overlay accuracy measurement pattern, which is substantially the same as the embodiment provided in fig. 2 to 5, and the main differences include: the extending directions of the initial stripe patterns of the first photoresist layer are different, and a method for manufacturing an overlay accuracy measurement pattern according to another embodiment of the present disclosure will be described below with reference to the accompanying drawings, where it is to be noted that the same or corresponding portions in the foregoing embodiments may refer to corresponding descriptions in the foregoing embodiments, and further description will not be repeated below.

Referring to fig. 10, fig. 10 is a schematic structural view of a first photoresist layer according to an embodiment of the disclosure, referring to fig. 11, fig. 11 is a schematic structural view of a wafer having a first target pattern according to an embodiment of the disclosure, referring to fig. 10 and fig. 11, a wafer 350 is provided, and an initial stripe pattern 310 of the first photoresist layer 300 is transferred onto the wafer 350 to form a first target pattern 360. Specifically, in some embodiments, the extending direction of the initial stripe patterns 310 may be inclined with respect to the first direction X, and the arrangement direction of the plurality of initial stripe patterns 310 may be inclined with respect to the second direction Y.

By setting the extending direction of the initial stripe pattern 310 to be different from the first direction X, the arrangement direction of the initial stripe pattern 310 is different from the second direction Y, so that the diversity of the second target pattern can be improved, and the universality of the second target pattern can be improved.

In some embodiments, the extending direction of the initial stripe patterns 310 is inclined to the first direction X by an angle in the range of 0 to 45 °, and the arrangement direction of the plurality of initial stripe patterns 310 is inclined to the second direction Y by an angle in the range of 0 to 45 °.

By setting the inclined angle of the extending direction of the initial stripe patterns 310 relative to the first direction X to be within the range of 0-45 °, and the inclined angle of the arrangement direction of the plurality of initial stripe patterns 310 and the second direction Y to be within the range of 0-45 °, the offsets of the finally formed second target patterns in the first direction X and the second direction Y can be simultaneously confirmed, so that the time for measuring the overlay error subsequently can be reduced.

The extending direction of the initial stripe pattern 310 may be inclined with respect to the first direction X or inclined with respect to the second direction Y, and the extending direction and the arrangement direction of the initial stripe pattern 310 may be adjusted according to actual production requirements.

The wafer 350 is patterned by using the first photoresist layer 300 as a mask to transfer the initial stripe pattern 310 onto the wafer 350, thereby forming a first target pattern 360.

Referring to fig. 12, fig. 12 is a schematic structural diagram of a second photoresist layer according to an embodiment of the disclosure; referring to fig. 13, fig. 13 is a schematic view illustrating a wafer structure including a second target pattern according to an embodiment of the disclosure; the first target pattern 360 (refer to fig. 11) is patterned using the second photoresist layer 320 as a mask to form a second target pattern 370.

Specifically, the second photoresist layer 320 may include a first grating unit 321, a second grating unit 322, a third grating unit 323, and a fourth grating unit 324 distributed clockwise around the center point.

The wafer 350 may include: a first grating area 351, a second grating area 352, a third grating area 353 and a fourth grating area 354 which are sequentially arranged clockwise; the method of forming the second target pattern 370 includes: the second photoresist layer 320 is used as a mask to perform a cutting process on the first target patterns 360 (refer to fig. 11) of the first grating region 351 and the third grating region 353 along the first direction X, and perform a cutting process on the first target patterns 360 (refer to fig. 11) of the second grating region 352 and the fourth grating region 354 along the second direction Y to form a second target pattern 370.

The first photoresist layer 300 provided in the present disclosure has a plurality of initial stripe patterns 310 whose extending direction is inclined with respect to the first direction X and whose arrangement direction is inclined with respect to the second direction Y, and the wafer 350 is patterned by using the first photoresist layer provided in the present disclosure as a mask, so that the pattern diversity of the second target pattern 370 can be improved, and the versatility of the formed overlay accuracy measurement pattern can be improved.

The embodiment of the disclosure also provides an overlay accuracy measurement pattern, which can be manufactured and formed by adopting all steps or part of the steps of the embodiment.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the embodiments of the present disclosure in practice. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the embodiments of the present disclosure, and it is therefore intended that the scope of the embodiments of the present disclosure be limited only by the terms of the appended claims.

Claims

1. A manufacturing method of overlay accuracy measurement patterns is characterized by comprising the following steps:

providing a wafer;

providing a first photoresist layer, wherein the first photoresist layer is provided with a plurality of initial strip-shaped graphs which are arranged in parallel;

patterning the wafer by taking the first photoresist layer as a mask to transfer the initial strip-shaped pattern onto the wafer to form a first target pattern;

providing a second photoresist layer, wherein the second photoresist layer is provided with a plurality of first mark patterns and second mark patterns, the first mark patterns extend along a first direction, and the second mark patterns extend along a second direction;

and after the first target pattern is formed, patterning the first target pattern by taking the second photoresist layer as a mask to form a second target pattern.

2. The method as claimed in claim 1, wherein gaps between adjacent initial stripe patterns are equal along the arrangement direction of the initial stripe patterns.

3. The method as claimed in claim 1, wherein the number of the initial stripe patterns is greater than or equal to 6.

4. The method as claimed in claim 1, wherein an orthogonal projection pattern of the initial stripe pattern on the wafer surface is rectangular, and an extending direction of the initial stripe pattern is perpendicular to an arrangement direction of the initial stripe pattern.

5. The method as claimed in claim 4, wherein an extending direction of the initial stripe patterns is the same as the first direction, and an arrangement direction of the plurality of initial stripe patterns is the same as the second direction.

6. The method as claimed in claim 4, wherein an extending direction of the initial stripe pattern is inclined with respect to the first direction, and an arrangement direction of the plurality of initial stripe patterns is inclined with respect to the second direction.

7. The method for manufacturing an overlay accuracy measurement pattern according to claim 5 or 6, wherein the wafer includes a first grating region, a second grating region, a third grating region and a fourth grating region, which are sequentially arranged clockwise; the method for forming the second target pattern comprises the following steps:

and taking the second photoresist layer as a mask, cutting off the first target graphs of the first grating area and the third grating area along the first direction, and cutting off the first target graphs of the second grating area and the fourth grating area along the second direction to form the second target graph.

8. The method as claimed in claim 6, wherein an angle between an extending direction of the initial stripe patterns and an inclination of the first direction is in a range of 0-45 °, and an angle between an arrangement direction of the initial stripe patterns and the inclination of the second direction is in a range of 0-45 °.

9. The method as claimed in claim 1, wherein an orthogonal projection pattern of the initial stripe pattern on the wafer surface is a circular track pattern.

10. The method as claimed in claim 1, wherein the second photoresist layer has a center point, and the first mark pattern and the second mark pattern are symmetric with respect to the center point.

11. The method as claimed in claim 10, wherein the second photoresist layer has a first grating unit, a second grating unit, a third grating unit and a fourth grating unit distributed clockwise around the central point, the first grating unit and the third grating unit are formed by a plurality of first mark patterns arranged at intervals, and the second grating unit and the fourth grating unit are formed by a plurality of second mark patterns arranged at intervals.

12. The method as claimed in claim 1, wherein the step of forming the second target pattern comprises:

filling the first target pattern to form a flat area;

and patterning the flat area by taking the second photoresist layer as a mask so as to transfer the first mark pattern and the second mark pattern to the flat area to form a second target pattern.

13. The method as claimed in claim 1, wherein the wafer includes functional regions and scribe line regions, the scribe line regions are located between adjacent functional regions, and the first target pattern and the second target pattern are formed in the scribe line regions.

14. The method as claimed in claim 1, wherein the first target pattern and the second target pattern are stripe patterns.

15. An overlay accuracy measurement pattern manufactured by the manufacturing method according to any one of claims 1 to 14.