CN117673042A - Alignment mark structure, semiconductor device and preparation method thereof - Google Patents

Abstract

The embodiment of the disclosure provides an alignment mark structure, a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. The alignment mark structure is formed in a cutting channel region of the semiconductor device and comprises an alignment mark and a dummy alignment mark; the dummy alignment mark is arranged on the outer side of the alignment mark and is arranged at intervals with the alignment mark. The present disclosure increases pattern density trenches within a scribe line region by disposing a dummy alignment mark on the outside of the overlay alignment mark, the dummy alignment mark being spaced apart from the overlay alignment mark. When the alignment mark structure is formed, mask materials used for filling the grooves in the cutting channel region can be added to ensure that the top surface of the mask material layer above the cutting channel region is flush with the top surface of the mask material layer above the chip region, thereby ensuring the integrity of the alignment mark structure.

Description

Alignment mark structure, semiconductor device and preparation method thereof

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to an alignment mark structure for alignment, a semiconductor device and a preparation method thereof.

Background

In semiconductor manufacturing, photolithography processes are important circuit pattern transfer processes. Photolithography is a process in which a pattern on a Mask (Mask) is transferred onto a wafer by exposure and development. And the basic measurement index of the photoetching technology is overlay accuracy (OVL), and the overlay accuracy ensures the alignment degree between various lines of different layers. Precisely, if the alignment accuracy between the front layer and the front layer exceeds the tolerance of error, the inter-layer design circuit may be broken or shorted, thereby affecting the yield of the semiconductor structure.

The wafer typically includes a plurality of semiconductor chips and scribe line regions separating the plurality of semiconductor chips. An alignment mark is usually formed in the scribe line region, and the alignment mark pattern in the scribe line region is prone to defects such as incomplete pattern during the manufacturing process, thereby affecting alignment measurement.

Disclosure of Invention

In view of the foregoing, embodiments of the present disclosure provide an overlay alignment mark structure, a semiconductor device and a method for manufacturing the same, for preventing pattern deletion of the overlay alignment mark structure.

A first aspect of an embodiment of the present disclosure provides an overlay alignment mark structure, comprising: the alignment mark structure is formed in the cutting channel region of the semiconductor device and comprises an alignment mark and a dummy alignment mark; the dummy alignment mark is arranged on the outer side of the alignment mark and is arranged at intervals with the alignment mark.

In some embodiments, the alignment mark includes a plurality of sub alignment marks, the plurality of sub alignment marks are disposed at intervals along the annular track, and the sub alignment marks located on a diagonal of the annular track are rotationally symmetrical with respect to a center of the annular track;

the dummy alignment marks comprise a plurality of first dummy alignment marks, and the plurality of first dummy alignment marks and the plurality of sub-alignment marks are arranged in one-to-one correspondence.

In some embodiments, the first dummy alignment mark is disposed at least on one side of the sub-overlay alignment mark.

In some embodiments, the position of one of the adjacent two first dummy alignment marks is not on the same side as the position of the other first dummy alignment mark.

In some embodiments, the first dummy alignment mark comprises a ring structure, the first dummy alignment mark encircling an outer perimeter of the sub-overlay alignment mark.

In some embodiments, the dummy alignment marks further include a second dummy alignment mark for connecting adjacent ones of the first dummy alignment marks.

In some embodiments, the second dummy alignment mark is flush with a side of the first dummy alignment mark facing away from a center of the annular track.

In some embodiments, the dummy alignment mark further comprises a third dummy alignment mark disposed annularly outside the first dummy alignment mark; or the third dummy alignment mark is annularly arranged on the peripheries of the first dummy alignment mark and the second dummy alignment mark.

In some embodiments, the number of the third dummy alignment marks is a plurality, and the plurality of the third dummy alignment marks are arranged at intervals.

In some embodiments, a vertical distance between adjacent ones of the first dummy alignment marks is greater than 6 μm.

In some embodiments, the first dummy alignment mark comprises a first sub dummy alignment mark, a second sub dummy alignment mark, a third sub dummy alignment mark, and a fourth sub dummy alignment mark connected in sequence, the first sub dummy alignment mark and the second sub dummy alignment mark being adjacent to the third dummy alignment mark;

the vertical distance between the first sub dummy alignment mark and the third dummy alignment mark is equal to the vertical distance between the second sub dummy alignment mark and the third dummy alignment mark; and a vertical distance between the first sub dummy alignment mark and the third dummy alignment mark is greater than 800nm.

In some embodiments, the dummy alignment mark is larger in size than the overlay alignment mark in a direction perpendicular to the third dummy alignment mark, and the dummy alignment mark gradually increases in size in a direction away from the center of the annular track.

In some embodiments, the number of the sub-alignment marks is four, the four sub-alignment marks enclose a rectangle, and the four sub-alignment marks are respectively located at the vertices of the rectangle;

in the adjacent two sub-alignment marks, one of the sub-alignment marks comprises a plurality of strip-shaped first alignment marks arranged at intervals, the other sub-alignment mark comprises a plurality of strip-shaped second alignment marks arranged at intervals, and the extending directions of the first alignment marks are mutually perpendicular to the extending directions of the second alignment marks.

A second aspect of an embodiment of the present disclosure provides a semiconductor device, which includes the overlay alignment mark structure of the first aspect.

A third aspect of the embodiments of the present disclosure provides a method for manufacturing a semiconductor device, including the steps of:

providing a substrate, wherein the substrate comprises a chip area and a cutting channel area;

forming an etching barrier layer on the substrate;

forming the alignment mark structure in the first aspect in the scribe line region, and forming a pattern in the chip region, wherein a gap is formed in the alignment mark structure;

forming a first mask layer, wherein the first mask layer covers the pattern on the chip area;

and expanding the gap in the overlay alignment mark structure.

In the alignment mark structure, the semiconductor device and the manufacturing method thereof provided by the embodiment of the disclosure, the dummy alignment mark is arranged at the outer side of the alignment mark, and the dummy alignment mark and the alignment mark are arranged at intervals, so that the pattern density in the dicing channel area is increased. When the conventional SADP technology is adopted to prepare the alignment mark structure, mask materials used for filling the grooves in the cutting channel region can be increased, so that the top surface of the mask material layer above the cutting channel region is flush with the top surface of the mask material layer above the chip region, the integrity of the alignment mark structure is ensured, the test patterns formed in the cutting channel region are prevented from being lost, and the subsequent alignment precision and the accuracy of measuring the performance of the semiconductor device are improved.

In addition to the technical problems, technical features constituting the technical solutions, and beneficial effects brought by the technical features of the technical solutions described above, other technical problems that can be solved by the alignment mark structure, the semiconductor device, and the manufacturing method thereof, other technical features included in the technical solutions, and beneficial effects brought by the technical features provided by the embodiments of the present disclosure are further described in detail in the detailed description.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, a brief description will be given below of the drawings required for the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a diagram of distribution of chip regions and dicing street regions provided by embodiments of the present disclosure;

FIG. 2 is a layout diagram of an overlay alignment mark according to an embodiment of the present disclosure;

fig. 3 to 11 are schematic diagrams of an overlay alignment mark structure according to an embodiment of the disclosure;

fig. 12 is a process flow diagram of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

fig. 13 is a schematic diagram of forming a photoresist layer in a method for manufacturing a semiconductor device according to an embodiment of the disclosure;

fig. 14 is a schematic view of forming a first mandrel in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

fig. 15 is a schematic view of forming a sacrificial layer in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

fig. 16 is a schematic diagram of forming a mask material layer in a method for manufacturing a semiconductor device according to an embodiment of the disclosure;

fig. 17 is a schematic view of forming a second mandrel in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

fig. 18 is a schematic diagram of forming an alignment mark structure in a method for manufacturing a semiconductor device according to an embodiment of the disclosure;

fig. 19 is a schematic view of expanding a gap in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

Reference numerals:

100: a semiconductor device; 110: a chip; 120: cutting the road area; 200: overlay alignment mark structure; 210: overlay alignment marks; 211: sub-overlay alignment marks; 2111: a first alignment mark; 2112: a second alignment mark; 220: a dummy alignment mark; 221: a first dummy alignment mark; 2211: virtually setting an alignment mark on the first sub-mark; 2212: virtually setting an alignment mark on the second sub; 2213: a third sub dummy alignment mark; 2214: a fourth sub dummy alignment mark; 222: a second dummy alignment mark; 222a: a first edge; 222b: a second side; 222c: a third side; 222d: fourth side;

10: a substrate; 20: etching the barrier layer; 30: a material layer; 40: a second mask layer; 41: a first mandrel; 50: a photoresist layer; 60: a sacrificial layer; 70: a mask material layer; 71: a second mandrel; 80: and a first mask layer.

Detailed Description

In the process of manufacturing semiconductor chips, the quality of the photolithographic process directly affects the performance of the final formed chip. The photolithography process is to copy the pattern on the photomask to the wafer coated with photoresist by exposure, and then to etch the pattern on the photomask on the wafer by development, post-baking, electroplating, reflow, and the like.

In the fabrication of integrated circuits (integrated circuit, IC), a complete chip is typically subjected to several tens to twenty times of lithography, which affects the parameters of the lithography process errors, in addition to the resolution of the lithography machine, and also the alignment accuracy. In order to achieve accurate alignment, an alignment mark is formed in the scribe line region of the wafer. In addition, the scribe line region is used to form a test pattern that characterizes the performance of the semiconductor device located within the chip region by detecting the performance of the test pattern.

However, the pattern density in the scribe line region is relatively small and the pattern density in the chip region is relatively large. When the conventional dual Self-alignment process (Self-aligned Double Patterning, referred to as SADP for short) is used to form the alignment mark in the scribe line region, specifically, a mandrel structure is required to be formed on the target layer of the scribe line region at intervals, then a sacrificial layer is formed to encapsulate the mandrel structure, and finally the mask material layer is backfilled. Since the pattern density of the scribe line region and the pattern density of the chip region are different, for example, the number of grooves in the scribe line region is smaller and the number of grooves in the chip region is larger. When the mask material layer is backfilled into the scribe line region and the chip region under the same deposition condition, in view of less mask material used for filling the trench in the scribe line region and more mask material used for filling the trench in the chip region, the top surface of the mask material layer above the scribe line region is higher than the top surface of the mask material layer above the chip region, and then the mask material layer is used as a mask, when the alignment mark is etched by etching the target layer in the scribe line region, the alignment mark cannot be etched effectively, resulting in pattern deletion. Thus, the accuracy of alignment measurement is reduced.

In view of the above technical problems, embodiments of the present disclosure provide an alignment mark structure, a semiconductor device and a method for manufacturing the same, in which a dummy alignment mark is disposed on an outer side of an alignment mark, and the dummy alignment mark and the alignment mark are disposed at intervals, so as to increase the pattern density of an edge region of the alignment mark structure, that is, increase the number of trenches of the alignment mark structure edge in a scribe line region. When the alignment mark structure is prepared by adopting the traditional SADP technology, the height difference between the mask material layer above the cutting channel region and the mask material layer above the chip region can be reduced or even avoided, especially the height difference between the mask material layer at the edge region of the alignment mark structure and the mask material layer at other regions of the alignment mark structure, so that the patterns at the edge region and the non-edge region of the alignment mark structure have uniform etching rates in the process of pattern transfer of the subsequent etching mask material layer, complete etching patterns are obtained, and the subsequent alignment measurement accuracy is ensured.

In order to make the above objects, features and advantages of the embodiments of the present disclosure more comprehensible, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present disclosure. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of the present disclosure.

Referring to fig. 1, an embodiment of the present disclosure provides an overlay alignment mark structure formed in a scribe line region of a semiconductor device. In this embodiment, the semiconductor device 100 may include a wafer. A wafer is a silicon wafer used for manufacturing a silicon semiconductor integrated circuit, and is called a wafer because the wafer is generally circular in shape. A plurality of chips 110 are arranged in an array on the wafer, and the chips 110 are separated from each other by scribe line regions 120.

Various circuit element structures are fabricated in the wafer in regions corresponding to the chips 110, for example, semiconductor structures fabricated on the chips 110 include diodes, transistors, field effect transistors, low power resistors, inductors, capacitors, and the like. After the semiconductor structure on the chip 110 is processed, dicing is performed along the dicing street 120, and each chip 110 is separated from the wafer to form individual chips 110 containing integrated circuits.

It will be appreciated that for simplicity of illustration, scribe line regions 120 are shown in a linear configuration between chips 110. In practice, scribe line regions 120 are configured to have a width and depth such that, after dicing along scribe line regions 120, a regular and uniform shape of chips 110 is formed.

As described above, in order to process the semiconductor structure on the chip 110 of the wafer and test the performance of the chip 110, it is generally necessary to prepare the overlay alignment mark structure and the test pattern for performance measurement in the scribe line region 120.

Referring to fig. 2 to 11, the overlay alignment mark structure 200 includes an overlay alignment mark 210 and a dummy alignment mark 220; the dummy alignment mark 220 is disposed outside the alignment mark 210 and spaced apart from the alignment mark 210. The alignment mark 210 and the dummy alignment mark 220 may be protrusions or grooves disposed in the scribe line region 120.

The dummy alignment marks 220 may be disposed on either side of the overlay alignment marks 210 and spaced apart from the overlay alignment marks 210 to increase the pattern density in the scribe line region 120. It should be noted that, in the present embodiment, the greater the pattern density, the greater the number of grooves defined by the patterns in the scribe line region 120.

When the conventional SADP process is used to prepare the alignment mark structure, the mask material used for filling the trench in the scribe line region 120 can be increased, so as to ensure that the top surface of the mask material layer above the scribe line region is flush with the top surface of the mask material layer above the chip region, thereby ensuring the integrity of the alignment mark structure 200, avoiding the test pattern formed in the scribe line region from being missing, and improving the subsequent alignment precision and the accuracy of measuring the performance of the semiconductor device.

In a possible embodiment, referring to fig. 2, the alignment mark 210 includes a plurality of sub-alignment marks 211, and the plurality of sub-alignment marks 211 are spaced along the circular track. For example, the plurality of sub-alignment marks 211 are arranged at intervals along a circular track or along a regular polygon track.

The sub-registration alignment marks 211 located on the diagonal of the annular track are rotationally symmetric with respect to the center of the annular track. For example, in two sub-alignment marks 211 on one diagonal line, one of the sub-alignment marks 211 coincides with the other sub-alignment mark 211 after rotating 180 ° around the center of the circular track.

Taking the orientation shown in fig. 2 as an example, from left to right, the pattern of the first sub-alignment mark 211 in the first row is rotated 180 ° about the center of the circular track and then matches the pattern of the second sub-alignment mark 211 in the second row. By the arrangement, the preparation of the alignment mark 210 can be facilitated, and the preparation process of the alignment mark 210 can be simplified.

In an example, the number of the sub-alignment marks 211 is four, the four sub-alignment marks 211 enclose a rectangle, and the four sub-alignment marks 211 are respectively located at the vertices of the rectangle.

Among the two adjacent sub-alignment marks 211, one sub-alignment mark includes a plurality of strip-shaped first alignment marks 2111 arranged at intervals, and the other sub-alignment mark includes a plurality of strip-shaped second alignment marks 2112 arranged at intervals, and the extending direction of the first alignment marks 2111 is perpendicular to the extending direction of the second alignment marks 2112.

With continued reference to fig. 1, in view of the array arrangement of the chips 110 on the wafer, and the dicing street regions 120 between adjacent chips 110 extending along the X-axis direction and the Y-axis direction in fig. 1, for convenient and precise alignment of the mask and the wafer, the alignment mark structures 200 are generally disposed along the extension direction of the dicing street regions 120.

The extending direction of the first alignment mark 2111 may be parallel to the X-axis direction, and the extending direction of the second alignment mark 2112 may be parallel to the Y-axis direction, so that the mask is aligned in both the X-axis direction and the Y-axis direction, so that the mask can be accurately positioned.

In the present embodiment, the number of the plurality of first alignment marks 2111 is six, and the six first alignment marks 2111 are arranged parallel to each other and at intervals. The first alignment mark 2111 may be a rectangular groove or a protrusion. Accordingly, the number and shape of the plurality of second alignment marks 2112 may be set in one-to-one correspondence with the number and shape of the plurality of first alignment marks 2111, so that the setting of the alignment mark structure 200 may be facilitated.

Referring to fig. 3, the dummy alignment marks 220 include a plurality of first dummy alignment marks 221, and the plurality of first dummy alignment marks 221 are disposed in one-to-one correspondence with the plurality of sub-alignment marks 211. For example, when the number of the sub-alignment marks 211 is four, the number of the first dummy alignment marks 221 is correspondingly four. A first dummy alignment mark 221 is disposed on one side of a sub-alignment mark 211.

The shape of the first dummy alignment marks 221 may also be trenches or bumps. When the shape of the first dummy alignment mark 221 is a trench, the number of trenches in the scribe line region 120 may be directly increased. When the shape of the first dummy alignment mark 221 is convex, the number of trenches in the scribe line region 120 can be increased by forming a trench between the first dummy alignment mark 221 and the sub-alignment mark 211, and further, when the conventional SADP process is used to prepare the alignment mark structure 200, the mask material used for filling the trench in the scribe line region 120 can be increased to ensure that the top surface of the mask material layer formed above the scribe line region is level with the top surface of the mask material layer formed above the chip region, thereby ensuring the integrity of the alignment mark structure 200, especially the integrity of the pattern in the edge region of the alignment mark structure, and avoiding the adverse effect of the pattern in the edge region of the alignment mark structure on the measurement structure due to the lack of the pattern in the edge region of the alignment mark structure.

In one possible embodiment, the first dummy alignment marks 221 are disposed at least on one side of the sub-overlay alignment marks 211.

Referring to fig. 3 to fig. 6, taking one sub-alignment mark 211 as an example, the number of the first dummy alignment marks 221 corresponding to the sub-alignment mark may be one or at least two.

In an example, please continue with fig. 3 and fig. 4, when the number of the first dummy alignment marks 221 is one, the first dummy alignment marks 221 are disposed at one side of the sub-alignment mark 211. Of the adjacent two first dummy alignment marks 221, the position of one first dummy alignment mark 221 is located on the same side as the position of the other first dummy alignment mark 221. Alternatively, among the adjacent two first dummy alignment marks 221, the position of one first dummy alignment mark 221 is located on a different side from the position of the other first dummy alignment mark 221.

Taking the orientation shown in fig. 3 as an example, the four sub-alignment marks 211 are arranged in two rows and two columns, in each row, two first dummy alignment marks 221 are respectively located at the lower sides of the corresponding sub-alignment marks 211, and in each column, two first dummy alignment marks 221 are respectively located at the lower sides of the corresponding sub-alignment marks 211.

Taking the orientation shown in fig. 4 as an example, in each row, one of the first dummy alignment marks 221 is located at the lower side of the sub-alignment mark 211 corresponding thereto, and the other first dummy alignment mark 221 is located at the other side than the lower side of the sub-alignment mark 211 corresponding thereto, for example, the other first dummy alignment mark is located at the left side of the sub-alignment mark 211 corresponding thereto.

When the number of the first dummy alignment marks 221 is at least two, the at least two first dummy alignment marks 221 are disposed at intervals along the circumferential direction of the sub-alignment mark 211.

In another example, taking the number of the first dummy alignment marks 221 as two as an example, please refer to fig. 5, the two first dummy alignment marks 221 are respectively located at two sides of the sub-overlay alignment mark 211. Two first dummy alignment marks 221 may be connected together, for example, one first dummy alignment mark 221 is disposed at the lower side of the sub-alignment mark 211 and the other first dummy alignment mark 221 is disposed at the right side of the sub-alignment mark 211. The right end portion of one of the first dummy alignment marks 221 and the lower end portion of the other first dummy alignment mark 221 are connected together.

The two first dummy alignment marks 221 may also be independently provided to be not connected to each other. For example, one of the first dummy alignment marks 221 is disposed at the lower side of the sub-alignment mark 211, and the other first dummy alignment mark 221 is disposed at the upper side of the sub-alignment mark 211.

In yet another example, referring to fig. 6, the first dummy alignment mark 221 includes a ring structure, and the first dummy alignment mark 221 surrounds the outer circumference of the sub-overlay alignment mark. In this way, the same etching precision between the edge pattern and the center pattern of the alignment mark structure 200 can be avoided as much as possible, the integrity of the alignment mark structure 200 is ensured, and the subsequent alignment precision is improved.

The vertical distance D1 between the adjacent first dummy alignment marks 221 is greater than or equal to 6 μm, so that a sufficient space is provided for the arrangement of the post-alignment mark structure, and the yield of the semiconductor device is improved.

In a possible embodiment, referring to fig. 7 and 8, the dummy alignment mark 220 further includes a second dummy alignment mark 222, and the second dummy alignment mark 222 is used to connect adjacent first dummy alignment marks 221.

In this embodiment, the first dummy alignment marks 221 may be provided on the outer periphery of the sub-alignment mark 211, or the second dummy alignment marks 222 may be provided in the region between adjacent first dummy alignment marks 221. By this arrangement, the area around the sub-overlay alignment mark 211 can be utilized to the greatest extent, and the integrity of the pattern of the overlay alignment mark structure 200 can be improved as much as possible.

With continued reference to fig. 8, in one possible implementation, the second dummy alignment mark 222 is flush with a side of the first dummy alignment mark 221 facing away from the center of the circular track.

Along the Y-axis direction, the second dummy alignment mark 222 has a first side 222a and a second side 222b disposed opposite to each other, the first side 222a being a side of the second dummy alignment mark 222 facing away from the center of the annular track, and the first side 222a being flush with a side of the first dummy alignment mark 221 facing away from the center of the annular track.

Along the X-axis direction, the second dummy alignment mark 222 has a third side 222c and a fourth side 222d that are disposed opposite to each other, the third side 222c being a side of the second dummy alignment mark 222 facing away from the center of the annular track, and the third side 222c being flush with a side of the first dummy alignment mark 221 facing away from the center of the annular track.

In the process of manufacturing a semiconductor, it is generally required to perform photolithography ten times or even several tens of times, and each of which is required to prepare an overlay alignment mark to check overlay deviation of two or more photolithography processes. For convenience of the following description, the overlay alignment mark structure in this embodiment may be referred to as a layer overlay alignment mark structure.

In this embodiment, the second dummy alignment mark 222 is flush with the side edge of the first dummy alignment mark 221 away from the center of the annular track, so that the area of the area surrounded by the dummy alignment mark 220 and the alignment mark 210 is increased, and sufficient space is provided for the arrangement of the alignment mark structure of the rear layer, thereby improving the yield of the semiconductor device.

In a possible embodiment, referring to fig. 9 and 10, the dummy alignment mark 220 further includes a third dummy alignment mark 223, and the third dummy alignment mark 223 is disposed around the outside of the first dummy alignment mark 221; or the third dummy alignment mark 223 is disposed around the outer circumferences of the first dummy alignment mark 221 and the second dummy alignment mark 222.

In an example, the third dummy alignment mark 223 is continuously added on the basis of the structure shown in fig. 6, and the third dummy alignment mark 223 is annularly arranged outside the first dummy alignment mark 221.

In another example, the third dummy alignment mark 223 is further added on the basis of the structure shown in fig. 8, and the third dummy alignment mark 223 is simultaneously looped around the outer circumferences of the first dummy alignment mark 221 and the second dummy alignment mark 222.

In this embodiment, by setting the third dummy alignment mark 223, the pattern density of the dummy alignment mark 220 is increased, so as to increase the pattern density of the scribe line region, and avoid the distortion of the pattern of the scribe line region due to the larger difference between the pattern densities of the chip region and the scribe line region, which affects the measurement accuracy of the pattern of the scribe line region.

For convenience of description of the positional relationship of the third dummy alignment mark 223 and the first dummy alignment mark 221 of the annular structure, the first dummy alignment mark may be divided. For example, the first dummy alignment mark 221 includes a first sub dummy alignment mark 2211, a second sub dummy alignment mark 2212, a third sub dummy alignment mark 2213, and a fourth sub dummy alignment mark 2214 connected in sequence, the first sub dummy alignment mark 2211 and the second sub dummy alignment mark 2212 being adjacent to the third dummy alignment mark 223. That is, the first dummy alignment mark 221 and the second sub dummy alignment mark 2212 are disposed at the outer side of the sub alignment mark 211 facing away from the center of the circular track, and the third sub dummy alignment mark 2213 and the fourth sub dummy alignment mark 2214 are disposed at the inner side of the sub alignment mark 211 facing toward the center of the circular track.

The vertical distance between the first sub dummy alignment mark 2211 and the third dummy alignment mark 223 is equal to the vertical distance between the second sub dummy alignment mark 2212 and the third dummy alignment mark 223; and the vertical distance between the first sub dummy alignment mark 2211 and the third dummy alignment mark 223 is greater than 800nm. By the arrangement, the vertical distance between the first dummy alignment mark 2211 and the third dummy alignment mark 223 can be prevented from being too small, the first dummy alignment mark 2211 and the third dummy alignment mark 223 are prevented from interfering with each other in the subsequent exposure, and the stability of the semiconductor device manufacturing process is improved.

Wherein, the vertical distance between the first dummy alignment mark 221 and the third dummy alignment mark 223 may be D2 shown in fig. 9. The vertical distance between the second sub dummy alignment mark 2212 and the third dummy alignment mark 223 may be D3 shown in fig. 9.

In one possible embodiment, referring to fig. 11, the number of the third dummy alignment marks 223 is plural, and the plural third dummy alignment marks 223 are spaced apart. That is, the plurality of third dummy alignment marks 223 are sequentially spaced apart in a direction away from the center of the circular track. Note that, the vertical distance between the adjacent third dummy alignment marks 223 may be the same or different, and the present embodiment is not limited specifically.

In one possible implementation, please continue with reference to fig. 11, the first dummy alignment mark 221 points in a vertical direction of the third dummy alignment mark 223, i.e., in the Y-axis direction shown in fig. 11.

The size of the dummy alignment mark 220 is larger than the size of the overlay alignment mark 210, i.e., the width W2 of the dummy alignment mark 220 is larger than the width W1 of the overlay alignment mark 210. By arranging the dummy alignment mark 220 with a relatively large size, the pattern density of the region where the alignment mark structure is located can be increased, and the alignment mark 210 formed in the preparation process is ensured to have an ideal etching shape.

Further, the dummy alignment marks 220 gradually increase in size in a direction away from the center of the circular track. Taking the orientation shown in fig. 11 as an example, the dimensions of the various portions of the dummy alignment marks 220 may gradually increase from the inside to the outside. Illustratively, the first third dummy alignment mark 223 has a size greater than the first dummy alignment mark 221, and the second third dummy alignment mark 223 has a size greater than the first third dummy alignment mark 223.

In this embodiment, the dummy alignment marks 220 have a size in the range of 500nm-1000nm. For example, the size of the first dummy alignment mark 221 may be 500nm, and the size of the third dummy alignment mark 223 is larger than the size of the first dummy alignment mark 221, for example, the size of the third dummy alignment mark 223 may be between 600nm and 1000nm. When the number of the third dummy alignment marks 223 is plural, the sizes of the plural third dummy alignment marks 223 sequentially increase from the inside to the outside.

Embodiments of the present disclosure provide a semiconductor device including the alignment mark structure of any of the above embodiments. In view of the details of the structure and the function of the alignment mark structure in the above embodiment, the details of the structure and the function of the alignment mark structure in the above embodiment are not repeated herein.

Referring to fig. 12, an embodiment of the disclosure further provides a method for manufacturing a semiconductor device, including the following steps:

s100: a substrate is provided, the substrate including a chip region and a scribe line region. The chip area is used for forming a device structure, and the cutting channel area is used for forming an alignment mark.

Referring to fig. 13, a substrate 10 is used to carry components disposed thereon and may include silicon substrates, silicon germanium substrates, silicon carbide substrates, silicon On Insulator (SOI) substrates, and Germanium On Insulator (GOI) substrates. In addition, a device structure may be formed in the substrate, and the device structure may be a device structure formed in a front-end of semiconductor process, for example, a MOS transistor.

It should be noted that fig. 13 represents an entire chip, the left side of the drawing represents the chip area, the right side of the drawing represents the scribe line area, and the ellipses in fig. 13 may represent only a portion of the chip area.

Step S200: an etch stop layer is formed on a substrate.

The etch stop layer 20 is formed on the substrate 10 by a process such as chemical vapor deposition (Chemical Vapor Deposition, CVD for short), physical vapor deposition (Physical Vapor Deposition, PVD for short), or atomic layer deposition (Atomic Layer Deposition, ALD for short). The material of the etching barrier layer includes silicon nitride, but is not limited thereto.

Step S300: and forming an alignment mark structure in the cutting channel region and forming a pattern in the chip region, wherein a gap is formed in the alignment mark structure.

For example, referring to fig. 13 and 14, a material layer 30, a second mask layer 40 and a photoresist layer 50 are formed on the etch stop layer 20 in a stacked arrangement. The photoresist layer 50 is patterned to form a mask pattern within the photoresist layer 50. And a part of the second mask layer 40 is removed by using the mask pattern as a mask, so that the remaining second mask layer 40 forms a plurality of first mandrels 41 arranged at intervals.

Some of the plurality of first mandrels 41 located on the scribe line region are used as mask patterns for subsequently forming the alignment mark for alignment, and the remaining portions are used as mask patterns for subsequently forming the dummy alignment mark. A plurality of first mandrels 41 located over the chip region are used as mask patterns for subsequent patterning.

Thereafter, referring to fig. 15, a sacrificial layer 60 is formed to encapsulate each first mandrel 41, and the sacrificial layer 60 also covers the material layer 30 exposed between adjacent first mandrels 41. The material of the sacrificial layer 60 includes silicon oxide, but is not limited thereto.

Thereafter, referring to fig. 16, the mask material layer 70 is backfilled, and the mask material layer 70 fills the area surrounded by the sacrificial layer 60. The material of the mask material layer 70 includes silicon oxynitride, but is not limited thereto.

Thereafter, referring to fig. 17, a CMP process may be used to planarize the top surface of the mask material layer such that the top surface of the remaining mask material layer is level with the top surface of the first mandrel, and remove the sacrificial layer on the top side of the first mandrel. The remaining masking material layer and sacrificial layer may be referred to as a second mandrel 71.

Finally, with the first mandrel 41 and the second mandrel 71 as masks, an alignment mark structure is formed in the scribe line region, and a pattern is formed in the chip region.

Compared with the technical scheme in the related art, the number of the first mandrels positioned in the cutting channel region is increased, the number of the grooves formed between the adjacent first mandrels is also increased, and the amount of mask materials backfilled in the cutting channel region can be increased, so that the top surfaces of the mask material layers positioned on the chip region and the cutting channel region are basically flush, the integrity of the formed alignment mark structure is ensured, the defect of patterns formed in the cutting channel region is avoided, and the subsequent alignment precision and the accuracy of measuring the performance of the semiconductor device are improved.

Note that, the overlay alignment mark structure 200 has a gap 201 therein, and the gap 201 may refer to a gap formed by the overlay alignment mark 210, for example, the gap herein may refer to a gap between adjacent first alignment marks and a gap between adjacent second alignment marks. A gap between the overlay alignment mark and the dummy alignment mark may also be referred to. It may also refer to a gap between the dummy alignment marks, for example, a gap between the first dummy alignment mark and the third dummy alignment mark, or a gap between adjacent third dummy alignment marks.

Step S400: a first mask layer is formed, the first mask layer covering the pattern on the chip region. The structure of which is shown in figure 18.

Thus, the first mask layer 80 can be used to block the pattern on the chip region, and the alignment mark structure on the scribe line region can be exposed.

Step S500: the gap in the overlay alignment mark structure is enlarged.

For example, referring to fig. 19, etching may be used to remove a portion of the width of the overlay alignment mark structure exposed in the gap, so as to expand the width of the gap 201 in the overlay alignment mark structure, and avoid the occurrence of a phenomenon that the pattern portion of the non-edge region of the alignment mark structure cannot expose the top surface of the etching stopper 20 due to the too small gap 201. By the arrangement, the etching uniformity of the patterns of the edge area and the patterns of the non-edge area of the alignment mark structure can be further improved, so that the signal intensity during the measurement of the subsequent alignment mark structure is improved, and better measurement accuracy is obtained.

In addition, by disposing the etching stopper 20, damage to the substrate 10 or devices within the substrate 10 can be avoided when expanding the gap 201 in the overlay alignment mark structure, so as to improve the yield of semiconductor devices.

In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.

In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Claims (15)

1. An alignment mark structure for alignment, wherein the alignment mark structure is formed in a scribe line region of a semiconductor device, and the alignment mark structure comprises an alignment mark and a dummy alignment mark; the dummy alignment mark is arranged on the outer side of the alignment mark and is arranged at intervals with the alignment mark.

2. The alignment mark structure according to claim 1, wherein the alignment mark comprises a plurality of sub alignment marks, the plurality of sub alignment marks are arranged at intervals along the annular track, and the sub alignment marks on a diagonal line of the annular track are rotationally symmetrical with respect to a center of the annular track;

the dummy alignment marks comprise a plurality of first dummy alignment marks, and the plurality of first dummy alignment marks and the plurality of sub-alignment marks are arranged in one-to-one correspondence.

3. The overlay alignment mark structure of claim 2, wherein the first dummy alignment mark is disposed at least on one side of the sub-overlay alignment mark.

4. The alignment mark alignment structure of claim 3, wherein one of the adjacent two first dummy alignment marks is located at a position different from a position of the other first dummy alignment mark.

5. The overlay alignment mark structure of claim 3, wherein the first dummy alignment mark comprises a ring structure, the first dummy alignment mark encircling an outer perimeter of the sub-overlay alignment mark.

6. The overlay alignment mark structure of claim 5, wherein the dummy alignment mark further comprises a second dummy alignment mark for connecting adjacent ones of the first dummy alignment marks.

7. The overlay alignment mark structure of claim 6, wherein the second dummy alignment mark is flush with a side of the first dummy alignment mark facing away from a center of the annular track.

8. The alignment mark alignment structure of claim 5 or 6, wherein the dummy alignment mark further comprises a third dummy alignment mark disposed annularly outside the first dummy alignment mark; or the third dummy alignment mark is annularly arranged on the peripheries of the first dummy alignment mark and the second dummy alignment mark.

9. The overlay alignment mark structure of claim 8, wherein the number of the third dummy alignment marks is plural, and the plural third dummy alignment marks are arranged at intervals.

10. The overlay alignment mark structure of claim 9, wherein a vertical distance between adjacent first dummy alignment marks is greater than 6 μm.

11. The overlay alignment mark structure of claim 8, wherein the first dummy alignment mark comprises a first sub dummy alignment mark, a second sub dummy alignment mark, a third sub dummy alignment mark, and a fourth sub dummy alignment mark connected in sequence, the first sub dummy alignment mark and the second sub dummy alignment mark being adjacent to the third dummy alignment mark;

the vertical distance between the first sub dummy alignment mark and the third dummy alignment mark is equal to the vertical distance between the second sub dummy alignment mark and the third dummy alignment mark; and a vertical distance between the first sub dummy alignment mark and the third dummy alignment mark is greater than 800nm.

12. The alignment mark structure of claim 11, wherein the dummy alignment mark has a size greater than the alignment mark along a vertical direction in which the first dummy alignment mark points to the third dummy alignment mark, and wherein the dummy alignment mark has a size that gradually increases in a direction away from a center of the circular track.

13. The alignment mark structure according to any one of claims 2 to 7, wherein the number of the sub alignment marks is four, the four sub alignment marks enclose a rectangle, and the four sub alignment marks are respectively located at the vertices of the rectangle;

in the adjacent two sub-alignment marks, one of the sub-alignment marks comprises a plurality of strip-shaped first alignment marks arranged at intervals, the other sub-alignment mark comprises a plurality of strip-shaped second alignment marks arranged at intervals, and the extending directions of the first alignment marks are mutually perpendicular to the extending directions of the second alignment marks.

14. A semiconductor device comprising the overlay alignment mark structure of any one of claims 1-13.

15. A method of manufacturing a semiconductor device, comprising the steps of:

providing a substrate, wherein the substrate comprises a chip area and a cutting channel area;

forming an etching barrier layer on the substrate;

forming the alignment mark structure of any one of claims 1-13 in the scribe line region and forming a pattern in the chip region, wherein the alignment mark structure has a gap therein;

forming a first mask layer, wherein the first mask layer covers the pattern on the chip area;

and expanding the gap in the overlay alignment mark structure.