KR20020009880A - Method of forming a overlay key - Google Patents

Abstract

PURPOSE: A method for manufacturing an overlay key is provided to precisely correct misalignment regarding the entire region on a semiconductor substrate, by forming 4 overlay keys in a scribe line on the substrate and by making each overlayer key form a vernier while using as a reference the portion where mutual asymmetrical deposition rates are the same in two contact holes. CONSTITUTION: At least two contact holes are formed in the scribe line on the semiconductor substrate. A metal material is deposited on the entire surface of the resultant structure having more than two contact holes. A photoresist layer pattern is formed between more than two contact holes surrounded by the metal material.

Description

Overlay Key Formation {METHOD OF FORMING A OVERLAY KEY}

The present invention relates to an overlay key forming method.

In the semiconductor device manufacturing process, a number of photographic and etching processes are repeatedly performed. As a series of semiconductor device manufacturing processes involving the photolithography process proceed, chips are formed on the semiconductor substrate, and a scribe line for dividing the chips is provided with various kinds of alignment keys for exposing the photolithography process. (Alignment Key) is formed. The overlay alignment key of the alignment keys serves to measure the degree of alignment of the preceding photolithography process and the subsequent photolithography process in performing a plurality of photolithography processes. Accordingly, the degree of alignment between the pattern formed in the preceding process and the pattern formed in the subsequent process can be known.

The photo process goes through a complicated process in which a plurality of exposure masks are overlapped and used. Alignment between the exposure masks used in each process is made based on the overlay key. Stepper, which is a step and repeat type exposure equipment mainly used in photographic processes, is a device in which a stage on which a semiconductor substrate is placed moves in the X-Y direction and repeatedly moves in alignment. The stage is aligned with the semiconductor substrate based on various kinds of alignment keys.

Looking at the overlay alignment in the photo process, the overlay of the semiconductor substrate that is exposed and exposed in the alignment equipment, such as a stepper is measured. Then, using the measured overlay displacement, a correction value is calculated statistically. The correction value is fed back to the stepper, and the stepper performs the correction and exposes it. Next, after the photosensitive film pattern is formed through the developing process, the displacement is measured again in the overlay key, and when the required process reference value is satisfied, the process proceeds to the subsequent process. If outside the process threshold, repeat the process.

In order to calculate a correction value using the overlay measurement system in the aligned exposed semiconductor substrate, an overlay measurement key, which is one of the alignment keys, is required. The overlay key is composed of a pattern in the overlay key (hereinafter referred to as a mother) already formed in the preceding process and a photosensitive film pattern (hereinafter referred to as son) in the overlay key formed through the exposure. The mother line uses a contact hole and a line / space pattern.

On the other hand, as semiconductors are highly integrated, the width of contact holes decreases and the depth becomes relatively deep. A new deposition mechanism is required to fill the contact holes having a large aspect ratio. Long throw sputtering (hereinafter referred to as LTS) to deposit metal materials by increasing the distance between the semiconductor substrate and the target in order to deposit metal materials in the contact holes having a high aspect ratio in order to reflect this demand. I'm using.

However, in general sputtering, the distance between the semiconductor substrate and the target is short, so that uniform deposition is performed on the semiconductor substrate. However, in the case of the LTS, the distance between the semiconductor substrate and the target becomes far and asymmetrical deposition occurs in the contact hole at the edge of the semiconductor substrate.

Hereinafter, with reference to FIGS. 1 to 5, when the LTS process in which asymmetrical deposition is performed is applied, the problem of the conventional overlay key forming method will be described.

Referring to FIG. 1, the target 3 and the semiconductor substrate 5 are spaced apart in the LTS chamber 1. Therefore, the metal material 11 is uniformly deposited in the contact hole 9 located in the center portion 7 of the semiconductor substrate 5, but the contact hole 9 located in the left side 13 of the semiconductor substrate 5 is contact hole. Asymmetrical deposition occurs in which the left sidewall of (9) is deposited relatively thick and the right sidewall of the contact hole 9 is formed relatively thick in the contact hole 9 located on the right side 15 of the semiconductor substrate 5. Of course, the same phenomenon occurs above and below the semiconductor substrate 5. That is, the degree of asymmetrical deposition increases from the central portion 7 of the semiconductor substrate 5 to the edge of the semiconductor substrate 5. The contact hole 9 in which the metal material 11 is deposited on the semiconductor substrate 5 shown in FIG. 1 has an enlarged cross section for clarity.

Referring to FIG. 2, a photosensitive film is coated on the insulating film 17 on the semiconductor substrate 5 and exposed using a photomask 19 for forming a contact hole. Next, the photosensitive film pattern 21 is formed through a developing process.

Referring to FIG. 3, the insulating layer 17 is etched using the photoresist pattern 21 as an etching mask to form a contact hole 9, and the photoresist pattern is removed. The metal material 11 is deposited on the entire surface of the product in which the contact hole 9 is formed by the LTS method. At this time, the metal material 11 deposited on the left wall of the contact hole 9 and the metal material 11 on the right wall are formed asymmetrically. FIG. 3 shows only the case of the overlay key 22 located in the left area in the center on the semiconductor substrate 5. The contact hole 9 surrounded by the metal material 11 corresponds to the mother 9 of the overlay key 22.

Referring to FIG. 4, a son is formed in the overlay key 22 on which the mother 9 is formed. The photoresist is coated on the entire surface of the resultant formed with the mother 9, and exposed using a photomask 23 for forming metal wiring. Subsequently, a photosensitive film pattern 25 is formed in the contact hole 9 surrounded by the metal material 11 through a developing process. The photosensitive film pattern 25 in the contact hole 9 becomes the son 25.

At this time, the left gap 27 and the right gap 29 of the mother 9 and the son 25 are not the same due to the deposition of the asymmetric metal material 11.

Referring to FIG. 5, a plan view of the overlay key 22 positioned in the left area in the center on the semiconductor substrate is illustrated. Here, FIG. 4 is a cross section along the line I-I. The center of the mother 9 and the center of the son 25 do not coincide and are moved in the horizontal direction. As a result, a misalignment is performed by the difference between the left gap 27 of the mother 9 and the right gap 29 of the son. As a result, the yield of the semiconductor device due to misalignment during subsequent metal wiring formation is reduced.

Accordingly, an aspect of the present invention is to provide a method for forming an overlay key capable of preventing misalignment between a preceding process and a subsequent process due to asymmetrical deposition on a semiconductor substrate.

1 is a schematic diagram for explaining asymmetrical deposition by a conventional long throw sputtering method.

2 to 4 are cross-sectional views sequentially illustrating a process of forming an overlay key according to a conventional method.

5 is a plan view of an overlay key formed in accordance with the prior art.

6 to 8 are cross-sectional views sequentially illustrating a process of forming an overlay key according to the present invention.

9 and 10 are plan views of overlay keys formed in accordance with the present invention.

11 is a schematic diagram for explaining an arrangement of an overlay key formed in accordance with the present invention on a semiconductor substrate.

In order to achieve the above technical problem, the present invention comprises the steps of forming at least two contact holes in the scribe line on the semiconductor substrate, the step of depositing a metal material on the entire surface of the product formed with the two or more contact holes and the metal material And forming a photoresist pattern between the surrounded two or more contact holes and the contact holes.

The photoresist pattern formed between the at least two contact holes and the contact holes may be formed by the same thickness of the metal material formed on the sidewalls of the one contact hole and the metal material formed on the sidewalls of the other contact hole. It is preferable to form such that the center of the photosensitive film pattern is coincident with the center of the deposited portion having the same thickness as a reference line.

The overlay key formed in the scribe line may be divided into a left region, a right region, an upper region, and a lower region with respect to the center of the semiconductor substrate to form four bundles of the overlay keys corresponding to each region. Do.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 11.

Referring to FIG. 6, a photosensitive film is coated on the insulating film 52 on the semiconductor substrate 50, and exposed using a photomask 54 forming a contact hole. Subsequently, the photosensitive film pattern 56 is formed through a developing process. Here, as viewed in cross section, a photosensitive film pattern 56 for forming two contact holes is formed.

Referring to FIG. 7, the insulating film 52 is etched using the photoresist pattern 56 as an etching mask, and then the photoresist pattern 56 is removed. The metal material 60 is deposited on the entire surface of the product from which the photoresist pattern 56 is removed by the LTS method. 7 shows a mother overlay key 61 formed in the scribe line of the left region from the center of the semiconductor substrate 50. The left sidewall of the left contact hole 58a and the left side of the right contact hole 58b are shown in FIG. The side wall is formed relatively thicker than the right side wall. This is because, as described above, the deposition by the LTS method is not uniformly deposited over the entire area on the semiconductor substrate 50. The left contact hole 58a and the right contact hole 58b on which the asymmetric metal material 60 is deposited correspond to the mother 58 of the overlay key 61.

Referring to FIG. 8, a photosensitive film is coated on the entire surface of the semiconductor substrate 50 on which the metal material 60 is deposited, and exposed using a photomask 62 for forming metal wiring. Next, the photosensitive film pattern 64 is formed through a developing process. The photoresist pattern 64 corresponds to the son 64 of the overlay key 61. Here, in contrast to the prior art, the son-shaped light shielding pattern 64a on the photomask 62 for forming the metallization is formed by asymmetrical deposition in two contact holes, which are the mothers 58, as the reference point. The photomask 62 is formed to form the metal wiring so that the son 64 is formed at the center thereof. That is, the distance 66 between the right sidewall of the left contact hole 58a of the mother 58 and the left end of the son 64 is the right sidewall of the right side of the son 64 and the right sidewall of the right contact hole 58b of the mother 58. The son son 64 is formed to be equal to the distance 68 between them. In addition, the distance between the left side wall of the left contact hole 58a of the mother 58 and the left end of the son 64 and the distance between the right end of the son 64 and the left side wall of the right contact hole 58b of the mother 58 It may be formed to match. In the two contact holes 58 surrounded by the asymmetrically deposited metal material 60, mutually asymmetrical deposition may be set to a reference line to form a son 64 to overcome the misalignment. As a result, the misalignment of the metal wiring may be prevented in a subsequent process of forming the metal wiring by etching the metal material by using the photosensitive film pattern 64, which is the son 64, as an etching mask.

9 is a plan view of an overlaid key 61 formed in the left region in the center of the semiconductor substrate. 8 is a cross-sectional view along II-II. The distance 66 between the right side of the left contact hole 58a of the mother terminal 58 and the left side of the son 64 and the right side of the right contact hole 58b of the mother 58 and the right side of the son ( 68 is the same. As a whole, the son 64 is not located in the center of the mother 58, which is the rectangular contact hole 58, but is located to the right along the horizontal direction. However, no vertical skew occurs. This is because the overlay key 61 of FIG. 9 illustrates a case where the overlay key 61 is located in the left region of the semiconductor substrate, so that deposition of the metal material that is deflected in the vertical direction does not occur. However, in the upper region and the lower region of the semiconductor substrate, the metal material is asymmetrically deposited along the vertical direction. Therefore, at least four overlay keys 61 are required to correct misalignment due to asymmetrical deposition over the entire area of the semiconductor substrate.

Referring to FIG. 10, the four overlay keys 61 are illustrated. Each overlay key 61 is used for alignment correction of four regions of the semiconductor substrate, for example, left, right, upper and lower regions. In the four overlay keys 61 each son 64 is positioned deflected left, right, up and down at the center of the square mother 58.

Referring to FIG. 11, a chip 70 is formed on a semiconductor substrate 50, and a scribe line 72 defining the chip 70 is formed. The semiconductor substrate 50 may be divided into four regions along the dividing line 74 defining the left, right, upper and lower regions on the semiconductor substrate. Four overlay keys 61 formed in accordance with the present invention described above are located in the scribe line 72. All four overlay keys 61 are formed in each scribe line 72 that defines each chip 70. Therefore, since the deflections of the deposition of the asymmetric metal material are formed differently according to the four regions on the semiconductor substrate 50, using the overlay keys corresponding to the respective regions as described above among the four overlay keys 61. Correcting the misalignment reduces the inaccuracy of the misalignment occurring in the prior art. This prevents misalignment during subsequent metallization, resulting in increased productivity due to improved yields.

As described above, according to the present invention, four overlay keys are formed in a scribe line on a semiconductor substrate, and each overlay key is formed by forming a son as a reference line based on a portion having the same degree of mutual asymmetry deposition in two contact holes. Correction of misalignment can be performed accurately over the entire area on the substrate. Therefore, the misalignment is prevented after the subsequent metallization is formed by more accurate alignment. The prevention of such misalignment increases the yield and, as a result, increases the productivity of the semiconductor device manufacturing process.

Claims (3)

Forming at least two contact holes in the scribe line on the semiconductor substrate; Depositing a metal material on the entire surface of the resultant product in which the two or more contact holes are formed; And Forming a photoresist pattern between the at least two contact holes and the contact holes surrounded by the metal material; The method of claim 1, The photoresist pattern formed between the at least two contact holes and the contact holes may be formed by the same thickness of the metal material formed on the sidewalls of the one contact hole and the metal material formed on the sidewalls of the other contact hole. And forming a center of the photoresist pattern in the center of the same thickness as a reference line. The method of claim 1, The overlay key formed in the scribe line is divided into a left region, a right region, an upper region, and a lower region with respect to the center of the semiconductor substrate to form four bundles of the overlay keys corresponding to each region. Overlay key formation method.