KR100262667B1 - A method for fabricating semiconductor device - Google Patents
A method for fabricating semiconductor device Download PDFInfo
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- KR100262667B1 KR100262667B1 KR1019960044817A KR19960044817A KR100262667B1 KR 100262667 B1 KR100262667 B1 KR 100262667B1 KR 1019960044817 A KR1019960044817 A KR 1019960044817A KR 19960044817 A KR19960044817 A KR 19960044817A KR 100262667 B1 KR100262667 B1 KR 100262667B1
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- Prior art keywords
- vernier
- overlay
- pattern
- semiconductor device
- line width
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
Description
본 발명은 반도체 제조 분야에 관한 것으로, 특히 반도체 장치 제조 공정 중 포토 마스크 공정을 통한 패턴 형성시 패턴 검사를 위한 오버레이 버니어(overlay vernier) 및 해상도 마크(resolution mark) 형성방법을 포함하는 반도체 장치 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing field, and more particularly, to a semiconductor device manufacturing method including an overlay vernier and a resolution mark forming method for pattern inspection during pattern formation through a photomask process during a semiconductor device manufacturing process .
이하, 첨부된 도면 도 1a 및 도 1b를 참조하여 종래기술 및 그 문제점을 살펴본다.BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and form a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
도 1a는 4메가디램을 기준으로 한 하나의 필드에서 스크라이브 라인(10)상에 오버레이 버니어(11), 디스토션(distortion) 버니어(12), 해상도 마크(13)등이 형성된 위치를 나타내고 있다. 여기서, 오버레이 버니어(11) 및 디스토션 버니어(12)와 해상도 마크(13)의 위치가 상이하여 웨이퍼 위치별 패턴의 균일도 및 해상도를 확인하기 위한 스캐닝을 따로 수행해야 했다.1A shows a position where an overlay vernier 11, a distortion vernier 12, a resolution mark 13, and the like are formed on a scribe line 10 in one field based on 4 megadiram. The positions of the overlay vernier 11 and the distortion vernier 12 and the resolution mark 13 are different, and scanning has to be separately performed to check the uniformity and resolution of the pattern for each wafer position.
해상도 마크(13)는 선폭 및 크기가 다른 패턴을 좁은 간격으로 여러 개 형성하므로써 포토 마스크 공정시 패턴의 균일도 및 해상도를 측정하기 위해 필드마다 하나씩 스크라이브 라인(10) 상에 형성된다.The resolution marks 13 are formed on the scribe lines 10 one by one for measuring the uniformity and the resolution of the pattern in the photomask process by forming a plurality of patterns having different line widths and sizes at narrow intervals.
오버레이 버니어(11)는 패턴의 중첩도를 측정하기 위하여 필드의 중앙부의 스크라이브 라인(10) 상에 위치하게 되고, 디스토션 버니어(12)는 노광시 렌즈의 왜곡에 의한 패턴의 뒤틀림 정도를 측정하기 위해 필드의 네 모서리의 스크라이브 라인(10) 상에 형성된다.The overlay vernier 11 is positioned on the scribe line 10 at the center of the field to measure the degree of overlap of the pattern and the distortion vernier 12 measures the distortion degree of the pattern due to the distortion of the lens during exposure Are formed on the scribe lines 10 at the four corners of the field.
한편, 도 1b에 도시된 바와 같이 종래의 오버레이 버니어를 사용한 패턴 중첩도 측정시에는 금속층의 난반사로 인하여 스캐닝시 오신호가 검출됨으로써 패턴의 정확한 정렬이 용이하지 않다. 여기서, 모 버니어(11a)는 층간절연막(15)을 선택적으로 식각하여 형성되는 콘택홀의 식각 및 금속막 증착시에 형성된 것이며, 자 버니어(11b)는 금속막(16) 상에 전도막 패턴을 정의하기 위한 포토레지스트 패턴을 형성할 때 형성된다. 미설명 도면 부호 14는 기판, X 및 X', Y 및 Y'는 패턴의 중첩도 측정을 위한 척도이다.On the other hand, as shown in FIG. 1B, when measuring the pattern overlap using conventional overlay vernier, due to irregular reflection of the metal layer, a signal is detected at the time of scanning, so that the pattern can not be accurately aligned. The mode vernier 11a is formed during the etching of the contact hole and the metal film deposition which are formed by selectively etching the interlayer insulating film 15 and the sub vernier 11b defines the conductive film pattern on the metal film 16. [ Is formed at the time of forming the photoresist pattern. 14 is a substrate, and X and X ', Y and Y' are measures for measuring the overlap degree of the pattern.
본 발명은 버니어의 단차에 의한 난반사를 감소시키고, 웨이퍼 위치별 패턴 균일도 확인이 용이하도록 하는 반도체 장치 제조방법을 제공하는데 그 목적이 있다.It is an object of the present invention to provide a semiconductor device manufacturing method which can reduce irregular reflection due to a step difference of a vernier and make it easy to confirm pattern uniformity by wafer position.
도 1a는 종래 기술에 따라 형성된 오버레이 버니어와 해상도 마크의 위치를 나타낸 평면도.BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a plan view showing positions of overlay verniers and resolution marks formed according to the prior art; Fig.
도 1b는 종래 기술에 따른 오버레이 버니어와 그 단면도 및 검출 신호를 나타낸 도면.Fig. 1B is a diagram showing an overlay vernier, a cross-sectional view, and a detection signal thereof according to the prior art.
도 2는 본 발명의 일 실시예에 따른 오버레이 버니어와 그 단면도 및 검출 신호를 나타낸 도면.2 shows an overlay vernier, a cross-sectional view thereof, and a detection signal according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
10 : 스크라이브 라인 11 : 오버레이 버니어10: scribe line 11: overlay vernier
12 : 디스토션 버니어 13, 22 : 해상도 마크12: Distortion Vernier 13, 22: Resolution mark
11a, 21a : 모 버니어 11b, 21b : 자 버니어11a, 21a: Moovurner 11b, 21b:
14. 23 : 기판 15, 24 : 층간절연막14. 23: Substrate 15, 24: Interlayer insulating film
16, 25 : 금속막16, 25: metal film
X, X', Y, Y' : 패턴의 중첩도 측정을 위한 척도X, X ', Y, Y': scale for measuring the overlap of patterns
Z : 모/자 버니어의 선폭Z: line width of mother /
상기 목적을 달성하기 위한 본 발명의 특징적인 반도체 장치 제조방법은, 박스-인-박스(box-in-box) 형태의 오버레이 버니어를 사용한 패턴의 중첩도 측정시 상기 오버레이 버니어의 단차에 의한 난반사를 감소시키기 위하여 모 버니어 및 자 버니어를 소정 두께의 선폭을 가지는 방형 테두리 형태로 형성하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including the steps of: (a) forming a pattern on an overlay vernier of a box-in- The moraine and the vernier are formed in a rectangular frame shape having a line width of a predetermined thickness.
즉, 본 발명은 모 버니어 및 자 버니어를 소정 두께의 선폭을 가지는 방형 테두리 형태로 형성하여 버니어의 단차에 의한 난반사를 감소시키는 기술이다. 또한, 본 발명은 모 버니어 및 자 버니어 내의 모서리에 해상도 마크를 형성함으로써 웨이퍼 위치별 패턴 균일도 확인이 용이하도록 한다.That is, the present invention is a technique of reducing the diffuse reflection due to the step of the vernier by forming the vernier and the vernier into a rectangular frame shape having a line width of a predetermined thickness. Further, the present invention makes it easy to confirm the pattern uniformity by wafer position by forming resolution marks at corners in the vernier and the vernier.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in order to facilitate the present invention by those skilled in the art.
첨부된 도면 도 2는 본 발명의 일 실시예에 따른 오버레이 버니어와 그 단면도 및 검출 신호를 나타낸 것으로, 이하 이를 참조하여 설명한다.2 is a sectional view and a detection signal of an overlay vernier according to an embodiment of the present invention, and will be described with reference to FIG.
본 실시예는 먼저, 오버레이 버니어 형성시에 모 버니어(21a) 및 자 버니어(21b)를 Z 만큼의 선폭을 가지는 방형 테두리 형태로 형성한다. 이때, 선폭 'Z'는 정해진 크기가 아니며, 종래의 오버레이 버니어에서 모 버니어(21a)에 의한 단차를 최소화하여 금속층의 난반사에 의한 오신호 검출 및 오정렬을 방지할 수 있도록 한다.In this embodiment, the moovernirers 21a and 21b are formed in a rectangular frame shape having a line width of Z when the overlay vernier is formed. At this time, the line width 'Z' is not a predetermined size, and it is possible to minimize misalignment due to irregular reflection of the metal layer by minimizing the level difference caused by the moonier 21a in the conventional overlay vernier.
더불어, 오버레이 버니어 형성시에 모 버니어(21a) 및 자 버니어(21b) 박스 네 모서리에 해상도 마크(22)를 동시에 형성함으로써 자동 중첩도 측정장비로 측정시 또는 전자 현미경을 사용하여 측정할 때 웨이퍼 상의 위치별 패턴 균일도를 확인할 수 있게 되어 공정 시간을 단축하고, 정확한 패턴의 형성을 기할 수 있게 된다.In addition, when the overlay vernier is formed, the resolution marks 22 are simultaneously formed at the four corners of the vernier 21a and the vernier 21b so that when the measurement is performed with the automatic overlap degree measuring device or the electron microscope, It is possible to confirm the pattern uniformity by position, thereby shortening the process time and enabling precise pattern formation.
해상도 마크(22)를 모 버니어(21a) 및 자 버니어(21b) 박스의 네 모서리에 형성하는 이유는 웨이퍼의 레벨링 체크를 고려한 것이다. 미설명 도면 부호 23은 기판, 24는 층간절연막, 25는 금속막, 그리고 X 및 X', Y 및 Y'는 패턴의 중첩도 측정을 위한 척도이다.The reason why the resolution marks 22 are formed at the four corners of the modelers 21a and 21b is that the wafer leveling check is considered. Reference numeral 23 denotes a substrate, 24 denotes an interlayer insulating film, 25 denotes a metal film, and X and X ', Y and Y' are measures for measuring the overlap degree of the pattern.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be apparent to those of ordinary skill in the art.
전술한 본 발명은 모 버니어 및 자 버니어를 소정 두께의 선폭을 가지는 방형 테두리 형태로 형성함으로써 단차에 의한 난반사를 방지하여 오신호의 검출을 막을 수 있고, 모 버니어 및 자 버니어의 모서리에 해상도 마크를 동시에 형성함으로써 공정을 줄이는 효과가 있다.The present invention can prevent the diffuse reflection due to the step difference and prevent the detection of an excellent signal by forming the vernier and the vernier in the form of a square frame having a line width of a predetermined thickness, So that the process can be reduced.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960044817A KR100262667B1 (en) | 1996-10-09 | 1996-10-09 | A method for fabricating semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960044817A KR100262667B1 (en) | 1996-10-09 | 1996-10-09 | A method for fabricating semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR19980026389A KR19980026389A (en) | 1998-07-15 |
| KR100262667B1 true KR100262667B1 (en) | 2000-09-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019960044817A KR100262667B1 (en) | 1996-10-09 | 1996-10-09 | A method for fabricating semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100519374B1 (en) * | 2000-12-12 | 2005-10-07 | 주식회사 하이닉스반도체 | Method for measuring overlay of semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0387013A (en) * | 1989-07-21 | 1991-04-11 | Nec Corp | Manufacture of semiconductor device |
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1996
- 1996-10-09 KR KR1019960044817A patent/KR100262667B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0387013A (en) * | 1989-07-21 | 1991-04-11 | Nec Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100519374B1 (en) * | 2000-12-12 | 2005-10-07 | 주식회사 하이닉스반도체 | Method for measuring overlay of semiconductor device |
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| Publication number | Publication date |
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| KR19980026389A (en) | 1998-07-15 |
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