KR20000003610A - Method of forming alignment mark of semiconductor device - Google Patents

Abstract

PURPOSE: The method improves the overlay accuracy by removing an oxide film causing CMP irregularity when forming an initial topology. CONSTITUTION: The method improves the alignment or the alignment measurement accuracy when forming a word line with a material including a metal or a metal component by using a topology as an alignment mark by forming the topology on an isolation region on a scribe line of a semiconductor substrate and forming an isolation insulation film and removing the isolation insulation film to reveal the topology with photolithography using a mask for scribe line.

Description

Method of forming alignment mark of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an alignment mark of a semiconductor device, and more particularly, to a technique of forming an alignment mark to improve overlapping accuracy by removing an oxide film causing CMP irregularities during initial topology formation.

In general, a highly integrated semiconductor device undergoes a complicated process in which a plurality of exposure masks are overlapped and used, and alignment between exposure masks used in stages is based on a mark of a specific shape.

The mark is called an alignment key or alignment mark, and is used for layer to layer alignment between different masks or between dies for one mask.

A stepper, which is a step and repeat type exposure apparatus used in a semiconductor device manufacturing process, is a device in which a stage moves in the X-Y direction and repeatedly moves in alignment. The stage is aligned automatically or manually on the basis of the alignment mark, the stage is mechanically operated, so that alignment errors occur during repeated processes, and if the alignment error exceeds the allowable range, device defects occur.

As described above, the adjustment range of the overlapping accuracy due to misalignment depends on the design rule of the device, and is usually about 20 to 30% of the design rule.

In addition, an overlay accuracy measurement mark for confirming that the alignment between the layers formed on the semiconductor substrate is correctly used is also used in the same manner as the alignment mark.

Conventional alignment marks and overlapping precision measurement marks are formed on a scribe line which is a portion where a chip is not formed in a semiconductor wafer, and a vernier alignment mark is used as a measuring method of misalignment using the alignment marks. It is compensated after measuring by the visual inspection method used and the automatic inspection method using a box in box or bar in bar alignment mark, but one side of the chip becomes weak as the device becomes highly integrated. It has a size of about 15 to 25 mm, and the dozens of mask processes are performed, the overlay measurement marks formed on the scribe line may be blurred or damaged as the contour of the overlay measurement mark pattern is continuously measured several times. Can be inaccurate. In addition, in a highly integrated semiconductor device requiring a large number of exposure masks, it is necessary to measure the overlay accuracy between a plurality of layers, and thus a plurality of overlay measurement marks are formed on a scribe line and used for the measurement. At this time, the size of the overlay mark has a size of 70 × 70 μm ² and 30 or more are required for 256M DRAM. As a result, the area occupied by them becomes large, and various marks required by the semiconductor manufacturing process, for example, LSA, FIA, EM, etc., cannot be formed on the scribe line, or the position of the overlay measurement mark is not placed at the outermost corner. Reduce precision or reduce process yield.

Hereinafter, with reference to the accompanying drawings will be described with respect to the prior art.

1A to 1D are process flow charts illustrating a device isolation process using a uniform CMP process, even though a gate electrode is formed using a metal or a material containing a metal component since the initial topology is 500 to 4000 microseconds after the CMP process. Connected to the surface topology there is no problem with alignment or its accuracy measurement.

2A to 2D are process flow diagrams illustrating a device isolation process using a non-uniform CMP process, in which initial topologies formed are nonuniform at each formation position, so that the topology is different, or the topology is not formed at all when an extreme CMP process is performed. It may not be.

As described above, the method for forming an alignment mark of a semiconductor device according to the prior art increases the initial topology because the difference between the initial topology and the reflectance cannot be read in the process of forming a gate electrode including an opaque metal or a metal component. Uneven or eliminated toroides, which must be connected to the surface topology, are transferred to the surface topology as it is, thereby making it impossible to align or measure the accuracy thereof, and there is a problem in that accuracy is unreliable.

In order to solve the problems of the prior art described above, after performing the device separation process after the CMP process, by using a mask to remove the oxide film of the alignment mark position, an artificial initial topology is formed, and the initial topology as a surface topology It is an object of the present invention to provide a method of forming an alignment mark of a semiconductor device that is connected to facilitate alignment or measurement of overlapping thereof.

1A-1D are process flow diagrams illustrating a device isolation process using a uniform CMP process.

2A-2D are process flow diagrams illustrating device isolation processes using non-uniform CMP processes.

Figure 3a to 3g is a process flow chart showing the alignment mark forming process according to the present invention.

4 is a plan view of a reticle for forming an alignment mark used in FIGS. 3a to 3g.

<Description of Signs of Major Parts of Drawings>

11: semiconductor substrate 13: nitride film pattern

15 oxide film 17 mask for scribe line

19 metal film for gate electrode 21 mask for gate electrode

23: Die 25: scribe line

27: reticle

In order to achieve the above object, a method of forming an alignment mark of a semiconductor device according to the present invention,

In the method for forming an alignment mark of a semiconductor device,

Exposing a portion intended to be an isolation region on an upper portion of the semiconductor substrate, and forming a nitride film pattern protecting the portion intended to be an alignment mark in the isolation region on the scrubber line outside the die;

Forming a trench by etching the semiconductor substrate using the nitride film pattern as an etching mask;

Forming an oxide film on the structure;

Removing the oxide film by a CMP process;

Removing the nitride film pattern;

Forming a mask for a scribe line exposing the alignment mark on the structure;

And forming an alignment mark by removing the oxide layer by using the scribe line mask as an etching mask.

Hereinafter, a method of forming an alignment mark of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

3A to 3G are process flowcharts illustrating an alignment mark forming process according to the present invention, and FIG. 4 is a plan view illustrating a reticle for forming an alignment mark used in FIGS. 3A to 3G.

First, a nitride film pattern 13 is formed on the semiconductor substrate 11 to expose a portion, which is intended as an isolation region, and protect a portion, which is an alignment mark, on the scribe line of the semiconductor substrate 11.

Next, the semiconductor substrate 11 is etched to a predetermined depth by using the nitride film pattern 13 as an etching mask to form a trench. At this time, the semiconductor substrate 11 is 100 ~ 5000Å thickness is removed. (See Figure 3a)

Next, an oxide film 15 is formed on the structure, and the planarization is performed by performing a CMP process to remove the nitride film pattern 13. (See FIG. 3B, FIG. 3C)

A scribe line mask 17 is formed on the structure to expose the semiconductor substrate 11 on which the topology is formed. (See FIG. 3D)

Next, the oxide film 15 is removed by a photolithography process using the scribe line mask 17, but the semiconductor substrate 11 having the topology is exposed to be exposed, and the scribe line mask 17 is removed. do. In this case, the exposure process during the photolithography process using the scribe line mask 17 is performed on the entire surface or part of the mark. In addition, referring to FIG. 4, a scribe line 25, which is a mark used to align or measure the outer edge of the die 23, is positioned on the reticle 27, which is a photoresist pattern used in the photolithography process. In addition, the equipment used in the exposure process is to measure the overlap accuracy by using a wafer pattern such as contact hole (C / H), line / space (L / S), island, chevron Overlapping accuracy measuring equipment and exposure equipment such as NIKON NSR, CANON FPA, SVG-L MS and ASML PAS are used. (See FIGS. 3D, 3E, and 4)

Next, the gate electrode metal film 19 is formed on the structure, and the gate electrode mask 21 is formed using the semiconductor substrate 11 having the topology as an alignment mark. In this case, instead of using the gate electrode metal film 19, a material including a metal component may be used. (See FIG. 3F, FIG. 3G)

As described above, in the method of forming an alignment mark of a semiconductor device according to the present invention, a topology is formed in a device isolation region on a scribe line of a semiconductor substrate, a device isolation insulating film is formed, and a photolithography process using a scribe line mask. By removing the device isolation insulating layer so that the topology is exposed, there is an advantage of improving alignment or measuring accuracy in forming a word line from a material including a metal or a metal component using the topology as an alignment mark.

Claims (2)

In the method for forming an alignment mark of a semiconductor device, Exposing a portion intended to be an isolation region on an upper portion of the semiconductor substrate, and forming a nitride film pattern protecting the portion intended to be an alignment mark in the isolation region on the scrubber line outside the die; Forming a trench by etching the semiconductor substrate using the nitride film pattern as an etching mask; Forming an oxide film on the structure; Removing the oxide film by a CMP process; Removing the nitride film pattern; Forming a mask for a scribe line exposing the alignment mark on the structure; Forming an alignment mark by removing the oxide layer using the scribe line mask as an etching mask. The method of claim 1, And a depth of the trench is 100 to 5000 micrometers.