KR20000047048A - Method for forming alignment mark of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming an alignment mark of a semiconductor device is provided to easily measure an alignment or the degree of a superposition. CONSTITUTION: An interlayer insulating film(13), which includes a contact hole(15) exposing part to form a via contact in cell and peripheral circuit parts of a semiconductor substrate and part to form an alignment mark in a scribe line area, is formed. A conductive layer is formed on the upper of the structure in which the interlayer insulating film is formed. The conductive layer is flattened using CMP process to form the via contact hole. A contact plug for the alignment mark is formed on the scribe line area. A photosensitive pattern(19) exposing the scribe line area is formed on the upper of the structure. The contact plug is exposed as etching the interlayer insulating film using the photosensitive pattern as an etching mask. And then the photosensitive pattern is removed.

Description

Method of forming alignment mark of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming an alignment mark of a semiconductor device, and more particularly, to a method of forming an alignment mark of a semiconductor device by artificially forming an initial topology removed by a CMP process during a contact forming process.

In general, a highly integrated semiconductor device undergoes a complicated process in which a plurality of exposure masks are overlapped and used, and alignment between exposure masks used in stages is based on a mark of a specific shape.

The mark is called an alignment key or alignment mark, and is used for layer to layer alignment between different masks or between dies for one mask.

A stepper, which is a step and repeat type exposure apparatus used in a semiconductor device manufacturing process, is a device in which a stage moves in the X-Y direction and repeatedly moves in alignment. The stage is aligned automatically or manually on the basis of the alignment mark, the stage is mechanically operated, so that an alignment error occurs during the repeated process, and if the alignment error exceeds the allowable range, device defects are generated.

As described above, the adjustment range of the overlapping accuracy due to misalignment depends on the design rule of the device, and is usually about 20 to 30% of the design rule.

In addition, an overlay accuracy measurement mark for confirming that the alignment between the layers formed on the semiconductor substrate is correctly used is also used in the same manner as the alignment mark.

Conventional alignment marks and overlapping precision measurement marks are formed on a scribe line which is a portion where a chip is not formed in a semiconductor wafer, and a vernier alignment mark is used as a measuring method of misalignment using the alignment marks. It is compensated after measuring by the visual inspection method used and the automatic inspection method using a box in box or bar in bar alignment mark, but one side of the chip becomes weak as the device becomes highly integrated. It has a size of about 15 to 25 mm, and dozens of mask processes are performed, so that the overlay measuring marks formed on the scrabble lines may become blurred or damaged due to several subsequent processes. It can be inaccurate when measuring. In addition, in a highly integrated semiconductor device requiring a large number of exposure masks, it is necessary to measure the overlay accuracy between a plurality of layers, and thus a plurality of overlay measurement marks are formed on a scribe line and used for the measurement. At this time, the size of the overlay mark has a size of 70 × 70 μm ² and 30 or more are required for 256M DRAM. As a result, the area occupied by them becomes large, and various marks required in the semiconductor manufacturing process, for example, LSA, FIA, EM, etc., cannot be formed on the scribe line, or the position of the overlay measurement mark is not placed at the outermost corner, so that the measurement accuracy Drop or reduce process yield.

Hereinafter, with reference to the accompanying drawings will be described with respect to the prior art.

1A to 1D are process flowcharts illustrating a metal wiring forming process using a one step process, and FIGS. 2A to 2D are process flowcharts illustrating a metal wiring forming process using a two step process.

First, the metal wiring is formed in a one step process as follows.

A first metal wiring 101 is formed on the semiconductor substrate (not shown) on which a predetermined lower structure is formed and connected to the lower structure.

In addition, an interlayer insulating film 103 having a contact hole 105 exposing the first metal wiring 101 is formed on the first metal wiring 101. (See FIG. 1A)

Next, after the second metal wiring metal film is formed on the structure, the CMP process is performed to planarize until the metal film having a predetermined thickness remains. (See FIGS. 1B and 1C)

On the other hand, the process of forming the metal wiring in a two-step process is as follows.

A first metal wiring 102 connected to the lower structure is formed on the semiconductor substrate (not shown) where a predetermined lower structure is formed.

Next, an interlayer insulating film 104 having a contact hole 106 exposing the first metal wiring 102 is formed. (See Figure 2A)

Next, after the first metal film 108 is formed on the structure, the contact plug is formed by removing the first metal film 108 by performing a CMP process until the interlayer insulating film 104 is exposed. . (See Figures 2B and 2C)

Next, a second metal film 110 connected with the contact plug is formed. In this case, the initial topology may be removed due to the CMP process, and thus misalignment may be generated during subsequent metallization patterning. (See FIG. 2D)

As described above, the method for forming an alignment mark of a semiconductor device according to the related art makes it impossible to read the difference between the initial topology and the reflectance in the deposition process of an opaque metal film during the metallization forming process. In the normal metal film CMP process, since the level of the interlayer insulating film pattern is so large that the step for alignment or measurement remains, the initial topology of the interlayer insulating film pattern cannot be read as it is, but the surface of the metal film is still connected to the topology. You can read However, as described above, the CMP process of the metal film by the two-step process does not have a large initial topology, and since a considerable amount of the metal film is removed by the CMP process, the surface topology of the subsequently formed metal film is small so that accurate alignment and measurement accuracy can be obtained. There is no problem.

In order to solve the above problems of the prior art, the lack of the initial topology due to the metallization forming process and the CMP process is used by using the difference in the etch selectivity between the interlayer insulating film and the metal film only for the mark for measuring alignment or overlapping thereof. It is an object of the present invention to provide a method for forming an alignment mark of a semiconductor device which facilitates measurement of alignment or overlapping degree by forming an artificial initial topology through an entire surface etching process and connecting the initial topology to a surface topology.

1A to 1C are process flowcharts illustrating a metal wiring forming process using a one-step process.

2A to 2D are process flowcharts showing a metal wiring forming process using a two-step process.

Figure 3a to 3g is a process flow chart showing a metal wiring forming process using the alignment mark in accordance with the present invention.

Figure 4 is a plan view of the reticle for forming the alignment mark used in Figures 3a to 3g.

<Description of Signs of Major Parts of Drawings>

11, 101, 102: first metal wiring 13, 103, 104: interlayer insulating film

15, 105, 106: contact hole 17, 108: first metal film

107: metal film 19: photosensitive film pattern

21, 110: second metal film 23: metal wiring mask

25: Die 27: scribe line

29: reticle

In order to achieve the above object, a method of forming an alignment mark of a semiconductor device according to the present invention,

Forming an interlayer insulating film having contact portions exposing portions intended to be via contacts and portions intended to be alignment marks on the scribe line region in the cell portion and the peripheral circuit portion of the semiconductor substrate;

Forming a conductive layer on the structure;

Forming a via contact plug in the cell portion and the peripheral circuit portion by planarizing the conductive layer by a chemical mechanical polishing process, and forming a contact plug for an alignment mark on the scribe line region;

Forming a photoresist pattern on the structure to expose the scribe line region;

Etching the interlayer insulating film on the scribe line using the photoresist pattern as an etching mask to expose the alignment plug contact plug;

It characterized in that it comprises a step of removing the photosensitive film pattern.

Hereinafter, a method of forming an alignment mark of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

3A to 3G are process flowcharts illustrating a metal wiring forming process used as an alignment mark according to the present invention, and FIG. 4 is a plan view illustrating a reticle for forming the alignment mark used in FIGS. 3A to 3G.

First, a first metal wiring 11 is formed on an upper portion of a semiconductor substrate on which lower structures (not shown) such as word lines, bit lines, and capacitors are formed.

Next, an interlayer insulating layer 13 having a contact hole 15 exposing the first metal wiring 11 is formed on the first metal wiring 11. At this time, the structures are formed simultaneously on the scribe line and the cell portion and the peripheral circuit portion. (See Figure 3a)

Next, a first metal layer 17 is formed on the structure to be connected to the first metal wiring 11 through the contact hole 15. (See Figure 3b)

Then, the first metal film 17 is removed by a CMP process until the interlayer insulating film 13 is exposed to form a contact plug. (See Figure 3c)

Then, a photoresist film (not shown) is applied on the structure, followed by an exposure and development process using a reticle 29 to form an alignment mark to form a photoresist pattern 19 exposing the contact plug. In this case, the exposure process using the reticle 29 is performed on the entire surface or part of the mark, and a scribe line 27, which is a mark used to align or measure the outside of the die 25, is positioned on the reticle 29. In addition, the equipment used in the exposure process is to measure the overlap accuracy by using a wafer pattern such as contact hole (C / H), line / space (L / S), island, chevron Overlapping accuracy measuring equipment and exposure equipment such as NIKON NSR, CANON FPA, SVG-L MS and ASML PAS are used. (See FIG. 3D, FIG. 4)

Next, the interlayer insulating layer 13 is etched by using the photoresist pattern 19 as an etch mask to expose the contact plug, thereby artificially forming a topology to form alignment marks for subsequent processes. In this case, the interlayer insulating layer 13 may remove 5 to 95% of the original deposition thickness by using a dry or wet etching method.

Next, the photoresist pattern 19 is removed. (See Figure 3e)

A second metal film 21 is formed on the structure to be connected to the contact plug. (See Figure 3f)

Thereafter, a metal wiring mask 23 is formed on the second metal film 21. In this case, the mask 23 for metal wiring may be formed without misalignment by the alignment mark formed in the previous process. (See Fig. 3g)

The second metal film 21 is patterned by using the metal wiring mask 23 as an etching mask.

As described above, in the method of forming an alignment mark of a semiconductor device according to the present invention, an alignment mark region is formed on a contact hole and a scribe line region exposing a portion, which is intended as a contact, in a cell portion and a peripheral circuit portion of a semiconductor substrate after a metal wiring forming process. An interlayer insulating film having a contact hole exposing a predetermined portion is formed, a conductive layer is formed to fill the contact hole, and a CMP process is performed to form a contact plug and a contact plug for an alignment mark. Using a photoresist pattern exposing a region as an etch mask, the entire surface is etched to protrude the contact plug for the alignment mark to form a topology, thereby facilitating subsequent alignment or overlapping measurement.

Claims (1)

Forming an interlayer insulating film having contact portions exposing portions intended to be via contacts and portions intended to be alignment marks on the scribe line region in the cell portion and the peripheral circuit portion of the semiconductor substrate; Forming a conductive layer on the structure; Forming a via contact plug in the cell portion and the peripheral circuit portion by planarizing the conductive layer by a chemical mechanical polishing process, and forming a contact plug for an alignment mark on the scribe line region; Forming a photoresist pattern on the structure to expose the scribe line region; Etching the interlayer insulating film on the scribe line using the photoresist pattern as an etching mask to expose the alignment plug contact plug; And a process of removing the photosensitive film pattern.