CN114200790A - Method and device for reducing wafer overlay deviation - Google Patents

Method and device for reducing wafer overlay deviation Download PDF

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Publication number
CN114200790A
CN114200790A CN202210031910.0A CN202210031910A CN114200790A CN 114200790 A CN114200790 A CN 114200790A CN 202210031910 A CN202210031910 A CN 202210031910A CN 114200790 A CN114200790 A CN 114200790A
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China
Prior art keywords
wafer
actual
zero
determining
alignment
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CN202210031910.0A
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Chinese (zh)
Inventor
包晓明
叶甜春
朱纪军
罗军
李彬鸿
赵杰
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Guangdong Greater Bay Area Institute of Integrated Circuit and System
Ruili Flat Core Microelectronics Guangzhou Co Ltd
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Aoxin Integrated Circuit Technology Guangdong Co ltd
Guangdong Greater Bay Area Institute of Integrated Circuit and System
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Application filed by Aoxin Integrated Circuit Technology Guangdong Co ltd, Guangdong Greater Bay Area Institute of Integrated Circuit and System filed Critical Aoxin Integrated Circuit Technology Guangdong Co ltd
Priority to CN202210031910.0A priority Critical patent/CN114200790A/en
Publication of CN114200790A publication Critical patent/CN114200790A/en
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    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70591Testing optical components
    • G03F7/706Aberration measurement
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7088Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection

Abstract

The embodiment of the application discloses a method and a device for reducing wafer overlay deviation, wherein the method comprises the following steps: determining an alignment mark and a region to be detected of the wafer, wherein the alignment mark is used for determining a positioning coordinate of a zero-layer pattern, and the region to be detected is an exposure region of a preset zero-layer pattern; exposing the wafer to obtain an actual zero-layer graph; and measuring the wafer through a measuring system, and determining the pattern offset according to the alignment mark, the actual zero-layer pattern and the positioning coordinates of the preset zero-layer pattern, wherein the pattern offset is used for calculating the alignment precision of the photoetching machine so as to respond in time when the actual alignment precision of the photoetching machine is determined to be smaller than the alignment precision threshold. According to the technical scheme, the alignment mark is arranged and the method of measuring the coordinate system is adopted, so that the actual alignment precision of the photoetching machine can be determined according to the positioning coordinate of the zero-layer graph, the wafer alignment deviation caused by the conveying deviation of the mechanical arm can be corrected in time, and the resource waste is avoided.

Description

Method and device for reducing wafer overlay deviation
Technical Field
The embodiment of the application relates to the technical field of semiconductors, in particular to a method and a device for reducing wafer overlay deviation.
Background
When a photoetching machine carries out zero-layer exposure on a silicon wafer (wafer), the wafer needs to be grabbed and conveyed through a mechanical arm, the imaging position of a circuit diagram of the zero-layer pattern on the silicon wafer after exposure completely depends on the precision of a mechanical conveying arm and a pre-alignment system of the photoetching machine and the displacement precision of a slide platform, and when the pre-alignment precision exceeds a threshold value due to overhauling or faults of the mechanical arm, the circuit diagram exposed on the silicon wafer is subjected to larger deviation and the wafer is scrapped.
In the prior art, a method commonly used in IC manufacturing currently is to fixedly select several machines which are relatively stable, have high pre-alignment accuracy and low downtime frequency, and are specially used for zero-level lithography according to the exposure accuracy and capability of a lithography machine in a factory, so as to reduce the overlay deviation of a wafer in the exposure process of the lithography machine.
Disclosure of Invention
The embodiment of the application provides a method and a device for reducing wafer overlay deviation. The technical scheme is as follows:
in one aspect, a method for reducing wafer overlay deviation is provided, the method comprising:
determining an alignment mark and a region to be detected of the wafer, wherein the alignment mark is used for determining a positioning coordinate of a zero-layer pattern, and the region to be detected is an exposure region of a preset zero-layer pattern;
exposing the wafer to obtain an actual zero-layer graph, wherein the actual zero-layer graph is obtained by exposing a mechanical arm and a pre-alignment system of a photoetching machine according to actual alignment precision;
and measuring the wafer through a measuring system, and determining a graph offset according to the alignment mark, the actual zero-layer graph and the positioning coordinates of the preset zero-layer graph, wherein the graph offset is used for calculating the actual alignment precision of the photoetching machine so as to respond in time when the actual alignment precision is determined to be smaller than an alignment precision threshold.
Specifically, the determining the alignment mark and the region to be measured of the wafer includes:
determining a wafer photomask according to the size information of the wafer, wherein the wafer photomask is used for determining the exposable range of the wafer;
determining the circle center position of the wafer, and adding at least one alignment mark according to the size information, wherein the alignment mark is used for establishing a measurement coordinate system according to the circle center position;
according to the measurement coordinate system, the number of the areas to be measured is selected to be a preset number on the wafer, the number of the areas to be measured is positively correlated with the actual alignment precision of the photoetching machine, and the more the number of the areas to be measured is, the higher the actual alignment precision is, the more the measurement is, the determination is.
Specifically, the method further comprises: and determining four regions to be measured according to the established measurement coordinate system, wherein the four regions to be measured are respectively positioned in four quadrant regions of the measurement coordinate system.
Specifically, the exposing the wafer to obtain an actual zero-layer pattern includes:
acquiring a wafer shooting image in an exposure program, wherein the wafer shooting image comprises all preset zero-layer patterns needing to be exposed on the wafer, and the preset zero-layer patterns and the area to be detected belong to a one-to-one correspondence relationship;
and exposing the wafer according to the circle center coordinate of the measurement coordinate system and the wafer shooting image to obtain the actual zero-layer graph.
Specifically, the method further comprises: and determining a first positioning coordinate of the central point of the area to be measured according to the wafer shooting chart and the circle center coordinate of the measurement coordinate system, wherein the area to be measured is a regular area.
Specifically, the measuring the wafer by the measuring system, and determining a pattern offset according to the alignment mark and the positioning coordinates of the actual zero-layer pattern and the preset zero-layer pattern include:
determining a second positioning coordinate of the exposed actual zero-layer graph through the measuring system, wherein the actual zero-layer graph is located in an actual measurement area, and the actual measurement area is used for determining a central point of the actual zero-layer graph;
determining the graphics offset based on the first location coordinates and the second location coordinates.
Specifically, the determining the pattern offset based on the first positioning coordinate and the second positioning coordinate includes:
and determining the horizontal figure offset and the vertical figure offset according to the measurement coordinate system, the first positioning coordinate and the second positioning coordinate.
Specifically, the method further comprises: determining the actual alignment precision of the photoetching machine according to the sum of the transverse pattern offset and the longitudinal pattern offset;
and controlling the photoetching machine to stop running or sending out a precision early warning in response to the fact that the actual alignment precision is smaller than the alignment precision threshold.
Specifically, the method further comprises: acquiring the rotational offset of the mechanical arm through a transmission unit of the photoetching machine, wherein the rotational offset is obtained by converting a sensor on the mechanical arm according to the deflection action of the mechanical arm; determining the actual alignment precision of the photoetching machine according to the rotation offset; and/or the presence of a gas in the gas,
acquiring a deflection angle of a pre-alignment light source in a pre-alignment system through a transmission unit of the photoetching machine; and determining the actual alignment precision of the photoetching machine according to the deflection angle.
In another aspect, an apparatus for reducing wafer overlay bias is provided, the apparatus comprising:
the determining module is used for determining an alignment mark and a to-be-detected area of the wafer, wherein the alignment mark is used for determining the positioning coordinate of a zero-layer pattern, and the to-be-detected area is an exposure area of a preset zero-layer pattern;
the exposure module is used for exposing the wafer to obtain an actual zero-layer graph, and the actual zero-layer graph is obtained by exposing a mechanical arm and a pre-alignment system of the photoetching machine according to actual alignment precision;
and the measuring module is used for measuring the wafer through a measuring system, determining a graph offset according to the alignment mark and the positioning coordinates of the actual zero-layer graph and the preset zero-layer graph, wherein the graph offset is used for calculating the actual alignment precision of the photoetching machine so as to respond in time when the actual alignment precision is determined to be smaller than an alignment precision threshold.
In another aspect, a computer device is provided, the computer device comprising a processor and a memory; the memory stores at least one instruction for execution by the processor to implement the method of optimizing a lithographic pattern as claimed in the preceding claim.
The beneficial effect that above-mentioned technical scheme brought includes at least: before the photoetching machine exposes the wafer, a measurement coordinate system is established on the wafer by adding an alignment mark, and the actual alignment deviation of the photoetching machine is determined by selecting the position difference between the actual zero layer graph in the region to be measured and the exposed actual zero layer graph. When the actual alignment deviation exceeds the alignment precision threshold, a response is made in time, the wafer alignment deviation caused by the mechanical arm transmission deviation is corrected in time, the wafer alignment deviation is reduced, and resource waste is avoided.
Drawings
FIG. 1 is a wafer exposure map provided by an exemplary embodiment of the present application;
FIG. 2 is a flowchart of a method for reducing wafer overlay bias according to one embodiment of the present disclosure;
FIG. 3 is a flowchart of a method for reducing wafer overlay bias according to another embodiment of the present disclosure;
FIG. 4 is a comparison graph of wafer exposures provided by an exemplary embodiment of the present application;
FIG. 5 is a plot of a position fix for a zero layer pattern provided by an exemplary embodiment of the present application;
fig. 6 is a block diagram illustrating an apparatus for reducing wafer overlay deviation according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
Reference herein to "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.
In the related art, when a lithography machine performs zero-layer exposure on a wafer (silicon wafer), the imaging position of a circuit diagram on the wafer after exposure completely depends on the precision of a mechanical transfer arm and a pre-alignment system of the lithography machine and the displacement precision of a slide platform. If during the processing of the same batch of wafers (one LOT, usually 25 wafers), after exposing a part of the wafers, if the mechanical precision of the lithography machine changes, such as arm motion deviation, precision drop of the pre-alignment light source, emergency braking of the slide stage (emergency error), and the like.
However, the current mainstream lithography machines do not have real-time monitoring and timely warning for this, so the machine does not give an alarm or goes down, and the processing is still continued, so the patterns of the remaining unexposed chips and the exposed chips of the same batch of wafers may have large overlay deviation, which is mainly reflected in parameters such as offset (translation), expansion (expansion), and magnification (mag). When a subsequent photolithography process or some special processes such as wafer bonding (bonding) are performed, the difference of the alignment precision between the wafers in the same batch is large due to the difference of the zero layers of the wafers in the same batch during the re-exposure, which has an influence on the processes such as etching (etch) and bonding in the later period, and is directly reflected in the influence on the electrical performance or the rejection of the wafers due to the inability of bonding.
Referring to fig. 1, in IC manufacturing, a lot of wafers 11 usually need to produce a plurality of chips, such as 5 × 5 array chips, when a lithography machine performs zero-level exposure, the wafer 11 is exposed through a preset exposure array pattern, and finally a preset zero-level pattern 12 is exposed on the wafer, where the preset zero-level pattern 12 of the same lot of wafers 11 may be a zero-level circuit pattern or the like. Precisely because the motion deviation of the mechanical arm and the precision of the pre-alignment light source of the pre-alignment system are changed when the photoetching machine operates, the overlay precision of the photoetching machine is reduced, and finally the actual zero-layer pattern 13 which does not meet the subsequent processing requirement is exposed on the wafer 11. Currently, a common method in IC manufacturing is to fixedly select several machines, which are relatively stable, have high pre-alignment accuracy and low downtime frequency, and are specially used for zero-level lithography according to the capability of the lithography machines in a factory, so that the common phenomenon is that there are about 30 lithography machines in the factory, but about 4 to 6 lithography machines actually used for processing the zero level are different (depending on the type of the factory product). For mass production of lithography machines, if the lithography machines cannot be found and early-warned in time, serious resource waste can be caused.
Fig. 2 is a flowchart of a method for reducing wafer overlay deviation according to an embodiment of the present disclosure, which specifically includes the following steps:
step 201, determining an alignment mark and a region to be measured of the wafer, where the alignment mark is used to determine a positioning coordinate of the zero layer pattern, and the region to be measured is an exposure region of a preset zero layer pattern.
Before the photoetching machine carries out photoetching, an alignment mark and a region to be detected are arranged on the surface of a wafer according to the placement position of the wafer. The alignment mark is used for determining positioning coordinates when a zero-layer graph is subsequently etched, and the area to be measured is also positioned on the surface of the wafer and in the exposure area of the wafer.
Step 202, exposing the wafer to obtain an actual zero-layer pattern, wherein the actual zero-layer pattern is obtained by exposing a mechanical arm and a pre-alignment system of the photoetching machine according to actual alignment precision.
The mechanical arm of the photoetching machine can cause deviation in grabbing and transmission due to high-frequency vibration, and the pre-alignment light source of the alignment system of the photoetching machine can be suddenly reduced due to the differential precision. In addition, the actual alignment accuracy of the lithography machine can be changed by emergency braking of the slide platform. Therefore, the waste of resources is avoided to cause the wafer scrap in the production process. Therefore, the wafer can be exposed firstly, and the actual zero-layer pattern is detected and judged so as to determine the actual alignment precision of the photoetching machine.
And 203, measuring the wafer through the measuring system, and determining the pattern offset according to the alignment mark and the positioning coordinates of the actual zero-layer pattern and the preset zero-layer pattern.
And after the photoetching machine completes the exposure of the wafer according to the actual alignment progress, measuring the wafer through a measuring system, wherein the purpose of measuring is to calculate the actual alignment precision of the photoetching machine according to the actual zero-layer graph obtained by alignment on the wafer. The metrology system may be a metrology tool or a metrology module within a lithography machine. The measurement machine or the measurement module can obtain the alignment mark determined in the above process and the established measurement coordinate system. The measurement system calculates the positioning coordinates of the actual zero-layer pattern and the preset zero-layer pattern according to the alignment marks arranged on the wafer. Because actual alignment precision inevitably has alignment deviation, so the zero layer figure of the region to be measured has position deviation, and the measurement system determines the figure offset according to the position deviation. The pattern offset is used to calculate the actual overlay accuracy of the lithography machine. When the actual alignment precision of the photoetching machine is determined to be smaller than the alignment precision threshold value, the response can be made in time through the alarm system. For example, a self-calibration function is started to perform precision correction, or operation and maintenance personnel are prompted to perform maintenance so as to correct the overlay deviation of the lithography machine in time.
According to the technical scheme, before the photoetching machine exposes the wafer, the positioning coordinate of the zero layer graph is convenient to calculate subsequently by adding the alignment mark, and the actual alignment deviation of the photoetching machine is determined by selecting the actual zero layer graph in the region to be detected and the position difference of the exposed actual zero layer graph. When the actual alignment deviation exceeds the alignment precision threshold, timely response is made, the photoetching machine is timely overhauled, the alignment precision is corrected, the wafer alignment deviation is reduced, and resource waste is avoided.
Fig. 3 is a flowchart of a method for reducing wafer overlay deviation according to an embodiment of the present disclosure, which specifically includes the following steps:
step 301, determining a wafer mask according to the dimension information of the wafer, wherein the wafer mask is used for determining the exposable range of the wafer.
Before reading a wafer and exposing, a wafer mask needs to be designed in advance, the wafer mask is determined according to the wafer size information, and the wafer mask can cover all the exposable range of the wafer.
Step 302, determining the circle center position of the wafer, and adding at least one alignment mark according to the size information, wherein the alignment mark is used for establishing a measurement coordinate system according to the circle center position.
After the wafer photomask is determined, the alignment mark needs to be determined according to the wafer photomask, the setting position of the alignment mark is mapped in the exposure area on the wafer, the alignment mark is used for determining the positioning coordinate of the zero-layer graph, the positioning coordinate generally takes the circle center position of the wafer as the origin of the measurement coordinate system, and after the alignment mark is determined, the measurement coordinate system can be established according to the circle center and at least one alignment mark.
In one possible embodiment, two alignment marks may be selected, and the two alignment marks are used to determine the horizontal axis and the vertical axis of the measurement coordinate system, respectively, and establish the measurement coordinate system according to the circle center position. In addition, only one alignment mark may be provided, and the horizontal axis or the vertical axis (the two axes are 90 degrees apart) of the measurement coordinate system may be determined directly from the center position and the alignment mark.
Step 303, selecting a preset number of regions to be measured on the wafer according to the measurement coordinate system, wherein the number of the regions to be measured is positively correlated with the actual alignment precision of the lithography machine, and the more the number of the selected regions to be measured is, the higher the actual alignment precision determined by measurement is.
After the measurement coordinate system is established, a region to be measured is selected on the wafer, the region to be measured is also located in the exposure region, the region to be measured is the exposure region of a preset zero-layer pattern, and the preset zero-layer pattern is a pattern exposed on the surface of the wafer according to a wafer shooting diagram under an ideal state.
In general, the number of the regions to be measured is positively correlated with the actual alignment precision of the lithography machine, and the more the number of the selected regions to be measured is, the higher the actual alignment precision determined by measurement is.
In a possible implementation manner, after the measurement coordinate system is determined, one region to be measured may be selected from four quadrant regions of the measurement coordinate system, and the region to be measured is used for comparing with an actual exposure position after the subsequent exposure is completed, so as to determine the actual alignment precision.
As shown in fig. 4, a measurement coordinate system is established by the center of the wafer and the two alignment marks, and four regions to be measured are selected as measurement points in the four quadrant regions respectively (the dotted cross in the figure represents a preset zero layer image expected to be exposed).
Step 304, a wafer shot chart in the exposure program is obtained, wherein the wafer shot chart comprises all preset zero-layer graphs to be exposed on the wafer, and the preset zero-layer graphs and the area to be detected belong to a one-to-one correspondence relationship.
The wafer shot chart is a template chart of the lithography machine which needs to expose the wafer, and the wafer shot chart contains all the preset zero layer patterns selected from the above, for example, the preset zero layer pattern 12 in fig. 1 is the wafer shot chart designed in the exposure program.
It should be noted that, after the measurement coordinate system and the area to be measured are determined, the zero-layer pattern determined in the wafer shot diagram is correspondingly determined. For example, the regions to be measured determined in the measurement coordinate system are used for exposing #6 and #19 (the 6 th and 19 th zero-layer patterns), respectively, the 6 th and 19 th zero-layer patterns in the wafer shot diagram are subsequent measurement objects, that is, the preset zero-layer patterns and the regions to be measured belong to a one-to-one correspondence relationship.
And 305, exposing the wafer according to the circle center coordinate of the measurement coordinate system and the wafer shooting image to obtain an actual zero-layer graph.
After the measurement coordinate system is determined, an exposure program can be started, and the wafer is exposed according to the wafer shooting image to obtain an exposed actual zero-layer graph. As shown in fig. 1, 25 chips were obtained by exposure of the wafer.
And step 306, determining a first positioning coordinate of the central point of the area to be measured according to the wafer shooting chart and the circle center coordinate of the measurement coordinate system, wherein the area to be measured is a regular area.
The region to be measured in the above step is set as a regular region in order to conveniently determine the center point of the preset zero-layer image, as shown in fig. 4, the center point of the dotted-line square frame is used as the first positioning coordinate of the region to be measured, and dx 'and dy' respectively represent the values in the x-axis direction and the y-axis direction.
It should be noted that the actual zero layer pattern generated by exposure on the wafer is obtained by exposing the mechanical arm and the pre-alignment system of the lithography machine according to the actual overlay accuracy, and after the exposure is completed, the actual overlay accuracy needs to be calculated according to the actual zero layer pattern.
And 307, determining a second positioning coordinate of the exposed actual zero-layer graph through the measuring system, wherein the actual zero-layer graph is located in an actual measurement area, and the actual measurement area is used for determining a central point of the actual zero-layer graph.
Because the preset zero layer pattern and the measurement coordinate system are virtually set by a program, after the measurement coordinate system is determined, the first positioning coordinate can be correspondingly determined, but the actual zero layer pattern in the actual measurement area is exposed on the wafer. Therefore, after the exposure is completed, the second positioning coordinates of the actual zero-layer pattern in the actual measurement area (virtually defined, not displayed on the wafer) need to be measured by the measurement system (the actual measurement area and the area to be measured belong to a mapping relationship). As shown in fig. 4, an overlay deviation exists between the actual zero layer pattern and the preset zero layer pattern after the exposure of the lithography machine, and the foregoing steps have already determined that #6 and #19 are the objects to be measured, so that after the exposure is completed, the measurement system can automatically determine the actual measurement areas corresponding to #6 and # 19.
Step 308, determining a pattern offset based on the first positioning coordinates and the second positioning coordinates.
As shown in fig. 5, the first location coordinate of the preset zero layer pattern is represented as (dx ', dy'), and the second location coordinate of the actual zero layer pattern is represented as (dx, dy), so that it can be determined that the zero layer pattern has an offset Δ x ═ dx-dx 'in the horizontal direction and an offset Δ y ═ dy-dy' in the vertical direction.
In a possible implementation manner, a prealigned light source or a mechanical arm of the lithography machine deviates when moving transversely or longitudinally, and an exposure image may deviate transversely or longitudinally, so that when calculating the actual alignment precision, the actual alignment precision is determined according to the sum of the transverse pattern offset and the longitudinal pattern offset, and when the actual alignment precision is smaller than an alignment precision threshold, that is, the alignment error is too large, a warning or control should be timely given to the downtime of the lithography machine, and the exposure should be stopped. Otherwise, continuing to control the photoetching machine to perform exposure.
In another possible embodiment, the lateral pattern shift amount and/or the longitudinal pattern shift amount may be compared with a shift amount threshold, the shift amount threshold may be set according to the exposure process or thought, and after Δ x and/Δ y exceed the shift amount threshold, corresponding operations are performed.
In the analysis of the cause of the overlay deviation, it is mentioned that the imaging position on the wafer completely depends on the precision of a mechanical transmission arm and a pre-alignment system of the lithography machine and the displacement precision of a slide glass platform, in order to completely avoid using the lithography machine of which the actual overlay deviation does not meet the production requirement, sensor equipment can be further installed on the mechanical arm and the pre-alignment system of the lithography machine, in the exposure process of the lithography machine, the rotational offset of the mechanical arm and/or the deflection angle of the pre-alignment light source are obtained in real time through a transmission unit, the rotational offset is obtained through conversion according to the deflection action of the mechanical arm, and when the rotational offset of the mechanical arm and/or the deflection angle of the pre-alignment light source exceed a rotational offset threshold and/or a deflection angle threshold, the lithography machine is controlled to send an early warning or halt.
In summary, in the embodiment of the present application, before exposure, at least one alignment mark is marked according to a wafer mask, and a measurement coordinate system is established according to a center of a wafer circle, so that it is convenient to subsequently select a region to be measured and determine a first positioning coordinate of a preset zero layer pattern in the region to be measured; after exposure is finished, the measurement system determines an actual measurement area according to the area to be measured, and calculates a first positioning coordinate of a preset zero-layer graph and a second positioning coordinate of an actual zero-layer graph according to a measurement coordinate system;
furthermore, after the first positioning coordinate and the second positioning coordinate are determined, the actual alignment precision of the photoetching machine is calculated according to the horizontal pattern offset and the vertical pattern offset, so that under the condition that the actual alignment precision is smaller than an alignment precision threshold value, the corresponding operation can be performed in time, the wafer alignment deviation caused by the transmission deviation of the mechanical arm can be corrected in time, the wafer alignment deviation can be reduced, and the resource waste can be avoided.
Fig. 6 is a block diagram illustrating an apparatus for reducing wafer overlay deviation according to an embodiment of the present disclosure. The device includes:
the determining module 601 is configured to determine an alignment mark and a to-be-detected area of a wafer, where the alignment mark is used to determine a positioning coordinate of a zero-layer pattern, and the to-be-detected area is an exposure area of a preset zero-layer pattern;
an exposure module 602, configured to expose the wafer to obtain an actual zero-layer pattern, where the actual zero-layer pattern is obtained by exposing a mechanical arm and a pre-alignment system of a lithography machine according to actual overlay accuracy;
a measurement module 603, configured to measure the wafer through a measurement system, and determine a pattern offset according to the alignment mark and the positioning coordinates of the actual zero-layer pattern and the preset zero-layer pattern, where the pattern offset is used to calculate the actual overlay accuracy of the lithography machine, so as to respond in time when it is determined that the actual overlay accuracy is smaller than an overlay accuracy threshold.
In an embodiment of the present application, there is also provided a computer device, including a processor and a memory; the memory stores at least one instruction for execution by the processor to implement the method for optimizing a lithographic pattern provided by the various method embodiments described above.
The above description is of the preferred embodiment of the invention; it is to be understood that the invention is not limited to the particular embodiments described above, in that devices and structures not described in detail are understood to be implemented in a manner common in the art; any person skilled in the art can make many possible variations and modifications, or modify equivalent embodiments, without departing from the technical solution of the invention, without affecting the essence of the invention; therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

Claims (11)

1. A method for reducing wafer overlay bias, the method comprising:
determining an alignment mark and a region to be detected of the wafer, wherein the alignment mark is used for determining a positioning coordinate of a zero-layer pattern, and the region to be detected is an exposure region of a preset zero-layer pattern;
exposing the wafer to obtain an actual zero-layer graph, wherein the actual zero-layer graph is obtained by exposing a mechanical arm and a pre-alignment system of a photoetching machine according to actual alignment precision;
and measuring the wafer through a measuring system, and determining a graph offset according to the alignment mark, the actual zero-layer graph and the positioning coordinates of the preset zero-layer graph, wherein the graph offset is used for calculating the actual alignment precision of the photoetching machine so as to respond in time when the actual alignment precision is determined to be smaller than an alignment precision threshold.
2. The method of claim 1, wherein the determining the alignment mark and the region to be tested of the wafer comprises:
determining a wafer photomask according to the size information of the wafer, wherein the wafer photomask is used for determining the exposable range of the wafer;
determining the circle center position of the wafer, and adding at least one alignment mark according to the size information, wherein the alignment mark is used for establishing a measurement coordinate system according to the circle center position;
according to the measurement coordinate system, the number of the areas to be measured is selected to be a preset number on the wafer, the number of the areas to be measured is positively correlated with the actual alignment precision of the photoetching machine, and the more the number of the areas to be measured is, the higher the actual alignment precision is, the more the measurement is, the determination is.
3. The method according to claim 2, characterized in that four regions to be measured are determined according to the established measuring coordinate system, and the four regions to be measured are respectively located in four quadrant regions of the measuring coordinate system.
4. The method of any one of claims 1 to 3, wherein said exposing said wafer to obtain an actual zero layer pattern comprises:
acquiring a wafer shooting image in an exposure program, wherein the wafer shooting image comprises all preset zero-layer patterns needing to be exposed on the wafer, and the preset zero-layer patterns and the area to be detected belong to a one-to-one correspondence relationship;
and exposing the wafer according to the circle center coordinate of the measurement coordinate system and the wafer shooting image to obtain the actual zero-layer graph.
5. The method of claim 4, further comprising:
and determining a first positioning coordinate of the central point of the area to be measured according to the wafer shooting chart and the circle center coordinate of the measurement coordinate system, wherein the area to be measured is a regular area.
6. The method of claim 5, wherein said measuring said wafer by a measurement system and determining a pattern offset based on said alignment marks and said positioning coordinates of said actual zero layer pattern and said predetermined zero layer pattern comprises:
determining a second positioning coordinate of the exposed actual zero-layer graph through the measuring system, wherein the actual zero-layer graph is located in an actual measurement area, and the actual measurement area is used for determining a central point of the actual zero-layer graph;
determining the graphics offset based on the first location coordinates and the second location coordinates.
7. The method of claim 6, wherein the determining the graphic offset based on the first location coordinates and the second location coordinates comprises:
and determining the horizontal figure offset and the vertical figure offset according to the measurement coordinate system, the first positioning coordinate and the second positioning coordinate.
8. The method of any of claims 1 to 7, wherein after determining the lateral pattern offset and the longitudinal pattern offset, the method further comprises:
determining the actual alignment precision of the photoetching machine according to the sum of the transverse pattern offset and the longitudinal pattern offset;
and controlling the photoetching machine to stop running or sending out a precision early warning in response to the fact that the actual alignment precision is smaller than the alignment precision threshold.
9. The method according to any one of claims 1 to 8, further comprising:
acquiring the rotational offset of the mechanical arm through a transmission unit of the photoetching machine, wherein the rotational offset is obtained by converting a sensor on the mechanical arm according to the deflection action of the mechanical arm; determining the actual alignment precision of the photoetching machine according to the rotation offset; and/or the presence of a gas in the gas,
acquiring a deflection angle of a pre-alignment light source in a pre-alignment system through a transmission unit of the photoetching machine; and determining the actual alignment precision of the photoetching machine according to the deflection angle.
10. An apparatus for reducing wafer overlay bias, the apparatus comprising:
the determining module is used for determining an alignment mark and a to-be-detected area of the wafer, wherein the alignment mark is used for determining the positioning coordinate of a zero-layer pattern, and the to-be-detected area is an exposure area of a preset zero-layer pattern;
the exposure module is used for exposing the wafer to obtain an actual zero-layer graph, and the actual zero-layer graph is obtained by exposing a mechanical arm and a pre-alignment system of the photoetching machine according to actual alignment precision;
and the measuring module is used for measuring the wafer through a measuring system, determining a graph offset according to the alignment mark and the positioning coordinates of the actual zero-layer graph and the preset zero-layer graph, wherein the graph offset is used for calculating the actual alignment precision of the photoetching machine so as to respond in time when the actual alignment precision is determined to be smaller than an alignment precision threshold.
11. A computer device, wherein the computer device comprises a processor and a memory; the memory stores at least one instruction for execution by the processor to implement the method of optimizing a lithographic pattern according to any of claims 1 to 7.
CN202210031910.0A 2022-01-12 2022-01-12 Method and device for reducing wafer overlay deviation Pending CN114200790A (en)

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