CN101446768A - Zero layer alignment maker and preparation method - Google Patents
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Abstract
The invention provides a method for preparing zero layer alignment marker, comprising the steps as follows: a semiconductor underlayer which is sequentially provided with an oxidation cushion layer, a corrosion blocking layer and a photoresist is provided; a zero layer alignment marking pattern and a shallow channel pattern are defined on the photoresist layer; the photoresist layer is taken as a mask to etch the corrosion blocking layer, the oxidation cushion layer and the semiconductor underlayer and form the zero layer alignment marking channel and the shallow channel; after the photoresist layer is removed, the oxidation lining layer is formed on the internal wall of the zero layer alignment marking channel and the shallow channel; the zero layer alignment marking channel and the shallow channel are filled with insulated medium layer, thus forming the zero layer alignment marker and the shallow channel separation structure; subsequently, the corrosion blocking layer is removed. The invention also provides a zero layer alignment marker which simplifies the process steps.
Description
Technical field
The present invention relates to semiconductor devices and making field, relate in particular to zero layer alignment mark and method for making.
Background technology
Heal under the little situation in the semiconductor technology integrated level high technology size that heals, processing step complexity and degree of difficulty are also more and more high, therefore must in technology, carry out process monitoring by the utilization measurement equipment,, reduce loss because of process error caused with real-time reflection problem.
Photoetching process in the semiconductor technology one of the most very important step of can saying so.Every each layer pattern relevant with the MOS modular construction and doped region all are to be decided by photoetching process.And determine the factor of the photoetching process success or failure of wafer usually, (Critical Dimension, outside control CD), another important person is the degree of accuracy of aligning except critical size.As shown in Figure 1,, before carrying out photoetching process, all can in wafer 10, etch some patterns earlier, with as the alignment mark 12 of follow-up each layer in when exposure in order to accomplish the effect of aligning.
The manufacture craft of existing zero layer alignment mark such as Fig. 2 are to shown in Figure 6.With reference to figure 2, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 is a P type silicon substrate; Forming thickness on Semiconductor substrate 100 is the oxide layer 102 of 200 dusts～400 dusts, and the method for described formation oxide layer 102 is a thermal oxidation method, and oxidate temperature is 1000 ℃～1200 ℃, and the material of oxide layer 102 is a monox; On oxide layer 102, form first photoresist layer 104 with spin-coating method, first photoresist layer 104 is exposed and develops, definition zero layer alignment mark figure; With first photoresist layer 104 is mask, with dry etching method etching oxidation layer 102 and Semiconductor substrate 100, forms zero layer alignment marking channel 105, and the degree of depth of described zero layer alignment marking channel 105 in Semiconductor substrate 100 is 1000 dusts～2000 dusts.
As shown in Figure 3, ashing method is removed first photoresist layer 104, then, removes residual first photoresist layer 104 and oxide layer 102 with the wet etching method; On Semiconductor substrate 100, reach zero layer alignment marking channel, 105 inwalls and form pad oxide 106 and corrosion barrier layer 108 successively, the method of described formation pad oxide 106 is a thermal oxidation method, temperature required is 800 ℃～1000 ℃, pad oxide 106 thickness that form are 80 dusts～150 dusts, and material is a monox; The method of described formation corrosion barrier layer 108 is a chemical vapour deposition technique, and required depositing temperature is 700 ℃～800 ℃, and the thickness of the corrosion barrier layer 108 of formation is 1500 dusts～2500 dusts, and material is silicon nitride or silicon oxynitride etc.; Spin coating second photoresist layer 110 on corrosion barrier layer 108, and the full zero layer alignment marking channel 105 of second photoresist layer, 110 fillings through exposure imaging technology, define the isolation structure figure; With second photoresist layer 110 is mask, with plasma dry etching method etching corrosion barrier layer 108, pad oxide 106 and Semiconductor substrate 100, forms shallow trench 111, and the degree of depth of described shallow trench 111 in Semiconductor substrate 100 is 2000 dusts～5000 dusts.
As shown in Figure 4, ashing method is removed second photoresist layer 110; The polymkeric substance that pasc reaction produces in etching gas and the Semiconductor substrate 100 when removing formation shallow trench 111 with the wet etching method, the solution of described wet etching is hydrofluorite; Then, remove the second residual photoresist layer 110 with the wet etching method, described wet corrosion solution is the mixed solution that comprises sulfuric acid and hydrogen peroxide; Forming thickness at shallow trench 111 inwalls is the lining oxide layer 112 of 100 dusts～200 dusts, and the method for described formation lining oxide layer 112 is a thermal oxidation method, and oxidate temperature is 800 ℃～1200 ℃; On corrosion barrier layer 108, form the insulating medium layer 114 that thickness is 5000 dusts～7000 dusts with the high density plasma CVD method, and insulating medium layer 114 is filled full groove 105 and shallow trench 111, the material of described insulating medium layer 114 be monox or spin coating megohmite insulant (SOD, Spin-On-Dielectric) etc.
As shown in Figure 5, with chemical mechanical polishing method planarization insulating medium layer 114 to exposing corrosion barrier layer 108; Remove corrosion barrier layer 108 to exposing pad oxide 106 with the wet etching method, the fleet plough groove isolation structure 115 that formation is made of insulating medium layer 114 in the shallow trench 111 and lining oxide layer 112, described etching solution is the solution that comprises hydrofluorite and phosphoric acid, because zero layer alignment marking channel, 105 sidewalls have corrosion barrier layer 108, therefore in etching process, come along and removed, stay slit 116 at zero layer alignment marking channel, 105 sidewalls, influenced with the quality of insulating medium layer 114 as alignment mark, because the material of insulating medium layer 114 is a monox, in the subsequent optical carving technology, owing to the different reason of Semiconductor substrate 200 silicon materials refractive indexes, can be told, therefore be can be used as zero layer alignment mark.
As shown in Figure 6, on pad oxide 106, form the 3rd photoresist layer,, expose the insulating medium layer 114 in zero layer alignment marking channel 105 through overexposure and developing process; With the 3rd photoresist layer is mask, remove insulating medium layer 114 in the zero layer alignment marking channel 105 and the corrosion barrier layer 108 under the insulating medium layer 114 to exposing pad oxide 106 with the dry etching method, form zero layer alignment mark 118, because the material of pad oxide 106 also is a monox, therefore also can be used as zero layer alignment mark.
In application number is 02108451 Chinese patent application, can also find more information relevant with technique scheme, form the method for zero layer alignment mark.
In the process of existing formation zero layer alignment mark, owing to remove in the corrosion barrier layer process, with the corrosion barrier layer of trenched side-wall also come along except, make as the insulating medium layer of zero layer alignment mark imperfect, therefore the step that needs to increase exposure imaging and etching again to be removing insulating medium layer in the groove and the corrosion barrier layer insulating medium layer under, with the zero layer alignment marking channel that cover pad oxide as zero layer alignment mark.Increase exposure imaging and etch step, caused processing step loaded down with trivial details, influenced the technology progress.
Summary of the invention
The problem that the present invention solves provides a kind of zero layer alignment mark and method for making, in order to simplify processing step.
For addressing the above problem, the invention provides a kind of method for making of zero layer alignment mark, comprising: the Semiconductor substrate that has pad oxide, corrosion barrier layer and photoresist layer successively is provided; On photoresist layer, define zero layer alignment mark figure and shallow trench figure; With the photoresist layer is mask, and etching corrosion barrier layer, pad oxide and Semiconductor substrate form zero layer alignment marking channel and shallow trench; After removing photoresist layer, form lining oxide layer in zero layer alignment marking channel and shallow trench inwall; In zero layer alignment marking channel and shallow trench, fill full insulating medium layer, form zero layer alignment mark and fleet plough groove isolation structure; Remove corrosion barrier layer.
Optionally, the described zero layer alignment marking channel and the degree of depth of shallow trench in Semiconductor substrate are 2000 dusts～5000 dusts.
Optionally, define zero layer alignment mark figure and shallow trench figure and also comprise step: earlier treating on the lay photoetching mask plate exposed zero layer alignment mark figure transfer to photoresist layer,, form zero layer alignment mark figure through developing; Then treating on another lay photoetching mask plate exposed the shallow trench figure transfer to photoresist layer,, form the shallow trench figure through developing.
Optionally, define zero layer alignment mark figure and shallow trench figure and also comprise step: earlier treating on the lay photoetching mask plate exposed the shallow trench figure transfer to photoresist layer,, form the shallow trench figure through developing; Then treating on another lay photoetching mask plate exposed zero layer alignment mark figure transfer to photoresist layer,, form zero layer alignment mark figure through developing.
Optionally, described when in zero layer alignment marking channel and shallow trench, filling full insulating medium layer, on corrosion barrier layer, form insulating medium layer; Before removing corrosion barrier layer, the planarization insulating medium layer is to exposing corrosion barrier layer.
Optionally, the method for formation insulating medium layer is the high density plasma CVD method.The material of described insulating medium layer is monox or spin coating megohmite insulant.
The invention provides a kind of zero layer alignment mark, comprising: be positioned at zero layer alignment marking channel of Semiconductor substrate, be positioned at the lining oxide layer of zero layer alignment marking channel inwall, fill full insulating medium layer in the described zero layer alignment marking channel.
Optionally, the degree of depth of described zero layer alignment marking channel in Semiconductor substrate is 2000 dusts～5000 dusts.
Optionally, the material of described insulating medium layer is monox or spin coating megohmite insulant.
Compared with prior art, such scheme has the following advantages: remove in the corrosion barrier layer process, because zero layer alignment marking channel sidewall does not have corrosion barrier layer, therefore the insulating medium layer in the zero layer alignment marking channel can be kept perfectly, as zero layer alignment mark, therefore the step that does not need to increase exposure imaging and etching to be removing insulating medium layer in the groove and the corrosion barrier layer insulating medium layer under, with the zero layer alignment marking channel that cover pad oxide as zero layer alignment mark.Simplified processing step.
Further, zero layer alignment mark and fleet plough groove isolation structure form simultaneously, and processing step is more simplified, and improve productive rate.
Description of drawings
Fig. 1 is the synoptic diagram of existing zero layer alignment mark;
Fig. 2 to Fig. 6 is the synoptic diagram that existing technology forms zero layer alignment mark;
Fig. 7 is the embodiment process flow diagram that the present invention forms zero layer alignment mark;
Fig. 8 to Figure 12 is the embodiment synoptic diagram that the present invention forms zero layer alignment mark.
Embodiment
The present invention removes in the corrosion barrier layer process, because zero layer alignment marking channel sidewall does not have corrosion barrier layer, therefore the insulating medium layer in the zero layer alignment marking channel can be kept perfectly, as zero layer alignment mark, therefore the step that does not need to increase exposure imaging and etching to be removing insulating medium layer in the groove and the corrosion barrier layer insulating medium layer under, with the zero layer alignment marking channel that cover pad oxide as zero layer alignment mark.Simplified processing step.
Further, zero layer alignment mark and fleet plough groove isolation structure form simultaneously, and processing step is more simplified, and improve productive rate.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Fig. 7 is the embodiment process flow diagram that the present invention forms zero layer alignment mark.As shown in Figure 7, execution in step S101 provides the Semiconductor substrate that has pad oxide, corrosion barrier layer and photoresist layer successively;
Described Semiconductor substrate is a P type silicon substrate.The material of pad oxide is a monox etc., and thickness is 80 dusts～150 dusts; The thickness of corrosion barrier layer is 1500 dusts～2500 dusts, and material is silicon nitride or silicon oxynitride etc.
Execution in step S102 defines zero layer alignment mark figure and shallow trench figure on photoresist layer;
Defining zero layer alignment mark figure and shallow trench figure can step: earlier treating on the lay photoetching mask plate exposed zero layer alignment mark figure transfer to photoresist layer, through developing, form zero layer alignment mark figure; Then treating on another lay photoetching mask plate exposed the shallow trench figure transfer to photoresist layer,, form the shallow trench figure through developing.
Defining zero layer alignment mark figure and shallow trench figure also can step: earlier treating on the lay photoetching mask plate exposed the shallow trench figure transfer to photoresist layer, through developing, form the shallow trench figure; Then treating on another lay photoetching mask plate exposed zero layer alignment mark figure transfer to photoresist layer,, form zero layer alignment mark figure through developing.
Execution in step S103 is a mask with the photoresist layer, and etching corrosion barrier layer, pad oxide and Semiconductor substrate form zero layer alignment marking channel and shallow trench;
With plasma dry etching method etching corrosion barrier layer, pad oxide and Semiconductor substrate.
Execution in step S104 behind the removal photoresist layer, forms lining oxide layer in zero layer alignment marking channel and shallow trench inwall;
Earlier remove photoresist layer, remove residual photoresist layer with the wet etching method then with ashing method.
The method that forms lining oxide layer is a thermal oxidation method, and the material of lining oxide layer is a monox etc., and thickness is 100 dusts～200 dusts.
Execution in step S105 fills full insulating medium layer in zero layer alignment marking channel and shallow trench, form zero layer alignment mark and fleet plough groove isolation structure;
The method of filling full insulating medium layer is the high density plasma CVD method, and the material of described insulating medium layer is monox or spin coating megohmite insulant.
Execution in step S106 removes corrosion barrier layer.
Remove corrosion barrier layer with the wet etching method.
Zero layer alignment mark based on above-mentioned embodiment forms comprises: be positioned at zero layer alignment marking channel of Semiconductor substrate, be positioned at the lining oxide layer of zero layer alignment marking channel inwall, fill full insulating medium layer in the described zero layer alignment marking channel.
Fig. 8 to Figure 12 is the embodiment synoptic diagram that the present invention forms zero layer alignment mark.As shown in Figure 8, provide Semiconductor substrate 200, described Semiconductor substrate 200 is a P type silicon substrate; Forming thickness on Semiconductor substrate 200 is the pad oxide 202 of 80 dusts～150 dusts, and the method for described formation pad oxide 202 is a thermal oxidation method, and oxidate temperature is 800 ℃～1200 ℃, and the material of pad oxide 202 is a monox etc.; On pad oxide 202, form corrosion barrier layer 204, the method of described formation corrosion barrier layer 204 is a chemical vapour deposition technique, required depositing temperature is 700 ℃～800 ℃, and the thickness of the corrosion barrier layer 204 of formation is 1500 dusts～2500 dusts, and material is silicon nitride or silicon oxynitride etc.
In the present embodiment, the thickness concrete example of described pad oxide 202 is as 80 dusts, 90 dusts, 100 dusts, 110 dusts, 120 dusts, 130 dusts, 140 dusts or 150 dusts etc.The oxidate temperature concrete example is as 800 ℃, 900 ℃, 1000 ℃, 1100 ℃ or 1200 ℃ etc.
In the present embodiment, described chemical vapor deposition temperature concrete example is as 700 ℃, 720 ℃, 740 ℃, 760 ℃, 780 ℃ or 800 ℃ etc.The thickness concrete example of corrosion barrier layer 204 is as 1500 dusts, 1600 dusts, 1700 dusts, 1800 dusts, 1900 dusts, 2000 dusts, 2100 dusts, 2200 dusts, 2300 dusts, 2400 dusts or 2500 dusts etc.
As shown in Figure 9, on corrosion barrier layer 204, form photoresist layer 206, earlier treating on the lay photoetching mask plate exposed the shallow trench figure transfer to photoresist layer 206,, on photoresist layer 206, form shallow trench figure 207 through exposure imaging technology with spin-coating method; Then, again treating on another lay photoetching mask plate exposed zero layer alignment mark figure transfer to photoresist layer 206,, on photoresist layer 206, form zero layer alignment mark figure 208 through exposure imaging technology.
Except that present embodiment, can also be earlier treating on the lay photoetching mask plate to be exposed zero layer alignment mark figure transfer to photoresist layer 206, through exposure imaging technology, on photoresist layer 206, form zero layer alignment mark figure 208; And then treating on another lay photoetching mask plate exposed the shallow trench figure transfer to photoresist layer 206, through exposure imaging technology, on photoresist layer 206, form shallow trench figure 207.
As shown in figure 10, with photoresist layer 206 is mask, with plasma dry etching method etching corrosion barrier layer 204, pad oxide 202 and Semiconductor substrate 200, form zero layer alignment marking channel 210 and shallow trench 211, the described zero layer alignment marking channel 210 and the degree of depth of shallow trench 211 in Semiconductor substrate 200 are 2000 dusts～5000 dusts; Ashing method is removed photoresist layer 206; The polymkeric substance that pasc reaction produces in etching gas and the Semiconductor substrate 200 when removing formation zero layer alignment marking channel 210 and shallow trench 211 with the wet etching method, the solution of described wet etching is that concentration is 1% hydrofluoric acid solution, etching time is 20 seconds～40 seconds, concrete example was as 20 seconds, 22 seconds, 24 seconds, 26 seconds, 28 seconds, 30 seconds, 32 seconds, 34 seconds, 36 seconds, 38 seconds or 40 seconds etc., preferred 30 seconds; Then, remove residual photoresist layer 206 with the wet etching method, described wet etching solution is the mixed solution that comprises sulfuric acid and hydrogen peroxide.
In the present embodiment, the gas that the plasma dry etching method is adopted is chlorine and hydrogen bromide, wherein the flow of hydrogen is 20sccm (standard ml/min)～100sccm, and concrete flow is 20sccm, 30sccm, 40sccm, 50sccm, 60sccm, 70sccm, 80sccm, 90sccm or 100sccm etc. for example; The flow of hydrogen bromide is 100sccm～300sccm, and concrete flow is 100sccm, 120sccm, 140sccm, 160sccm, 180sccm, 200sccm, 220sccm, 240sccm, 260sccm, 280sccm or 300sccm etc. for example.
In the present embodiment, described zero layer alignment marking channel 210 and the degree of depth concrete example of shallow trench 211 in Semiconductor substrate 200 are as 2000 dusts, 2500 dusts, 3000 dusts, 3500 dusts, 4000 dusts, 4500 dusts or 5000 dusts etc.
As shown in figure 11, be the lining oxide layer 212 of 100 dusts～200 dusts in zero layer alignment marking channel 210 and shallow trench 211 inwalls formation thickness, the method for described formation lining oxide layer 212 is a thermal oxidation method, oxidate temperature is 800 ℃～1200 ℃; On corrosion barrier layer 204, form the insulating medium layer 214 that thickness is 5000 dusts～7000 dusts with the high density plasma CVD method, and insulating medium layer 214 is filled full zero layer alignment marking channel 210 and shallow trench 211, and the material of described insulating medium layer 214 is monox or spin coating megohmite insulant (SOD) etc.
In the present embodiment, the thickness concrete example of described lining oxide layer 212 is as 100 dusts, 120 dusts, 140 dusts, 160 dusts, 180 dusts or 200 dusts etc.Described oxidate temperature concrete example is as 800 ℃, 850 ℃, 900 ℃, 950 ℃, 1000 ℃, 1050 ℃, 1100 ℃, 1150 ℃ or 1200 ℃ etc.
In the present embodiment, the thickness concrete example of described insulating medium layer 214 on corrosion barrier layer 204 is as 5000 dusts, 5500 dusts, 6000 dusts, 6500 dusts or 7000 dusts etc.
As shown in figure 12, with chemical mechanical polishing method planarization insulating medium layer 214 to exposing corrosion barrier layer 204; Remove corrosion barrier layer 204 to exposing pad oxide 202 with the wet etching method, form zero layer alignment mark 216 and fleet plough groove isolation structure 217, described etching solution is hydrofluorite and phosphoric acid, be 2% hydrofluoric acid solution etching 50 seconds～70 seconds earlier promptly with concentration, and then with phosphoric acid solution etching 40 minutes～60 minutes.
In the present embodiment, with the time concrete example of hydrofluoric acid solution etching as 50 seconds, 52 seconds, 54 seconds, 56 seconds, 58 seconds, 60 seconds, 62 seconds, 64 seconds, 66 seconds, 68 seconds or 70 seconds etc., preferred 60 seconds; With the time concrete example of phosphoric acid solution etching as 40 minutes, 42 minutes, 44 minutes, 46 minutes, 48 minutes, 50 minutes, 52 minutes, 54 minutes, 56 minutes, 58 minutes or 60 minutes etc., preferred 50 minutes.
Zero layer alignment mark 216 and fleet plough groove isolation structure 217 form simultaneously, and processing step is more simplified, and improve productive rate.And in removing the corrosion barrier layer process, because zero layer alignment marking channel sidewall does not have corrosion barrier layer, therefore the insulating medium layer in the zero layer alignment marking channel can be kept perfectly, as zero layer alignment mark, therefore do not need to increase the step of exposure imaging and etching with insulating medium layer in the removal groove and the corrosion barrier layer under the insulating medium layer, as zero layer of alignment mark, simplified processing step with the zero layer alignment marking channel that cover pad oxide.
Zero layer alignment mark based on the foregoing description forms comprises: Semiconductor substrate 200; Be positioned at the pad oxide 202 on the Semiconductor substrate 200; Be positioned at Semiconductor substrate 200 and run through zero layer alignment marking channel 210 of pad oxide 202; Be positioned at the lining oxide layer 212 of zero layer alignment marking channel, 210 inwalls; Fill the insulating medium layer 214 in the full alignment marking channel 210.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (10)
1. the method for making of one kind zero layer alignment mark is characterized in that, comprising:
The Semiconductor substrate that has pad oxide, corrosion barrier layer and photoresist layer successively is provided;
On photoresist layer, define zero layer alignment mark figure and shallow trench figure;
With the photoresist layer is mask, and etching corrosion barrier layer, pad oxide and Semiconductor substrate form zero layer alignment marking channel and shallow trench;
After removing photoresist layer, form lining oxide layer in zero layer alignment marking channel and shallow trench inwall;
In zero layer alignment marking channel and shallow trench, fill full insulating medium layer, form zero layer alignment mark and fleet plough groove isolation structure;
Remove corrosion barrier layer.
2. according to the method for making of the described zero layer alignment mark of claim 1, it is characterized in that the described zero layer alignment marking channel and the degree of depth of shallow trench in Semiconductor substrate are 2000 dusts～5000 dusts.
3. according to the method for making of the described zero layer alignment mark of claim 1, it is characterized in that, define zero layer alignment mark figure and shallow trench figure and also comprise step:
Earlier treating on the lay photoetching mask plate exposed zero layer alignment mark figure transfer to photoresist layer,, form zero layer alignment mark figure through developing;
Then treating on another lay photoetching mask plate exposed the shallow trench figure transfer to photoresist layer,, form the shallow trench figure through developing.
4. according to the method for making of the described zero layer alignment mark of claim 1, it is characterized in that, define zero layer alignment mark figure and shallow trench figure and also comprise step:
Earlier treating on the lay photoetching mask plate exposed the shallow trench figure transfer to photoresist layer,, form the shallow trench figure through developing;
Then treating on another lay photoetching mask plate exposed zero layer alignment mark figure transfer to photoresist layer,, form zero layer alignment mark figure through developing.
5. according to the method for making of the described zero layer alignment mark of claim 1, it is characterized in that, described when in zero layer alignment marking channel and shallow trench, filling full insulating medium layer, on corrosion barrier layer, form insulating medium layer;
Before removing corrosion barrier layer, the planarization insulating medium layer is to exposing corrosion barrier layer.
6. according to the method for making of the described zero layer alignment mark of claim 5, it is characterized in that the method that forms insulating medium layer is the high density plasma CVD method.
7. according to the method for making of the described zero layer alignment mark of claim 6, it is characterized in that the material of described insulating medium layer is monox or spin coating megohmite insulant.
8. one kind zero layer alignment mark comprises: be positioned at zero layer alignment marking channel of Semiconductor substrate, be positioned at the lining oxide layer of zero layer alignment marking channel inwall, it is characterized in that, fill full insulating medium layer in the described zero layer alignment marking channel.
9. described according to Claim 8 zero layer alignment mark is characterized in that, the degree of depth of described zero layer alignment marking channel in Semiconductor substrate is 2000 dusts～5000 dusts.
10. described according to Claim 8 zero layer alignment mark is characterized in that the material of described insulating medium layer is monox or spin coating megohmite insulant.
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| CN108375871B (en) * | 2018-02-06 | 2021-08-24 | 武汉新芯集成电路制造有限公司 | Mask plate, manufacturing method and alignment method |
| US11143973B2 (en) | 2019-01-25 | 2021-10-12 | Powerchip Semiconductor Manufacturing Corporation | Method for designing photomask |
| CN114424124A (en) * | 2019-09-19 | 2022-04-29 | Asml荷兰有限公司 | Method for designing alignment mark |
| CN113140500A (en) * | 2021-04-19 | 2021-07-20 | 上海积塔半导体有限公司 | Method for manufacturing semiconductor structure |
| CN113140500B (en) * | 2021-04-19 | 2023-08-22 | 上海积塔半导体有限公司 | Method for manufacturing semiconductor structure |
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| CN115116936A (en) * | 2022-06-29 | 2022-09-27 | 武汉新芯集成电路制造有限公司 | Semiconductor device comprising LDMOS transistor and manufacturing method thereof |
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