CN103035511A - Method for producing zero layer photoetching marking of high-voltage device without barrier layers - Google Patents
Method for producing zero layer photoetching marking of high-voltage device without barrier layers Download PDFInfo
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Abstract
The invention discloses a method for producing zero layer photoetching marking of a high-voltage device without barrier layers. The method for producing the zero layer photoetching marking of the high-voltage device without the barrier layers comprises the following steps: (1) etching a zero layer lithography marking groove, (2) depositing a layer of medium layer and removing medium layers of regions outside the zero layer lithography marking groove, (3) etching a deep groove, (4) selectively growing an epitaxial layer on a silicon substrate, (5) removing anti-configuration epitaxial materials deposited on the silicon substrate in the epitaxial growth process of epitaxial layer, (6) etching away a medium layer inside the zero layer lithography marking groove by the adoption of the method of wet etching and leaving a zero layer lithography marking graph. Through the method for producing the zero layer photoetching marking of the high-voltage device without the barrier layers, lithography markings which are easy to recognize can be formed on the high-voltage device without the barrier layers, and therefore a follow-up film layer can be directed at conveniently, smooth of technological process can be guaranteed, and good yield of a product is improved.
Description
Technical field
The present invention relates to a kind of semiconductor technology method, be specifically related to a kind of method of zero layer photoetching mark of the high pressure resistant device of making unobstructed layer.
Background technology
A kind of novel semiconductor device occurred in now semiconductor power is used, this semiconductor device can either improve puncture voltage can reduce again resistance under the conducting state.The PN post layer that it has alternative arrangement plays the effect of the super junction (super junction) as drift layer.
The method of etching and filling deep trench in the super junction MOS transistor manufacture process, at n+ type silicon substrate growth one deck n-type epitaxial loayer (monocrystalline silicon), then one or more layers oxide-film of deposit or nitride film on this epitaxial loayer, etching deep trench again, and carry out selective epitaxial with p-type monocrystalline silicon and fill this deep trench, use at last cmp (CMP) technique to carry out flattening surface.This deep groove structure is as the p-type semiconductor column at this moment, and the both sides of this deep groove structure have namely obtained p-type and the N-shaped semiconductor column of vertical alternative arrangement as the N-shaped semiconductor column.
In the said method in monocrystalline silicon selective epitaxial process, the etching gas that need to improve fillibility and introduce can cause lateral etching and the generation bottom otch of the monocrystalline substrate top oxide layer that exposes of deep trench both sides, silicon substrate in the otch exposes at this moment, can be filled by silicon epitaxy again subsequently.Because this part epitaxial loayer is present in the oxide-film lower surface, and silicon substrate formation one, horizontal direction is difficult to remove in planarization process along the dorsad part extension of groove.Remove technique at the subsequent oxidation film, be not removed if be filled in the epitaxial loayer of this part otch the inside, will form the silicon ridge in the both sides of groove, affect some electric property of device.
If carry out photoetching and the etching of deep trench with the method on barrier layer, can't guarantee that the silicon ridge can be removed, therefore can't use the assembly of one or more layers oxide layer or nitration case to be used as the barrier layer of etching.
Zero layer photoetching mark generally is to adopt first to expose, develops, and then produces through the method for over etching, and its surfacial pattern zone must the certain offset (step height) of maintenance, and this mark could work at mask aligner.And high pressure resistant device is owing to being directly to carry out deep plough groove etched and the formation figure at silicon substrate, and then fill deep trench with epitaxy technology, because the existence of unobstructed layer in zero layer cursor figure, can cause when filling deep trench, epitaxial loayer also can be filled in the figure of zero layer photoetching mark, and deep trench filler and silicon substrate all are monocrystalline, in follow-up cmp flow process, owing to causing offset too little without high selectivity, this photo-etching mark is beyond recognition, and causes can't using in the follow-up technique this zero layer pattern, for the aligning of subsequent film brings difficulty, affect the smooth and easy of technological process, and then can affect the yield of product.
As shown in Figure 1, zero layer photoetching mark is filled by epitaxial loayer (EPI), is beyond recognition.
Summary of the invention
Technical problem to be solved by this invention provides a kind of method of zero layer photoetching mark of the high tension apparatus of making unobstructed layer, and it can form the zero layer photoetching mark of easy identification.
For solving the problems of the technologies described above, the technical solution of method of zero layer photoetching mark that the present invention makes the high tension apparatus of unobstructed layer is:
May further comprise the steps:
The first step forms one deck photoresistance at silicon substrate, and carries out exposure imaging at silicon substrate; Then etch zero layer photoetching mark groove at silicon substrate; The degree of depth of zero layer photoetching mark groove is 0.1～10 micron, and width is 1～10 micron, and length is 1～10 micron; The pattern of groove is vertical or tilts;
Wherein zero layer photoetching mark groove is preferably dimensioned to be: 0.5～5 micron of the degree of depth, 1～6 micron of width, 1～10 micron of length.
Second step is removed the photoresistance on the silicon substrate; Then deposit a layer thickness is 0.1～10 micron dielectric layer on silicon substrate; Remove zero layer photoetching mark groove with the dielectric layer of exterior domain by cmp afterwards; Described dielectric layer is oxide-film or nitride film;
Wherein dielectric layer is generated by the method for decompression or aumospheric pressure cvd; Dielectric layer fills up zero layer photoetching mark groove, perhaps covers the Partial Height of zero layer photoetching mark groove, does not namely fill up zero layer photoetching mark groove.
Wherein the thickness of dielectric layer is preferably 0.1～1 micron.
The employed lapping liquid of cmp is for comprising silicon dioxide and containing akaline liquid stabilizer hydroxy.
The 3rd step formed one deck photoresistance at silicon substrate, etched deep trench with the method for dry etching; The degree of depth of deep trench is 10～100 microns, and width is 1～10 micron; Then the photoresistance on the silicon substrate is removed;
Wherein deep trench is preferably dimensioned to be: 30～100 microns of the degree of depth, 1～5 micron of width.
In the 4th step, selective growth one deck epitaxial loayer makes epitaxial loayer that deep trench is filled up on silicon substrate; The deposition thickness of epitaxial loayer is 0.5～5 micron;
Wherein the deposition thickness of epitaxial loayer is preferably 0.5～2.5 micron.
The method of selective growth epitaxial loayer adopts the rpcvd method, and comes selective growth at silicon chip surface with etching gas chlorination hydrogen.
In the 5th step, with the mode of cmp the transoid epitaxial material that is deposited in the epitaxial process on the silicon substrate is removed;
The 6th step etched away the dielectric layer in the zero layer photoetching mark groove with the method for wet etching, stayed zero layer photoetching marker graphic.
In the wet etching process, for the oxide film dielectric layer, employed etching liquid is buffered hydrofluoric acid, and the concentration of buffered hydrofluoric acid liquid is 0.01～20%, and etch amount is 0.1～1 micron; For the nitride film dielectric layer, employed etching liquid is phosphoric acid solution, and the temperature of solution is 150～200 ℃, and the concentration of solution is 20～80%, and etch amount is 0.1～1 micron.
The technique effect that the present invention can reach is:
The present invention forms first the groove of zero layer photoetching mark, and this groove can be pattern vertical or that tilt; Rear deposit one deck dielectric layer, this dielectric layer can use oxide-film or nitride film; With cmp all the other the regional dielectric layers the dielectric layer in cursor are removed fully subsequently; And then carry out the flow process of etching, selective epitaxial precipitation and the cmp of follow-up deep trench; At last the dielectric layer in the cursor is removed, stayed the cursor figure.
The present invention can form at the high tension apparatus of unobstructed layer the easily photo-etching mark of identification, makes things convenient for the aligning of subsequent film, can guarantee the smooth and easy of technological process, improves the yield of product.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the schematic diagram that adopts the formed zero layer photoetching mark of prior art;
Fig. 2 to Figure 12 is concrete technology step schematic diagram;
Figure 13 is the schematic diagram of the formed zero layer photoetching mark of method of the zero layer photoetching mark of the present invention's high tension apparatus of making unobstructed layer.
Description of reference numerals among the figure:
1 is silicon substrate, and 2 is photoresistance (PR),
3 is dielectric layer, and 4 is the selective epitaxial precipitation layer.
Embodiment
The present invention makes the method for zero layer photoetching mark of the high tension apparatus of unobstructed layer, may further comprise the steps:
The first step forms one deck photoresistance 2 at as shown in Figure 2 silicon substrate 1, and carries out exposure imaging at silicon substrate 1, as shown in Figure 3; Then etch zero layer photoetching mark groove at silicon substrate 1, as shown in Figure 4; The degree of depth of zero layer photoetching mark groove is 0.1～10 micron, and width is 1～10 micron, and length is 1～10 micron; The pattern of groove is vertical or tilts all can;
Zero layer photoetching mark groove is preferably dimensioned to be: 0.5～5 micron of the degree of depth, 1～6 micron of width, 1～10 micron of length;
Second step is removed the photoresistance 2 on the silicon substrate 1, as shown in Figure 5; Then deposit one deck dielectric layer 3 on silicon substrate 1, as shown in Figure 6; The thickness of dielectric layer 3 is 0.1～10 micron, and dielectric layer 3 can be generated by the method for decompression or aumospheric pressure cvd; Dielectric layer can be oxide-film or nitride film; This dielectric layer can fill up zero layer photoetching mark groove, also can not fill up zero layer photoetching mark groove;
The thickness of dielectric layer 3 is preferably 0.1～1 micron,
Remove zero layer photoetching mark groove with the dielectric layer 3 of exterior domain, as shown in Figure 7 by cmp afterwards;
The employed lapping liquid of cmp is for comprising silicon dioxide and containing akaline liquid stabilizer hydroxy, and is residual without dielectric layer 3 to guarantee the zone except zero layer photoetching mark groove;
The 3rd step as shown in Figure 8, formed one deck photoresistance 2 at silicon substrate 1, etched deep trench with the method for dry etching; The degree of depth of deep trench is 10～100 microns, and width is 1～10 micron;
Deep trench is preferably dimensioned to be: 30～100 microns of the degree of depth, 1～5 micron of width;
Then the photoresistance 2 on the silicon substrate 1 is removed, as shown in Figure 9;
In the 4th step, selective growth one deck epitaxial loayer 4 on silicon substrate 1 makes epitaxial loayer 4 that deep trench is filled up, as shown in figure 10; The deposition thickness of this epitaxial loayer 4 is 0.5～5 micron;
The deposition thickness of epitaxial loayer 4 is preferably 0.5～2.5 micron;
The method of selective growth epitaxial loayer 4 adopts the rpcvd method, and comes selective growth at silicon chip surface with etching gas chlorination hydrogen, to prevent too early sealing in deep trench in the growth course, has avoided hole to produce;
The 5th step, with the mode of cmp the transoid epitaxial material that is deposited in the epitaxial process on the silicon substrate 1 is removed, with its planarization, form the PN post layer of alternative arrangement, as shown in figure 11;
Employed lapping liquid is the lapping liquid that monocrystalline silicon relative medium layer 3 has high selectivity in the chemical mechanical planarization process, removes totally with the transoid epitaxial loayer of guaranteeing silicon substrate 1 top, meanwhile dielectric layer 3 frees of losses in the zero layer photoetching mark groove; Can use the fixedly method of milling time;
The 6th step etched away the dielectric layer 3 in the zero layer photoetching mark groove with the method for wet etching, stayed zero layer photoetching marker graphic, as shown in figure 12;
Employed liquid is for having the liquid of high selectivity in the wet etching process with respect to the oxide film dielectric layer, and described etching liquid comprises that dilute hydrofluoric acid, buffered hydrofluoric acid etc. have the liquid of etching to oxide-film;
The concentration of buffered hydrofluoric acid liquid is 0.01～20%, and etch amount is 0.1～1 micron;
Or hot phosphoric acid solution etc. has the solution of high selectivity with respect to the nitride film dielectric layer, and its solution concentration is 20～80%, and etch amount is 0.1～1 micron.
For adopting the formed zero layer photoetching marker graphic of the present invention, can use as shown in figure 13.
Claims (10)
1. the method for the zero layer photoetching mark of the high tension apparatus of the unobstructed layer of making is characterized in that, may further comprise the steps:
The first step forms one deck photoresistance at silicon substrate, and carries out exposure imaging at silicon substrate; Then etch zero layer photoetching mark groove at silicon substrate; The degree of depth of zero layer photoetching mark groove is 0.1～10 micron, and width is 1～10 micron, and length is 1～10 micron; The pattern of groove is vertical or tilts;
Second step is removed the photoresistance on the silicon substrate; Then deposit a layer thickness is 0.1～10 micron dielectric layer on silicon substrate; Remove zero layer photoetching mark groove with the dielectric layer of exterior domain by cmp afterwards; Described dielectric layer is oxide-film or nitride film;
The 3rd step formed one deck photoresistance at silicon substrate, etched deep trench with the method for dry etching; The degree of depth of deep trench is 10～100 microns, and width is 1～10 micron; Then the photoresistance on the silicon substrate is removed;
In the 4th step, selective growth one deck epitaxial loayer makes epitaxial loayer that deep trench is filled up on silicon substrate; The deposition thickness of epitaxial loayer is 0.5～5 micron;
In the 5th step, with the mode of cmp the transoid epitaxial material that is deposited in the epitaxial process on the silicon substrate is removed;
The 6th step etched away the dielectric layer in the zero layer photoetching mark groove with the method for wet etching, stayed zero layer photoetching marker graphic.
2. the method for the zero layer photoetching mark of the high tension apparatus of the unobstructed layer of making according to claim 1 is characterized in that, zero layer photoetching mark groove is of a size of in the described first step: 0.5～5 micron of the degree of depth, 1～6 micron of width, 1～10 micron of length.
3. the method for the zero layer photoetching mark of the high tension apparatus of the unobstructed layer of making according to claim 1 is characterized in that, the dielectric layer in the described second step is generated by the method for decompression or aumospheric pressure cvd.
4. the method for the zero layer photoetching mark of the high tension apparatus of the unobstructed layer of making according to claim 1 is characterized in that, the dielectric layer in the described second step fills up zero layer photoetching mark groove, perhaps covers the Partial Height of zero layer photoetching mark groove.
5. the method for the zero layer photoetching mark of the high tension apparatus of the unobstructed layer of making according to claim 1 is characterized in that, the thickness of the dielectric layer in the described second step is 0.1～1 micron.
6. the method for the zero layer photoetching mark of the high tension apparatus of the unobstructed layer of making according to claim 1 is characterized in that, the employed lapping liquid of described second step cmp is for comprising silicon dioxide and containing akaline liquid stabilizer hydroxy.
7. the method for the zero layer photoetching mark of the high tension apparatus of the unobstructed layer of making according to claim 1 is characterized in that, deep trench is of a size of in described the 3rd step: 30～100 microns of the degree of depth, 1～5 micron of width.
8. the method for the zero layer photoetching mark of the high tension apparatus of the unobstructed layer of making according to claim 1 is characterized in that, the deposition thickness of epitaxial loayer is 0.5～2.5 micron in described the 4th step.
9. the method for the zero layer photoetching mark of the high tension apparatus of the unobstructed layer of making according to claim 1, it is characterized in that, the method of selective growth epitaxial loayer adopts the rpcvd method in described the 4th step, and comes selective growth at silicon chip surface with etching gas chlorination hydrogen.
10. the method for the zero layer photoetching mark of the high tension apparatus of the unobstructed layer of making according to claim 1, it is characterized in that, in the wet etching process in described the 6th step, for the oxide film dielectric layer, employed etching liquid is buffered hydrofluoric acid, the concentration of buffered hydrofluoric acid liquid is 0.01～20%, and etch amount is 0.1～1 micron; For the nitride film dielectric layer, employed etching liquid is phosphoric acid solution, and the temperature of solution is 150～200 ℃, and the concentration of solution is 20～80%, and etch amount is 0.1～1 micron.
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| CN104409348A (en) * | 2014-11-10 | 2015-03-11 | 成都士兰半导体制造有限公司 | Method for manufacturing trench device |
| CN104752323A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof |
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| CN104752323B (en) * | 2013-12-27 | 2018-03-20 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof |
| CN104952849A (en) * | 2014-03-31 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Alignment structure for silicon through hole manufacture and method for manufacturing silicon through hole |
| CN104952849B (en) * | 2014-03-31 | 2019-01-08 | 中芯国际集成电路制造(上海)有限公司 | The production method of align structures and through silicon via for through silicon via production |
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| CN104409348A (en) * | 2014-11-10 | 2015-03-11 | 成都士兰半导体制造有限公司 | Method for manufacturing trench device |
| CN104882436A (en) * | 2015-03-31 | 2015-09-02 | 上海华虹宏力半导体制造有限公司 | Preparation method for lithography alignment mark in two epitaxial processes |
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| CN105789181B (en) * | 2016-01-29 | 2018-08-21 | 上海华虹宏力半导体制造有限公司 | A kind of reverse phase photoetching alignment mark and its production method |
| CN105789181A (en) * | 2016-01-29 | 2016-07-20 | 上海华虹宏力半导体制造有限公司 | Anti-phase lithography aligning mark and manufacturing method thereof |
| CN108063121A (en) * | 2016-11-08 | 2018-05-22 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method, electronic device |
| CN108127582A (en) * | 2017-12-13 | 2018-06-08 | 湖北鼎汇微电子材料有限公司 | A kind of mold and preparation method for preparing polishing layer |
| CN112510016A (en) * | 2020-12-08 | 2021-03-16 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN112563246A (en) * | 2020-12-18 | 2021-03-26 | 河源市众拓光电科技有限公司 | Photoetching overlay mark and preparation method thereof |
| CN112992773A (en) * | 2021-02-04 | 2021-06-18 | 华虹半导体(无锡)有限公司 | Alignment mark forming method for deep trench isolation and semiconductor device structure |
| CN112992773B (en) * | 2021-02-04 | 2022-09-20 | 华虹半导体(无锡)有限公司 | Alignment mark forming method for deep trench isolation and semiconductor device structure |
| CN113675174A (en) * | 2021-08-17 | 2021-11-19 | 青岛佳恩半导体科技有限公司 | Preparation method for improving Mark point morphology of power device |
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