CN104952849A - Alignment structure for silicon through hole manufacture and method for manufacturing silicon through hole - Google Patents
Alignment structure for silicon through hole manufacture and method for manufacturing silicon through hole Download PDFInfo
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Abstract
The present invention provides an alignment structure for silicon through hole manufacture and a method for manufacturing a silicon through hole. The alignment structure comprises a substrate, an interlayer dielectric layer arranged on the surface of the substrate, a first dielectric layer arranged on the surface of the interlayer dielectric layer far from the substrate, a groove which goes through the interlayer dielectric layer and the first dielectric layer, a metal layer which is arranged along the inner wall of the groove, and a nitride layer arranged on the metal layer. The groove is provided with a recess which is arranged on the nitride layer. Since the groove is internally provided with the recess, after a first metal interconnection layer is formed, due to the existence of the recess, the recess is needed to be filled when the first metal interconnection layer is manufactured and a small recess is formed at the surface of the first metal interconnection layer, thus when the groove is used to carry out alignment, the alignment structure can be rapidly found and aligned by using the rough surface characteristic, and the alignment degree of the formed silicon through hole is improved.
Description
Technical field
The application relates to technical field of manufacturing semiconductors, in particular to a kind of for the align structures of silicon through hole making and the manufacture method of silicon through hole.
Background technology
In recent years, along with the development of 3-D stacks technology and MEMS package technology, silicon through hole (TSV, Through-Silicon-Via) interconnection technique receives great attention.TSV, by making vertical conducting between chip and chip, realizes three-dimensional transfer of data, thus shortens transmission range, save the surface area of chip and reduce power consumption.Utilize TSV technology, the company such as Intel, IBM has obtained important breakthrough in laminated chips technical field and has achieved commodity production, and at present, increasing company has put in the research and development of TSV technology.
Based on different application, the realization of TSV technology mainly can be divided into two kinds: first through-hole approaches and rear through-hole approaches.First first through-hole approaches forms in front side of silicon wafer etching the blind hole do not run through, and in hole, plated metal Seed Layer fills up blind hole again, finally from thinning back side silicon chip until expose metal electrode.Then through-hole approaches is first carried out thinning etching again to silicon chip and is formed through hole, fills up through hole again, finally remove Seed Layer again after the thicker metal seed layer of backside deposition.
Rear through-hole approaches conventional at present comprises Making programme as shown in Figure 1, first, the upper interlayer dielectric layer 102 ' of the chip substrate 100 ' of road technique before completing, form the device with cross-section structure shown in Fig. 2, wherein front road technique has completed the making of grid structure 101 '; Selectivity photoetching is carried out to the interlayer dielectric layer 102 ' shown in Fig. 2, forms groove 200 ' and conductive trench 300 ', form the device with cross-section structure shown in Fig. 3; Groove 200 ' shown in Fig. 3 and the middle deposits tungsten of conductive trench 300 ', formed and have tungsten structure 105 ' shown in Fig. 4 and contact hole 106 '; The upper deposited silicon nitride of tungsten structure 105 ' of the groove 200 ' shown in Fig. 4, form the silicon nitride layer 107 ' shown in Fig. 5, be provided with silicon nitride layer 107 ' in tungsten structure 105 ' wherein not only in groove 200 ', interlayer dielectric layer 102 ' is also provided with silicon nitride layer 107 '; Selective etch is carried out to the silicon nitride layer 107 ' in Fig. 5, interlayer dielectric layer 102 ' and substrate 100 ', forms the first silicon hole 400 ' shown in Fig. 6; With silicon nitride layer 107 ' upper deposition TEOS(tetraethoxysilane in the first silicon hole 400 ' in Fig. 6) and CMP is carried out to the TEOS deposit on interlayer dielectric layer 102, silicon nitride layer 107 ', obtain the TEOS layer 108 ' shown in Fig. 7; The upper deposited copper of TEOS layer 108 ' in the first silicon hole 400 ' shown in Fig. 7 also carries out CMP formation copper conductive layer 109 ' to copper, obtain having the device of cross-section structure shown in Fig. 8, the conductive layer 109 ' wherein in the first silicon hole 400 ' and TEOS layer 108 ' form the first silicon through hole.After formation first silicon through hole, continue plated metal on the device architecture shown in Fig. 8, form the metal interconnecting layer 110 ' shown in Fig. 9.
After said process completes, utilize the tungsten structure 105 ' being formed at align structures in Fig. 8, silicon nitride layer 107 ', TEOS layer 108 ' is aimed at the opening of aiming at of mask plate, make the silicon vias masks opening on mask plate and the first silicon through-hole alignment formed, then etching formation second silicon hole is carried out along with interconnection structure makes, the second silicon through hole is made in the second silicon hole, repeat said process and form the 3rd silicon through hole, N silicon through hole, wherein the first silicon through hole, second silicon through hole, 3rd silicon through hole, complete silicon through hole is connected to form with N silicon through hole, but, align structures its surfacing after metal interconnecting layer is set in prior art, optical detection structure is utilized to be difficult to fast, accurately position, therefore, affect the order of accuarcy of follow-up formed silicon through hole.
Summary of the invention
The application aims to provide a kind of for the align structures of silicon through hole making and the manufacture method of silicon through hole, the problem that the align structures made to solve silicon through hole of the prior art is difficult to fast, accurately aims at.
To achieve these goals, according to an aspect of the application, provide a kind of align structures made for silicon through hole, align structures comprises: substrate; Interlayer dielectric layer, is arranged on a surface of the substrate; First dielectric layer, is arranged on interlayer dielectric layer away from the surface of substrate; Groove, runs through interlayer dielectric layer and the first dielectric layer is arranged; Metal level, the inwall along groove is arranged; Nitration case, arrange on the metal layer, groove has depression, and depression is arranged on nitration case.
Further, above-mentioned align structures also comprises polysilicon layer, polysilicon layer be arranged in depression and the upper surface of polysilicon layer lower than the upper surface of nitration case.
Further, the characteristic size of above-mentioned groove is W
1, the degree of depth is L
1, the characteristic size of polysilicon layer is W
2, the upper surface of polysilicon layer is L apart from the distance of described substrate top surface
2, wherein, W
2for W
130 ~ 80%, preferably 40 ~ 70%; L
2for L
11 ~ 70%, preferably 1 ~ 60%, further preferably 5 ~ 50%.
Further, above-mentioned metal level is metal tungsten layer.
Further, above-mentioned nitration case is silicon nitride layer.
According to the another aspect of the application, provide a kind of manufacture method of silicon through hole, comprising: step S1, provide chip, chip has substrate and is positioned at the semiconductor front road process structure on described substrate; Step S2, chip makes align structures and the first silicon through hole; Step S3, utilize align structures that the first silicon through hole is aimed at silicon via mask opening, to carry out the making of silicon through hole, this align structures is above-mentioned align structures.
Further, above-mentioned semiconductor front road process structure comprises grid structure, and above-mentioned steps S2 comprises: on the surface with grid structure of substrate, set gradually interlayer dielectric layer and the first dielectric layer; Etch the first dielectric layer and interlayer dielectric layer successively, the groove forming align structures and the conductive trench be positioned at above grid structure; In groove and conductive trench, correspondence arranges metal level and contact hole; First dielectric layer, metal level and contact hole arrange nitration case; Nitration case in groove arranges polysilicon layer and etches formation first silicon hole; Dielectric barrier layer and conductive layer are set in the first silicon hole, form the first silicon through hole; Remove the nitration case of more than the first dielectric layer; And remove the depression that part or all of polysilicon layer forms align structures.
Further, the thickness of said first dielectric layer is 10 ~ 200nm.
Further, the material of above-mentioned formation first dielectric layer is silicon nitride, the silicon nitride of carbon containing or the tetraethoxysilane of ozone oxidation.
Further, the setting up procedure of said first dielectric layer adopts physical vaporous deposition, chemical vapour deposition technique or plasma deposition to implement.
Further, the forming process of above-mentioned metal level and contact hole comprises: plated metal in groove, in conductive trench and on the first dielectric layer; Chemical-mechanical planarization is carried out to the metal on the first dielectric layer, obtains the metal level be formed in groove and the contact hole be formed in conductive trench.
Further, above-mentioned nitration case in groove arranges polysilicon layer and the process etching shape the first one-tenth silicon hole comprises: deposit spathic silicon on nitration case; Remove polysilicon than grooves, obtain polysilicon layer; Etch nitride layer, the first dielectric layer, interlayer dielectric layer and substrate, form the first silicon hole successively; Or deposit spathic silicon on nitration case; Etch polysilicon, nitration case, the first dielectric layer, interlayer dielectric layer and substrate, form the first silicon hole successively; Remove polysilicon than grooves, obtain polysilicon layer.
Further, the process of above-mentioned removal polysilicon adopts chemical mechanical planarization method to implement.
Further, the above-mentioned process arranging dielectric barrier layer and conductive layer comprises: deposit dielectric isolated material on the inwall of the first silicon hole, on exposed nitration case and on polysilicon layer; Deposits conductive material in dielectric spacer material; Remove electric conducting material and the dielectric spacer material of more than nitration case, form conductive layer and dielectric barrier layer.
Further, the above-mentioned process arranging dielectric barrier layer and conductive layer comprises: deposit dielectric isolated material on the inwall of the first silicon hole, on exposed nitration case and on polysilicon layer; Dielectric spacer material in the first silicon hole covers crystal seed layer; Deposits conductive material on crystal seed layer and dielectric spacer material; Remove electric conducting material and the dielectric spacer material of more than nitration case, form conductive layer and dielectric barrier layer.
Further, above-mentioned dielectric spacer material is silica, silicon oxide carbide or silicon oxynitride.
Further, the thickness of above-mentioned dielectric barrier layer is 50 ~ 1000nm.
Further, the process of above-mentioned deposits conductive material adopts physical vaporous deposition, chemical vapour deposition technique or plasma deposition to implement.
Further, the process of the electric conducting material more than above-mentioned removal nitration case and dielectric spacer material adopts chemical mechanical planarization method to implement.
Further, the process of the nitration case more than above-mentioned removal first dielectric layer adopts selective wet chemical etching method to implement.
Further, the process of the part or all of polysilicon layer of above-mentioned removal adopts selective wet chemical etching to implement, and the etching agent of wet etching comprises Tetramethylammonium hydroxide.
The technical scheme of application the application, owing to being provided with depression in groove, therefore after formation first metal interconnecting layer due to the existence of this depression, the first metal interconnecting layer is made to need to fill this depression and then form little depression on the surface of the first metal interconnecting layer when making, and then utilizing it on time, utilize the feature of its surface irregularity can find fast and aim at this align structures, and improve the degree of registration of formed silicon through hole.
Accompanying drawing explanation
The Figure of description forming a application's part is used to provide further understanding of the present application, and the schematic description and description of the application, for explaining the application, does not form the improper restriction to the application.In the accompanying drawings:
Fig. 1 shows the Making programme figure of silicon through hole in prior art;
Cross-sectional view in the chip substrate that Fig. 2 shows road technique before completing after interlayer dielectric layer;
Fig. 3 shows and carries out selectivity photoetching to the interlayer dielectric layer shown in Fig. 2, forms the cross-sectional view after groove and conductive trench;
Fig. 4 show in the groove shown in Fig. 3 and conductive trench deposits tungsten form tungsten structure and contact hole after cross-sectional view;
Fig. 5 shows the cross-sectional view on the tungsten structure of the groove shown in Fig. 4 after deposited silicon nitride formation silicon nitride layer;
Fig. 6 shows and carries out selective etch to the silicon nitride layer in Fig. 5, interlayer dielectric layer and substrate and form the cross-sectional view after the first silicon hole;
Fig. 7 shows in the first silicon hole in Fig. 6 and silicon nitride layer deposits TEOS and carries out CMP to the TEOS deposit on interlayer dielectric layer and silicon nitride layer and obtains the cross-sectional view after TEOS layer;
Fig. 8 shows deposited copper on the TEOS layer in the first silicon hole shown in Fig. 7 and carries out CMP to copper and forms the cross-sectional view after copper conductive layer;
Fig. 9 shows the cross-sectional view on the device architecture shown in Fig. 8 after plated metal formation metal interconnecting layer;
Figure 10 shows the cross-sectional view of the align structures that a kind of preferred implementation of the application provides;
Figure 11 shows the schematic flow sheet of the silicon via-hole fabrication process that a kind of preferred implementation of the application provides;
Figure 12 to Figure 23 shows the device profile structural representation after performing each step shown in Figure 11, wherein,
Figure 12 shows the cross-sectional view after be successively set on interlayer dielectric layer and the first dielectric layer on the surface with grid structure of substrate;
Figure 13 shows the cross-sectional view after the groove etching the first dielectric layer shown in Figure 12 and interlayer dielectric layer formation align structures successively and the conductive trench be positioned at above grid structure;
Figure 14 to show in the groove shown in Figure 13 and conductive trench and correspondingly forms the cross-sectional view after metal level and contact hole;
Figure 15 shows the cross-sectional view on the first dielectric layer, metal level and the contact hole shown in Figure 14 after depositing nitride formation nitration case;
Figure 16 shows the cross-sectional view on the nitration case shown in Figure 15 after deposit spathic silicon;
Figure 17 shows the cross-sectional view after the polysilicon removed outside groove shown in Figure 16;
Figure 18 shows and etches the nitration case shown in Figure 17, the first dielectric layer, interlayer dielectric layer and substrate successively, forms the cross-sectional view after the first silicon hole;
Figure 19 shows the cross-sectional view on nitration case on the inwall of the first silicon hole shown in Figure 18, exposed and on polysilicon layer after deposit dielectric isolated material;
Figure 20 shows the cross-sectional view in the dielectric spacer material shown in Figure 19 after deposits conductive material;
Figure 21 shows and removes more than the nitration case shown in Figure 20 electric conducting material and dielectric spacer material, forms the cross-sectional view after the conductive layer of the first silicon through hole and dielectric barrier layer;
Figure 22 shows the cross-sectional view after the nitration case removing more than the first dielectric layer shown in Figure 21;
Figure 23 shows the cross-sectional view after removing the whole polysilicon layers formation align structures shown in Figure 22; And
Figure 24 shows the cross-sectional view form the first metal interconnecting layer on the metal level and nitration case of the first dielectric layer shown in Figure 23, dielectric barrier layer, conductive layer, contact hole, groove after.
Embodiment
It is noted that following detailed description is all exemplary, be intended to provide further instruction to the application.Unless otherwise, all technology used herein and scientific terminology have the identical meanings usually understood with the application person of an ordinary skill in the technical field.
It should be noted that used term is only to describe embodiment here, and be not intended to the illustrative embodiments of restricted root according to the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to comprise plural form, in addition, it is to be further understood that, when use belongs to " comprising " and/or " comprising " in this manual, it indicates existing characteristics, step, operation, device, assembly and/or their combination.
For convenience of description, here can usage space relative terms, as " ... on ", " in ... top ", " at ... upper surface ", " above " etc., be used for the spatial relation described as a device shown in the figure or feature and other devices or feature.Should be understood that, space relative terms is intended to comprise the different azimuth in use or operation except the described in the drawings orientation of device.Such as, " in other devices or structure below " or " under other devices or structure " will be positioned as after if the device in accompanying drawing is squeezed, being then described as the device of " above other devices or structure " or " on other devices or structure ".Thus, exemplary term " in ... top " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (90-degree rotation or be in other orientation), and relatively describe space used here and make respective explanations.
Introduce as background technology, existing silicon through hole is in manufacturing process, the align structures surfacing adopted, optical detection structure is utilized to be difficult to position quickly and accurately, affect the order of accuarcy of follow-up formed silicon through hole, in order to solve as above problem, the manufacture method of the align structures that the silicon through hole that present applicant proposes a kind of semiconductor device makes and silicon through hole.
The application's one preferred embodiment in, provide a kind of align structures made for silicon through hole, as shown in Figure 10, this align structures comprises substrate 100, interlayer dielectric layer 102, first dielectric layer 103, groove 200, metal level 104 and nitration case 106, interlayer dielectric layer 102 is arranged on the surface of substrate 100, first dielectric layer 103 is arranged on the surface of interlayer dielectric layer 102 away from substrate 100, groove 200 runs through interlayer dielectric layer 102 and the first dielectric layer 103 is arranged, and metal level 104 is arranged along the inwall of groove 200; Nitration case 106 is arranged on metal level 104, and wherein, above-mentioned groove 200 has depression 201, and this depression 201 is arranged on described nitration case 106.
There is the align structures of cross-section structure as shown in Figure 10, owing to being provided with depression 201 in groove 200, therefore after formation first metal interconnecting layer 110 due to the existence of this depression 201, the first metal interconnecting layer 110 is made to need to fill this depression 201 and then form little depression (as shown in figure 24) on the surface of the first metal interconnecting layer 110 when making, and then utilizing it on time, utilize the feature of its surface irregularity can find fast and aim at this align structures, and improve the degree of registration of formed silicon through hole.
In the application's another preferred embodiment, above-mentioned align structures also comprises polysilicon layer 107, polysilicon layer 107 be positioned at above-mentioned depression 201 and the upper surface of polysilicon layer 107 lower than the upper surface of nitration case 106.There is the align structures of said structure, because the upper surface of polysilicon layer 107 is lower than the upper surface of nitration case 106, therefore in groove 200, still there is the dolly dimple that the degree of depth is less than above-mentioned depression 201, therefore, form the first metal interconnecting layer 110 surface remain irregular, and then irregular surface can be utilized can to find this align structures quickly and accurately.
As described above, the application mainly utilizes in above-mentioned align structures because the depression formed lower than the upper surface of interlayer dielectric layer 102 without the upper surface of polysilicon layer 107 or polysilicon layer 107 is aimed at, in order to make depression more obvious, more be conducive to quick and precisely aiming at, preferably when having polysilicon layer 107, the characteristic size of above-mentioned groove is W
1, the degree of depth is L
1, the characteristic size of above-mentioned dielectric barrier layer is W
2, the distance of the upper surface distance substrate top surface of above-mentioned dielectric barrier layer is L
2, wherein, W
2for W
130 ~ 80%, preferably 40 ~ 70%; L
2for L
11 ~ 70%, preferably 1 ~ 60%, further preferably 5 ~ 50%.
Above-mentioned characteristic size is similar to this area usual definition, refers to the size of the corresponding component extended along channel width dimension, the width size of groove 200 as shown in Figure 10, the width size of polysilicon layer 107.
The metal level 105 of the application can be metal tungsten layer; The nitration case 106 of the application is silicon nitride layer, or the silicon nitride layer of carbon containing.
In the another kind of typical execution mode of the application, provide a kind of manufacture method of silicon through hole, Figure 11 shows the schematic flow sheet of this manufacture method.This manufacture method comprises: step S1, provides chip, and chip has substrate and is positioned at the semiconductor front road process structure on substrate; Step S2, chip makes align structures and the first silicon through hole; Step S3, utilize align structures that the first silicon through hole is aimed at silicon via mask opening, to carry out the making of silicon through hole, this align structures is above-mentioned align structures.
When utilizing above-mentioned manufacture method to make silicon through hole, the first silicon through hole is formed while formation align structures, and then make the silicon through hole that will be formed relative with the position of align structures fixing, this align structures is utilized to make the second silicon through hole further, 3rd silicon through hole, during N silicon through hole, above-mentioned align structures surface is utilized to have irregular feature, align structures position can be located rapidly and accurately, and then the opening of align structures can carry out rapid alignment with align structures on mask plate, the first silicon through hole silicon vias masks on mask plate being opened on formed accurately is aimed at, can accurately etch above established first silicon through hole when carrying out next step etching, make the second silicon through hole, 3rd silicon through hole, N silicon through hole is accurately aimed in three-dimensional structure, extend, form complete silicon through hole.As can be seen here, the silicon via-hole fabrication process alignment speed of the application is very fast and accurately, and therefore make efficiency is improved and the levels of precision of the silicon through hole obtained is higher.Size those skilled in the art of above-mentioned N can require to set according to the semiconductor design of reality, are generally not more than 10.
The application another preferred embodiment in, the front road of the semiconductor in above-mentioned manufacture method process structure comprises grid structure, and above-mentioned steps S2 comprises: on the surface with grid structure of substrate, set gradually interlayer dielectric layer and the first dielectric layer 103; Etch the first dielectric layer 103 and interlayer dielectric layer 102 successively, the groove 200 forming align structures and the conductive trench 300 be positioned at above grid structure 101; In groove 200 and conductive trench 300, correspondence arranges metal level 104 and contact hole 105; First dielectric layer 103, metal level 104 and contact hole 105 arrange nitration case 106; Nitration case 106 in groove 200 arranges polysilicon layer 107 and etches formation first silicon hole 400; Dielectric barrier layer 108 and conductive layer 109 are set in the first silicon hole 400, form the first silicon through hole; Remove the nitration case 106 of the first dielectric layer more than 103; And remove the depression 201 that part or all of polysilicon layer 107 forms align structures.
Above-mentioned manufacture method, polysilicon layer 107 is utilized to replace the dielectric barrier layer be filled in prior art in groove 200 above nitration case 106, and by the adjustment to manufacture craft, remove above-mentioned part or all of polysilicon layer 107, make to exist in groove 200 dolly dimple that depression 201 or the degree of depth are less than depression 201, so when plated metal forms the first metal interconnecting layer 110, need all the other positions unnecessary, metal filled space above align structures, and then the upper surface of the first metal interconnecting layer formed can out-of-flatness.When utilizing above-mentioned manufacture method to make silicon through hole, the surface of align structures has irregular feature, therefore can find fast and aim at this align structures, and improves the degree of registration of formed silicon through hole.It is all adopt ordinary skill in the art means to implement that above-mentioned manufacture method utilizes, and is combined to form above-mentioned manufacture method to each routine techniques means, and therefore this manufacture method is simple, controlled, is conducive to extensive enforcement.
Now, the illustrative embodiments according to the application is described with reference to the accompanying drawings in more detail.But these illustrative embodiments can be implemented by multiple different form, and should not be interpreted as being only limited to execution mode set forth herein.Should be understood that, there is provided these execution modes be in order to make the application open thorough and complete, and the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expand the thickness in layer and region, and use the device that identical Reference numeral represents identical, thus will omit description of them.
First, provide chip, this chip has been the chip after semiconductor front road technique, and have substrate 100 and semiconductor front road process structure, preferably this semiconductor front road process structure comprises grid structure 101.
Then, the surface with grid structure 101 of substrate 100 sets gradually interlayer dielectric layer 102 and the first dielectric layer 103, form the device with cross-section structure shown in Figure 12.Forming the material of interlayer dielectric layer is that low K electrolyte is formed, such as phosphosilicate glass (PSG), boron phosphorus silicate glass (BPSG), fluorinated silicate glass (FSG), SiOxCy, spin-coating glass, spin coating condensate, carbofrax material, they compound, they synthetic, their combination etc.The physical vaporous deposition that said first dielectric layer 103 can adopt this area conventional or chemical vapour deposition technique are implemented; wherein; the material forming the first dielectric layer 103 includes but not limited to the silicon nitride of silicon nitride, carbon containing and the tetraethoxysilane of ozone oxidation; the silicon nitride of preferred carbon containing; playing on the protective effect basis to interlayer dielectric layer 102, the thickness of the first preferably above-mentioned dielectric layer 103 is 10 ~ 200nm.
Then the first dielectric layer 103 and interlayer dielectric layer 102 shown in Figure 12 are etched, form the groove 200 shown in Figure 13 and conductive trench 300.The lithographic method that above-mentioned etching process can adopt this area conventional, to form groove 200 identical with conductive trench with groove of the prior art with conductive trench 300, the groove 200 formed is align structures positions of follow-up formation, contact hole 105 position of the follow-up formation of conductive trench formula formed.The application is understood better in order to make those skilled in the art; following schematically illustrating is carried out to lithographic method: photoresist is set on the first dielectric layer 103; then graphical treatment is carried out to this photoresist; to form opening in the position for forming groove 200 and conductive trench 300 correspondence, under the protection of the photoresist after graphically, wet etching or dry etching are carried out to the first dielectric layer 103 and interlayer dielectric layer 102.
After formation groove 200 and conductive trench 300, to plated metal in the groove 200 shown in Figure 13, in conductive trench 300 and on the first dielectric layer 103; Then chemical-mechanical planarization is carried out to the metal on the first dielectric layer 103, obtain the contact hole 105 being formed at the metal level 104 in groove 200 and being formed in conductive trench 300 shown in Figure 14.Above-mentioned deposition process can adopt the methods such as chemical vapour deposition technique, physical vaporous deposition or plasma deposition to implement, and the metal deposited is preferably tungsten.
After formation metal level 104, on the first dielectric layer 103, metal level 104 and the contact hole 105 shown in Figure 14, depositing nitride forms the nitration case 106 shown in Figure 15.Above-mentioned nitride is silicon nitride, the carborundum of carbon containing, oxygen containing silicon nitride, is preferably silicon nitride; Same deposition process can adopt chemical vapour deposition technique, physical vaporous deposition or plasma deposition.
Nitration case 106 after nitration case 106 is formed in groove 200 shown in Figure 15 arranges polysilicon layer 107 and etches formation first silicon hole 400.This first silicon hole 400 is identical with first silicon hole of this area is all the first silicon through hole position of follow-up formation.According to the practice of this area, the first silicon hole 400 characteristic size formed is less than the characteristic size of aforementioned grooves 200, and the degree of depth of the first silicon hole 400 is obviously greater than the degree of depth of groove 200.
Said process those skilled in the art can take prior art as reference, suitable technique is adopted to implement, the application preferably adopts following two kinds of modes to implement, wherein execution mode comprises: a deposit spathic silicon on the nitration case 106 shown in Figure 15, forms the device with cross-section structure shown in Figure 16; Remove the polysilicon outside groove 200, obtain the polysilicon layer 107 shown in Figure 17; Etch nitration case 106, first dielectric layer 103, interlayer dielectric layer 102 and the substrate 100 shown in Figure 17 successively, form the first silicon hole 400 shown in Figure 18, said process is that the polysilicon first removed outside groove 200 forms polysilicon layer 107, rear etching formation first silicon hole 400.Another kind of execution mode comprises: deposit spathic silicon on the nitration case 106 shown in Figure 15; Etch polysilicon, nitration case 106, first dielectric layer 103, interlayer dielectric layer 102 and substrate 100, form the first silicon hole 400 successively; Remove the polysilicon outside groove 200, obtain polysilicon layer 107, the second execution mode forms polysilicon layer 107 after first forming the first silicon hole 400.No matter adopt which kind of mode above-mentioned all can obtain the structure shown in Figure 19, above-mentioned execution mode preferably adopts chemical mechanical polishing method to implement when removing polysilicon.
After shape first silicon hole 400, the dielectric barrier layer 108 shown in Figure 21 and conductive layer 109 are set in the first silicon hole 400 shown in Figure 18.This dielectric barrier layer 108 being arranged in the first silicon hole 400, for the electric conducting material of the first silicon through hole and substrate 100 being isolated, is avoided the first silicon through hole and substrate 100 break-through, is made semiconductor device failure.The material that the application forms above-mentioned dielectric barrier layer 108 includes but not limited to silica, silicon oxide carbide or silicon oxynitride, preferred silicon oxide carbide or silicon oxynitride.In order to obtain more preferably dielectric isolation effect, the thickness of preferred above-mentioned dielectric barrier layer 108 is 50 ~ 1000nm.Above-mentioned setting up procedure can adopt in this area the common method forming the first silicon through hole to implement.Preferably in the following ways, wherein a kind of mode comprises the application:
Deposit dielectric isolated material on the inwall of the first silicon hole 400 shown in Figure 18, on exposed nitration case 106 and on polysilicon layer 107, obtains having the device of cross-section structure shown in Figure 19; Deposits conductive material in the dielectric spacer material shown in Figure 19, obtains having the device of cross-section structure shown in Figure 20; Remove electric conducting material and the dielectric spacer material of the nitration case more than 106 shown in Figure 20, form the conductive layer 109 shown in Figure 21 and dielectric barrier layer 108.
Another kind of mode comprises: deposit dielectric isolated material on the inwall of the first silicon hole 400 shown in Figure 18, on exposed nitration case 106 and on polysilicon layer 107; Dielectric spacer material in the first silicon hole 400 covers crystal seed layer (not shown); Deposits conductive material on crystal seed layer and dielectric spacer material; Remove electric conducting material and the dielectric spacer material of nitration case more than 106, form the conductive layer 109 shown in Figure 21 and dielectric barrier layer 108.Wherein, crystal seed layer is formed between plated metal, be metal carrying for sedimentary origin, to improve deposition efficiency and good interface characteristics.
The deposition process of above-mentioned each mode dielectric isolated material and electric conducting material includes but not limited to adopt physical vaporous deposition, chemical vapour deposition technique and plasma deposition, preferred using plasma sedimentation.Remove the preferred chemical-mechanical planarization method of method of electric conducting material and dielectric spacer material.
After formation conductive layer 109 and dielectric barrier layer 108, remove the nitration case 106 of the first dielectric layer more than 103 shown in Figure 21, obtain having the device of cross-section structure shown in Figure 22.The process of above-mentioned removal nitration case 106 preferably adopts selective wet chemical etching method to implement.Nitride and the high etachable material of oxide etching selection and comparison is selected to etch, such as phosphoric acid.
After removing nitration case 106, remove the part or all of polysilicon layer 107 shown in Figure 22, after removing whole polysilicon layer 107, form the depression 201 of align structures, obtain having the device of cross-section structure shown in Figure 23.The depression 201 that align structures comprises metal level 104 in groove 200, nitration case 106 and is positioned at above nitration case 106, if polysilicon layer 107 is not completely removed align structures also comprise partial polysilicon layer 107.The process of the part or all of polysilicon layer 107 of above-mentioned removal adopts selective wet chemical etching to implement, the etching agent of wet etching is preferably tetramethyl ammonium hydroxide solution, the selectivity of this solution to polysilicon is higher, and an etch polysilicon when etching, does not etch other materials.In the process of above-mentioned removal polysilicon layer, the first dielectric layer 103 pairs of interlayer dielectric layers 102 and following structure thereof play a protective role, and then avoid causing damage to the semiconductor device formed in the process removing polysilicon layer 107.
In order to further illustrate the technique effect of the application, after the above-mentioned align structures of formation, the metal level 104 and nitration case 106 of the first dielectric layer 103 shown in Figure 23, dielectric barrier layer 108, conductive layer 109, contact hole 105, groove 200 form the first metal interconnecting layer 110 shown in Figure 24.The employing chemical vapour deposition (CVD) of above-mentioned first metal interconnecting layer 110, physical vapour deposition (PVD) or plasma deposited metal are formed.Because the upper surface of align structures is lower than the upper surface of interlayer dielectric layer 102, namely depression 201 is formed in groove 200 position, therefore, when plated metal, metal needs will fill this depression 201, so after the deposition completing metal, because the existence of depression makes the first metal interconnecting layer 110 be positioned at above align structures also there is little depression, so when utilizing this align structures to make silicon through hole further, align structures position can be located rapidly and accurately, and then alignment mask plate can carry out rapid alignment with align structures, can accurately etch above established silicon through hole when carrying out next step etching, silicon through hole is made accurately to aim at extension in three-dimensional structure.
As can be seen from the above description, the application's the above embodiments achieve following technique effect:
1), depression is provided with in groove, therefore after formation first metal interconnecting layer due to the existence of this depression, the first metal interconnecting layer is made to need to fill this depression and then form little depression on the surface of the first metal interconnecting layer when making, and then utilizing it on time, utilize the feature of its surface irregularity can find fast and aim at this align structures, and improve the degree of registration of formed silicon through hole;
2), the silicon via-hole fabrication process alignment speed of the application is very fast and accurately, and therefore make efficiency is improved and the levels of precision of the silicon through hole obtained is higher.
The foregoing is only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (18)
1., for the align structures that silicon through hole makes, described align structures comprises:
Substrate;
Interlayer dielectric layer, is arranged on the surface of described substrate;
First dielectric layer, is arranged on the surface of described interlayer dielectric layer away from described substrate;
Groove, runs through described interlayer dielectric layer and described first dielectric layer is arranged;
Metal level, the inwall along described groove is arranged;
Nitration case, is arranged on described metal level, it is characterized in that,
Described groove has depression, and described depression is arranged on described nitration case.
2. align structures according to claim 1, it is characterized in that, described align structures also comprises polysilicon layer, described polysilicon layer be arranged in described depression and the upper surface of described polysilicon layer lower than the upper surface of described nitration case.
3. align structures according to claim 2, it is characterized in that, the characteristic size of described groove is W
1, the degree of depth is L
1, the characteristic size of described polysilicon layer is W
2, the upper surface of described polysilicon layer is L apart from the distance of described substrate top surface
2, wherein, W
2for W
130 ~ 80%, preferably 40 ~ 70%; L
2for L
11 ~ 70%, preferably 1 ~ 60%, further preferably 5 ~ 50%.
4. align structures according to any one of claims 1 to 3, is characterized in that, described metal level is metal tungsten layer.
5. align structures according to any one of claims 1 to 3, is characterized in that, described nitration case is silicon nitride layer.
6. a manufacture method for silicon through hole, comprising:
Step S1, provides chip, and described chip has substrate and is positioned at the semiconductor front road process structure on described substrate;
Step S2, makes align structures and the first silicon through hole on the chip;
Step S3, utilizes described align structures that described first silicon through hole is aimed at silicon via mask opening, to carry out the making of described silicon through hole, it is characterized in that, the align structures of described align structures according to any one of claim 1 to 5.
7. manufacture method according to claim 6, is characterized in that, described semiconductor front road process structure comprises grid structure, and described step S2 comprises:
The surface with described grid structure of described substrate sets gradually interlayer dielectric layer and the first dielectric layer;
Etch described first dielectric layer and described interlayer dielectric layer successively, the groove forming described align structures and the conductive trench be positioned at above described grid structure;
In described groove and described conductive trench, correspondence arranges metal level and contact hole;
Described first dielectric layer, described metal level and contact hole arrange nitration case;
Described nitration case in described groove arranges polysilicon layer and etches formation first silicon hole;
Dielectric barrier layer and conductive layer are set in described first silicon hole, form described first silicon through hole;
Remove the described nitration case of more than described first dielectric layer; And
Remove the depression that part or all of described polysilicon layer forms described align structures.
8. manufacture method according to claim 7, it is characterized in that, the thickness of described first dielectric layer is 10 ~ 200nm, the material being preferably formed described first dielectric layer is silicon nitride, the silicon nitride of carbon containing or the tetraethoxysilane of ozone oxidation, and preferably the setting up procedure of described first dielectric layer adopts physical vaporous deposition, chemical vapour deposition technique or plasma deposition to implement.
9. manufacture method according to claim 7, is characterized in that, the forming process of described metal level and described contact hole comprises:
Plated metal in described groove, in described conductive trench and on described first dielectric layer;
Chemical-mechanical planarization is carried out to the metal on described first dielectric layer, obtains the described metal level be formed in described groove and the described contact hole be formed in described conductive trench.
10. manufacture method according to claim 7, is characterized in that, the described nitration case in described groove arranges polysilicon layer and the process etching formation first silicon hole comprises:
Deposit spathic silicon on described nitration case;
Remove the described polysilicon outside described groove, obtain described polysilicon layer;
Etch described nitration case, described first dielectric layer, described interlayer dielectric layer and described substrate successively, form described first silicon hole; Or
Deposit spathic silicon on described nitration case;
Etch described polysilicon, described nitration case, described first dielectric layer, described interlayer dielectric layer and described substrate successively, form described first silicon hole;
Remove the described polysilicon outside described groove, obtain described polysilicon layer.
11. manufacture methods according to claim 10, is characterized in that, the process of described removal polysilicon adopts chemical mechanical planarization method to implement.
12. manufacture methods according to claim 7, is characterized in that, the described process arranging dielectric barrier layer and conductive layer comprises:
Deposit dielectric isolated material on the inwall of described first silicon hole, on exposed described nitration case and on described polysilicon layer;
Deposits conductive material in described dielectric spacer material;
Remove the described electric conducting material of more than described nitration case and described dielectric spacer material, form described conductive layer and described dielectric barrier layer; Or
Deposit dielectric isolated material on the inwall of described first silicon hole, on exposed described nitration case and on described polysilicon layer;
Described dielectric spacer material in described first silicon hole covers crystal seed layer;
Deposits conductive material on described crystal seed layer and described dielectric spacer material;
Remove the described electric conducting material of more than described nitration case and described dielectric spacer material, form described conductive layer and described dielectric barrier layer.
13. manufacture methods according to claim 12, is characterized in that, described dielectric spacer material is silica, silicon oxide carbide or silicon oxynitride.
14. manufacture methods according to claim 7 or 12, it is characterized in that, the thickness of described dielectric barrier layer is 50 ~ 1000nm.
15. manufacture methods according to claim 12, is characterized in that, the process of described deposits conductive material adopts physical vaporous deposition, chemical vapour deposition technique or plasma deposition to implement.
16. manufacture methods according to claim 12, is characterized in that, the process of electric conducting material more than described removal nitration case and dielectric spacer material adopts chemical mechanical planarization method to implement.
17. manufacture methods according to claim 7, is characterized in that, the process of nitration case more than described removal first dielectric layer adopts selective wet chemical etching method to implement.
18. manufacture methods according to claim 7, is characterized in that, the process of the part or all of polysilicon layer of described removal adopts selective wet chemical etching to implement, and the etching agent of described wet etching comprises Tetramethylammonium hydroxide.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109524424A (en) * | 2017-09-18 | 2019-03-26 | 豪威科技股份有限公司 | Backside illuminated image sensor with autoregistration metal pad structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6232200B1 (en) * | 1998-10-22 | 2001-05-15 | United Microelectronics Corp. | Method of reconstructing alignment mark during STI process |
| US20030017707A1 (en) * | 2001-07-19 | 2003-01-23 | Tomio Yamashita | Semiconductor device and method for manufacturing thereof |
| WO2004023551A1 (en) * | 2002-09-04 | 2004-03-18 | Infineon Technologies Ag | Mram mtj stack to conductive line alignment method |
| CN103035511A (en) * | 2011-10-09 | 2013-04-10 | 上海华虹Nec电子有限公司 | Method for producing zero layer photoetching marking of high-voltage device without barrier layers |
| CN104733371A (en) * | 2013-12-18 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | Through silicon via forming method and alignment structure of semiconductor device |
-
2014
- 2014-03-31 CN CN201410127763.2A patent/CN104952849B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6232200B1 (en) * | 1998-10-22 | 2001-05-15 | United Microelectronics Corp. | Method of reconstructing alignment mark during STI process |
| US20030017707A1 (en) * | 2001-07-19 | 2003-01-23 | Tomio Yamashita | Semiconductor device and method for manufacturing thereof |
| WO2004023551A1 (en) * | 2002-09-04 | 2004-03-18 | Infineon Technologies Ag | Mram mtj stack to conductive line alignment method |
| CN103035511A (en) * | 2011-10-09 | 2013-04-10 | 上海华虹Nec电子有限公司 | Method for producing zero layer photoetching marking of high-voltage device without barrier layers |
| CN104733371A (en) * | 2013-12-18 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | Through silicon via forming method and alignment structure of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109524424A (en) * | 2017-09-18 | 2019-03-26 | 豪威科技股份有限公司 | Backside illuminated image sensor with autoregistration metal pad structure |
| CN109524424B (en) * | 2017-09-18 | 2019-09-17 | 豪威科技股份有限公司 | Backside illuminated image sensor with autoregistration metal pad structure |
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