CN104952849B - The production method of align structures and through silicon via for through silicon via production - Google Patents
The production method of align structures and through silicon via for through silicon via production Download PDFInfo
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- CN104952849B CN104952849B CN201410127763.2A CN201410127763A CN104952849B CN 104952849 B CN104952849 B CN 104952849B CN 201410127763 A CN201410127763 A CN 201410127763A CN 104952849 B CN104952849 B CN 104952849B
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Abstract
This application provides a kind of align structures for through silicon via production and the production methods of through silicon via.The align structures include: substrate；Interlayer dielectric layer, setting is on a surface of the substrate；Interlayer dielectric layer is arranged in far from the surface of substrate in first dielectric layer；Groove is arranged through interlayer dielectric layer and the first dielectric layer；Metal layer, the inner wall along groove are arranged；Nitration case, on the metal layer, groove has recess for setting, and recess is arranged on nitration case.Due to being provided with recess in groove, therefore due to the presence of the recess after forming the first metal interconnecting layer, so that the first metal interconnecting layer needs to fill the recess in production and then forms small recess on the surface of the first metal interconnecting layer, and then when using its alignment, it can be quickly found out using the characteristics of its surface irregularity and be directed at the align structures, and improve the degree of registration for being formed by through silicon via.
Description
Technical field
This application involves technical field of manufacturing semiconductors, in particular to a kind of alignment knot for through silicon via production
The production method of structure and through silicon via.
Background technique
In recent years, with the development of 3-D stacks technology and MEMS package technology, through silicon via (TSV, Through-
Silicon-Via) interconnection technique receives great attention.TSV is realized by making vertical conducting between chip and chip
Three-dimensional data transmission, so as to shorten transmission range, saves the surface area of chip and reduces power consumption.Using TSV technology,
The companies such as Intel, IBM obtain important breakthrough in laminated chips technical field and realize commodity production, currently, more next
More companies have put into the research and development of TSV technology.
Based on different applications, the realization of TSV technology can be divided mainly into two kinds: first through-hole approaches and rear through-hole approaches.First
Through-hole approaches first front side of silicon wafer etch to be formed not through blind hole, deposited metal seed layer fills up blind hole again in hole, most
Afterwards from thinning back side silicon wafer up to exposing metal electrode.Then through-hole approaches first be thinned to silicon wafer and etch to form through-hole again,
Through-hole is filled up again after the thicker metal seed layer of backside deposition, finally removes seed layer again.
Through-hole approaches include production process as shown in Figure 1 after currently used, firstly, in the chip of the preceding road technique of completion
Interlayer dielectric layer 102 ' on substrate 100 ' forms the device with cross-section structure shown in Fig. 2, wherein preceding road technique is complete
At the production of gate structure 101 '；Selective photoetching is carried out to interlayer dielectric layer 102 ' shown in Fig. 2, groove 200 ' is formed and leads
Electric groove 300 ' forms the device with cross-section structure shown in Fig. 3；In groove 200 ' and conductive trench 300 ' shown in Fig. 3
Deposits tungsten, being formed has tungsten structure 105 ' shown in Fig. 4 and contact hole 106 '；The tungsten structure 105 ' of groove 200 ' shown in Fig. 4
Upper deposited silicon nitride forms silicon nitride layer 107 ' shown in fig. 5, wherein being not only provided in the tungsten structure 105 ' in groove 200 '
Silicon nitride layer 107 ' is also equipped with silicon nitride layer 107 ' on interlayer dielectric layer 102 '；To silicon nitride layer 107 ', the interlayer in Fig. 5
Dielectric layer 102 ' and substrate 100 ' carry out selective etch, form the first silicon hole 400 ' shown in fig. 6；The first silicon into Fig. 6
Hole 400 ' neutralize silicon nitride layer 107 ' on deposit TEOS(ethyl orthosilicate) and on interlayer dielectric layer 102 TEOS deposit,
Silicon nitride layer 107 ' carries out CMP, obtains TEOS layer 108 ' shown in Fig. 7；TEOS layer in the first silicon hole 400 ' shown in Fig. 7
Copper is deposited on 108 ' and CMP is carried out to copper and forms copper conductive layer 109 ', obtains the device with cross-section structure shown in Fig. 8, wherein
Conductive layer 109 ' and TEOS layer 108 ' in first silicon hole 400 ' form the first through silicon via.After forming the first through silicon via, after
Continue deposited metal on device architecture shown in Fig. 8, forms metal interconnecting layer 110 ' shown in Fig. 9.
After the completion of the above process, using be formed in the tungsten structure 105 ' of align structures in Fig. 8, silicon nitride layer 107 ',
The alignment opening of TEOS layer 108 ' and mask plate is aligned so that the through silicon via mask open on mask plate with formed
The alignment of first through silicon via performs etching to form the second silicon hole, makes second in the second silicon hole then as interconnection structure production
Through silicon via, repeat the above process to be formed third through silicon via ..., N through silicon via, wherein the first through silicon via, the second through silicon via,
Three through silicon vias ... and N through silicon via is connected to form complete through silicon via, still, align structures are in setting gold in the prior art
Its surfacing after category interconnection layer, is difficult to quickly and accurately be positioned, therefore, influences subsequent institute using optical detection structure
The order of accuarcy of the through silicon via of formation.
Summary of the invention
The production method that the application is intended to provide a kind of align structures for through silicon via production and through silicon via, it is existing to solve
Have the align structures of the through silicon via production in technology be difficult to quickly, the problem of precisely aligning.
To achieve the goals above, according to the one aspect of the application, a kind of alignment for through silicon via production is provided
Structure, align structures include: substrate；Interlayer dielectric layer, setting is on a surface of the substrate；First dielectric layer, setting are situated between in interlayer
Matter layer is far from the surface of substrate；Groove is arranged through interlayer dielectric layer and the first dielectric layer；Metal layer, along the inner wall of groove
Setting；Nitration case, on the metal layer, groove has recess for setting, and recess is arranged on nitration case.
Further, above-mentioned align structures further include polysilicon layer, polysilicon layer be located in recess and polysilicon layer it is upper
Surface is lower than the upper surface of nitration case.
Further, the characteristic size of above-mentioned groove is W1, depth L1, the characteristic size of polysilicon layer is W2, polysilicon
Distance of the upper surface of layer apart from the upper surface of substrate is L2, wherein W2For W130~80%, preferably 40~70%；L2For L1
1~70%, preferably 1~60%, further preferred 5~50%.
Further, above-mentioned metal layer is metal tungsten layer.
Further, above-mentioned nitration case is silicon nitride layer.
According to the another aspect of the application, a kind of production method of through silicon via is provided, comprising: step S1 provides chip,
Chip has substrate and the preceding road process structure of semiconductor on the substrate；Step S2, makes align structures on chip
With the first through silicon via；Step S3 is directed at the first through silicon via with through silicon via mask open using align structures, to carry out through silicon via
Production, the align structures be above-mentioned align structures.
Further, the preceding road process structure of above-mentioned semiconductor includes gate structure, and above-mentioned steps S2 includes: the tool in substrate
Have and sets gradually interlayer dielectric layer and the first dielectric layer on the surface of gate structure；It is sequentially etched the first dielectric layer and inter-level dielectric
Layer, forms the groove of align structures and the conductive trench above gate structure；It is correspondingly arranged in groove and conductive trench
Metal layer and contact hole；Nitration case is set on the first dielectric layer, metal layer and contact hole；It is arranged on nitration case in groove
Polysilicon layer simultaneously etches to form the first silicon hole；Dielectric barrier layer and conductive layer are set in the first silicon hole, form the first through silicon via；
Remove the nitration case of the first dielectric layer or more；And the part or all of polysilicon layer of removal forms the recess of align structures.
Further, said first dielectric layer with a thickness of 10~200nm.
Further, the material of above-mentioned the first dielectric layer of formation be silicon nitride, carbon containing silicon nitride or ozone oxidation just
Silester.
Further, the setting up procedure of said first dielectric layer using physical vaporous deposition, chemical vapour deposition technique or
Plasma deposition is implemented.
Further, the forming process of above-mentioned metal layer and contact hole includes: to be situated between in groove, in conductive trench with first
Deposited metal in electric layer；Chemical-mechanical planarization is carried out to the metal on the first dielectric layer, obtains being formed in the metal in groove
Layer and the contact hole being formed in conductive trench.
Further, polysilicon layer is set on the above-mentioned nitration case in groove and etches shape first into the process packet of silicon hole
It includes: the deposit polycrystalline silicon on nitration case；Polysilicon than grooves is removed, polysilicon layer is obtained；It is sequentially etched nitration case, first
Dielectric layer, interlayer dielectric layer and substrate form the first silicon hole；Or the deposit polycrystalline silicon on nitration case；Be sequentially etched polysilicon,
Nitration case, the first dielectric layer, interlayer dielectric layer and substrate form the first silicon hole；Polysilicon than grooves is removed, polycrystalline is obtained
Silicon layer.
Further, the process of above-mentioned removal polysilicon is implemented using chemical mechanical planarization method.
Further, above-mentioned setting dielectric barrier layer and the process of conductive layer include: on the inner wall of the first silicon hole, it is exposed
Nitration case on and polysilicon layer on deposit dielectric isolated material；Conductive material is deposited in dielectric spacer material；Removal nitridation
Layer or more conductive material and dielectric spacer material, form conductive layer and dielectric barrier layer.
Further, above-mentioned setting dielectric barrier layer and the process of conductive layer include: on the inner wall of the first silicon hole, it is exposed
Nitration case on and polysilicon layer on deposit dielectric isolated material；Crystal seed is covered in the dielectric spacer material in the first silicon hole
Layer；Conductive material is deposited on seed layer and dielectric spacer material；Remove the conductive material and dielectric isolation material of nitration case or more
Material forms conductive layer and dielectric barrier layer.
Further, above-mentioned dielectric spacer material is silica, silicon oxide carbide or silicon oxynitride.
Further, above-mentioned dielectric barrier layer with a thickness of 50~1000nm.
Further, the process of above-mentioned deposition conductive material using physical vaporous deposition, chemical vapour deposition technique or waits
Plasma deposition method is implemented.
Further, the process of conductive material more than above-mentioned removal nitration case and dielectric spacer material uses chemical machinery
Flattening method is implemented.
Further, the process of nitration case more than above-mentioned the first dielectric layer of removal is implemented using selective wet chemical etching method.
Further, the process of the part or all of polysilicon layer of above-mentioned removal is implemented using selective wet chemical etching, and wet process is carved
The etching agent of erosion includes tetramethylammonium hydroxide.
Using the technical solution of the application, due to being provided with recess in groove, after forming the first metal interconnecting layer
Due to the presence of the recess, so that the first metal interconnecting layer needs to fill the recess and then in the first metal interconnecting layer in production
Surface form small recess, and then when using its alignment, can be quickly found out using the characteristics of its surface irregularity and right
The quasi- align structures, and improve the degree of registration for being formed by through silicon via.
Detailed description of the invention
The accompanying drawings constituting a part of this application is used to provide further understanding of the present application, and the application's shows
Meaning property embodiment and its explanation are not constituted an undue limitation on the present application for explaining the application.In the accompanying drawings:
Fig. 1 shows the production flow diagram of through silicon via in the prior art；
Fig. 2 shows the schematic diagram of the section structure in the chip substrate of the preceding road technique of completion after interlayer dielectric layer；
Fig. 3, which is shown, carries out selective photoetching, cuing open after formation groove and conductive trench to interlayer dielectric layer shown in Fig. 2
Face structural schematic diagram；
Fig. 4 shows deposits tungsten in groove and conductive trench shown in Fig. 3 and forms the section after tungsten structure and contact hole
Structural schematic diagram；
Fig. 5 shows deposited silicon nitride on the tungsten structure of groove shown in Fig. 4 and forms the cross-section structure after silicon nitride layer
Schematic diagram；
Fig. 6, which is shown, carries out selective etch the first silicon hole of formation to silicon nitride layer, interlayer dielectric layer and the substrate in Fig. 5
The schematic diagram of the section structure afterwards；
Fig. 7 is shown in the first silicon hole into Fig. 6 with deposition TEOS on silicon nitride layer and on interlayer dielectric layer
TEOS deposit and silicon nitride layer carry out CMP and obtain the schematic diagram of the section structure after TEOS layers；
Fig. 8, which shows to deposit copper on the TEOS layer in the first silicon hole shown in Fig. 7 and carry out CMP to copper, forms copper conduction
The schematic diagram of the section structure after layer；
Fig. 9 shows deposited metal on device architecture shown in Fig. 8 and forms the cross-section structure signal after metal interconnecting layer
Figure；
Figure 10 shows the schematic diagram of the section structure of align structures provided by a kind of preferred embodiment of the application；
Figure 11 shows the flow diagram of through silicon via production method provided by a kind of preferred embodiment of the application；
Figure 12 to Figure 23 shows the device profile structural schematic diagram after executing each step shown in Figure 11, wherein
Figure 12 is shown is successively set on interlayer dielectric layer and first Jie on the surface with gate structure in substrate
The schematic diagram of the section structure after electric layer；
Figure 13 shows the groove for being sequentially etched the first dielectric layer shown in Figure 12 and interlayer dielectric layer formation align structures
With the schematic diagram of the section structure after the conductive trench above gate structure；
Figure 14 shows the section being correspondingly formed after metal layer and contact hole in the groove shown in Figure 13 and conductive trench
Structural schematic diagram；
Figure 15 is shown on the first dielectric layer, metal layer and contact hole shown in Figure 14 after cvd nitride object formation nitration case
The schematic diagram of the section structure；
Figure 16 shows the schematic diagram of the section structure on nitration case shown in figure 15 after deposit polycrystalline silicon；
Figure 17 shows the schematic diagram of the section structure after the polysilicon except groove shown in removal Figure 16；
Figure 18, which is shown, is sequentially etched nitration case shown in Figure 17, the first dielectric layer, interlayer dielectric layer and substrate, forms the
The schematic diagram of the section structure after one silicon hole；
Figure 19 shows on the inner wall of the first silicon hole shown in Figure 18, deposits on exposed nitration case and on polysilicon layer
The schematic diagram of the section structure after dielectric spacer material；
Figure 20 shows the schematic diagram of the section structure deposited after conductive material in the dielectric spacer material shown in Figure 19；
Figure 21 shows the conductive material and dielectric spacer material of nitration case shown in removal Figure 20 or more, forms the first silicon
The conductive layer of through-hole and the schematic diagram of the section structure after dielectric barrier layer；
Figure 22 shows the schematic diagram of the section structure after the nitration case of the first dielectric layer shown in removal Figure 21 or more；
Figure 23 shows whole polysilicon layer shown in removal Figure 22 and forms the schematic diagram of the section structure after align structures；With
And
Figure 24 shows the metal of the first dielectric layer shown in Figure 23, dielectric barrier layer, conductive layer, contact hole, groove
The schematic diagram of the section structure after the first metal interconnecting layer is formed on layer and nitration case.
Specific embodiment
It is noted that following detailed description is all illustrative, it is intended to provide further instruction to the application.Unless another
It indicates, all technical and scientific terms used herein has usual with the application person of an ordinary skill in the technical field
The identical meanings of understanding.
It should be noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singular
Also be intended to include plural form, additionally, it should be understood that, when in the present specification using belong to "comprising" and/or " packet
Include " when, indicate existing characteristics, step, operation, device, component and/or their combination.
For ease of description, spatially relative term can be used herein, as " ... on ", " ... top ",
" ... upper surface ", " above " etc., for describing such as a device shown in the figure or feature and other devices or spy
The spatial relation of sign.It should be understood that spatially relative term is intended to comprising the orientation in addition to device described in figure
Except different direction in use or operation.For example, being described as if the device in attached drawing is squeezed " in other devices
It will be positioned as " under other devices or construction after part or construction top " or the device of " on other devices or construction "
Side " or " under other devices or construction ".Thus, exemplary term " ... top " may include " ... top " and
" in ... lower section " two kinds of orientation.The device can also be positioned with other different modes and (is rotated by 90 ° or in other orientation), and
And respective explanations are made to the opposite description in space used herein above.
As background technique is introduced, existing through silicon via is in manufacturing process, used align structures surfacing, benefit
It is difficult to quickly and accurately be positioned with optical detection structure, influences the subsequent order of accuarcy for being formed by through silicon via, to understand
Problem certainly as above, present applicant proposes a kind of align structures of the through silicon via of semiconductor devices production and the production sides of through silicon via
Method.
In a kind of preferred embodiment of the application, a kind of align structures for through silicon via production are provided, are such as schemed
Shown in 10, which includes substrate 100, interlayer dielectric layer 102, the first dielectric layer 103, groove 200,104 and of metal layer
Nitration case 106, interlayer dielectric layer 102 are arranged on the surface of substrate 100, and the first dielectric layer 103 is arranged in interlayer dielectric layer 102
On surface far from substrate 100, groove 200 is arranged through interlayer dielectric layer 102 and the first dielectric layer 103, and metal layer 104 is along recessed
The inner wall of slot 200 is arranged；Nitration case 106 is arranged on metal layer 104, wherein above-mentioned groove 200 has recess 201, the recess
201 are arranged on the nitration case 106.
Align structures with cross-section structure as shown in Figure 10, due to being provided with recess 201 in groove 200, in shape
At the presence after the first metal interconnecting layer 110 due to the recess 201, so that the first metal interconnecting layer 110 needs to fill out in production
It fills the recess 201 and then is formed small recess (as shown in figure 24) on the surface of the first metal interconnecting layer 110, and then utilizing it
When alignment, it can be quickly found out using the characteristics of its surface irregularity and be directed at the align structures, and improved and be formed by
The degree of registration of through silicon via.
In the application another preferred embodiment, above-mentioned align structures further include polysilicon layer 107, polysilicon layer
107 are located at upper surface of in the above-mentioned recess 201 and upper surface of polysilicon layer 107 lower than nitration case 106.With above structure
Align structures still have in groove 200 since the upper surface of polysilicon layer 107 is lower than the upper surface of nitration case 106
Depth is less than the dolly dimple of above-mentioned recess 201, and therefore, the surface for forming the first metal interconnecting layer 110 is still out-of-flatness,
And then the surface that can use out-of-flatness can quickly and accurately find the align structures.
As described above, the application mainly utilizes in above-mentioned align structures due to no polysilicon layer 107 or polysilicon
The recess that the upper surface of layer 107 is lower than the upper surface of interlayer dielectric layer 102 and is formed is aligned, in order to keep recess more bright
It is aobvious, it is more advantageous to and is quick and precisely aligned, preferably when with polysilicon layer 107, the characteristic size of above-mentioned groove is W1, depth be
L1, the characteristic size of above-mentioned dielectric barrier layer is W2, distance of the upper surface of above-mentioned dielectric barrier layer apart from upper surface of substrate be
L2, wherein W2For W130~80%, preferably 40~70%；L2For L11~70%, preferably 1~60%, further preferred 5~50%.
Features described above size is similar to this field usual definition, refers to the ruler of the corresponding component extended along channel width dimension
It is very little, the width size of groove 200 as shown in Figure 10, the width size of polysilicon layer 107.
The metal layer 105 of the application can be metal tungsten layer；The nitration case 106 of the application is silicon nitride layer or carbon containing
Silicon nitride layer.
In another typical embodiment of the application, a kind of production method of through silicon via is provided, Figure 11 is shown
The flow diagram of the production method.The production method includes: step S1, provides chip, and chip has substrate and is located at substrate
On the preceding road process structure of semiconductor；Step S2 makes align structures and the first through silicon via on chip；Step S3, using pair
Quasi- structure is directed at the first through silicon via with through silicon via mask open, and to carry out the production of through silicon via, which is above-mentioned
Align structures.
When using above-mentioned production method production through silicon via, the first through silicon via is formed while forming align structures, into
And make through silicon via to be formed and align structures position it is relatively fixed, it is logical further to make the second silicon using the align structures
Hole, third through silicon via ..., N through silicon via when, have the characteristics that out-of-flatness using above-mentioned align structures surface, can be quick
It is accurately located align structures position, and then the opening of align structures can be quickly right with align structures progress on mask plate
Standard carries out the etching of next step so that through silicon via mask open is precisely aligned in the first through silicon via formed on mask plate
When can accurately be performed etching above established first through silicon via, make the second through silicon via, third through silicon via ...,
N through silicon via is precisely aligned in three-dimensional structure, is extended, and complete through silicon via is formed.It can be seen that the silicon of the application is logical
Hole production method alignment speed is very fast and accurate, thus producing efficiency be improved and the levels of precision of obtained through silicon via compared with
It is high.Size those skilled in the art of above-mentioned N can set according to actual semiconductor design requirement, generally no greater than
10。
In another preferred embodiment of the application, the preceding road process structure of semiconductor in above-mentioned production method includes
Gate structure, above-mentioned steps S2 include: to set gradually interlayer dielectric layer and first on the surface with gate structure of substrate
Dielectric layer 103；It is sequentially etched the first dielectric layer 103 and interlayer dielectric layer 102, form the groove 200 of align structures and is located at grid
The conductive trench 300 of 101 top of pole structure；Metal layer 104 and contact hole are correspondingly arranged in groove 200 and conductive trench 300
105；Nitration case 106 is set on the first dielectric layer 103, metal layer 104 and contact hole 105；Nitration case in groove 200
Polysilicon layer 107 is set on 106 and etches to form the first silicon hole 400；108 He of dielectric barrier layer is set in the first silicon hole 400
Conductive layer 109 forms the first through silicon via；Remove the nitration case 106 of the first 103 or more dielectric layer；And removal is part or all of
The recess 201 of the formation align structures of polysilicon layer 107.
Above-mentioned production method utilizes the dielectric barrier layer for being filled in 106 top of nitration case in groove 200 in the prior art
Polysilicon layer 107 replaces, and by the adjustment to manufacture craft, above-mentioned part or all of polysilicon layer 107 is removed, so that recessed
There is recess 201 in slot 200 or depth is less than the dolly dimple of recess 201, then forming the interconnection of the first metal in deposited metal
When layer 110, remaining the extra position of space for needing metal to fill above align structures, and then it is formed by the first metal interconnecting layer
Upper surface can out-of-flatness.When using above-mentioned production method production through silicon via, the surface of align structures has the spy of out-of-flatness
Point, therefore can be quickly found out and be directed at the align structures, and improve the degree of registration for being formed by through silicon via.Above-mentioned system
Make method and implemented using ordinary skill in the art means using being, and each conventional technical means is combined to be formed it is above-mentioned
Production method, therefore the production method is simple, controllable, is conducive to implement on a large scale.
Now, the illustrative embodiments according to the application are more fully described with reference to the accompanying drawings.However, these are exemplary
Embodiment can be implemented by many different forms, and should not be construed to be limited solely to embodiment party set forth herein
Formula.It should be understood that it is thoroughly and complete to these embodiments are provided so that disclosure herein, and these are shown
The design of example property embodiment is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expands layer
With the thickness in region, and make that identical device is presented with like reference characters, thus description of them will be omitted.
Firstly, providing chip, which is the chip completed after the preceding road technique of semiconductor, has substrate 100 and semiconductor
The preceding road process structure of preceding road process structure, the preferably semiconductor includes gate structure 101.
Then, interlayer dielectric layer 102 and first is set gradually on the surface with gate structure 101 of substrate 100 to be situated between
Electric layer 103 forms the device with cross-section structure shown in Figure 12.The material for forming interlayer dielectric layer is low K electrolyte shape
At, such as phosphosilicate glass (PSG), boron phosphorus silicate glass (BPSG), fluorinated silicate glass (FSG), SiOxCy, spin coating
Glass, spin coating condensate, carbofrax material, their compound, their synthetic, their combination etc..Above-mentioned first is situated between
Electric layer 103 can be implemented using physical vaporous deposition commonly used in the art or chemical vapour deposition technique, wherein form first and be situated between
The material of electric layer 103 includes but is not limited to the ethyl orthosilicate of silicon nitride, carbon containing silicon nitride and ozone oxidation, preferably carbon containing
Silicon nitride, on the basis of playing the protective effect to interlayer dielectric layer 102, the first preferably above-mentioned dielectric layer 103 with a thickness of
10~200nm.
Then the first dielectric layer 103 and interlayer dielectric layer 102 shown in Figure 12 are performed etching, forms groove shown in Figure 13
200 and conductive trench 300.Above-mentioned etching process can use lithographic method commonly used in the art, formed groove 200 and conduction
Groove 300 is identical as groove in the prior art and conductive trench, and being formed by groove 200 is the align structures institute being subsequently formed
In position, it is formed by 105 position of contact hole that conductive trench formula is subsequently formed.In order to keep those skilled in the art more preferable
Ground understands the application, carries out property explanation illustrated below to lithographic method: photoresist is arranged on the first dielectric layer 103, then right
The photoresist is patterned processing, to form opening in groove 200 to be formed and the corresponding position of conductive trench 300, is scheming
Wet etching or dry etching are carried out to the first dielectric layer 103 and interlayer dielectric layer 102 under the protection of photoresist after shape.
After forming groove 200 and conductive trench 300, into groove 200 shown in Figure 13, in conductive trench 300 and
Deposited metal on first dielectric layer 103；Then chemical-mechanical planarization is carried out to the metal on the first dielectric layer 103, obtains figure
The metal layer 104 being formed in shown in 14 in groove 200 and the contact hole 105 being formed in conductive trench 300.It is above-mentioned to deposit
Journey can be implemented using the methods of chemical vapour deposition technique, physical vaporous deposition or plasma deposition, the gold deposited
Belonging to is preferably tungsten.
After forming metal layer 104, on the first dielectric layer 103, metal layer 104 and contact hole 105 shown in Figure 14
Cvd nitride object forms nitration case 106 shown in figure 15.Above-mentioned nitride is silicon nitride, carbon containing silicon carbide, oxygen containing nitridation
Silicon, preferably silicon nitride；Same deposition method can be heavy using chemical vapour deposition technique, physical vaporous deposition or plasma
Area method.
Polysilicon layer 107 is set simultaneously on nitration case 106 after nitration case 106 is formed in the groove 200 shown in Figure 15
Etching forms the first silicon hole 400.First silicon hole 400 identical as first silicon hole of this field is all that the first silicon being subsequently formed leads to
Hole position.According to the practice of this field, 400 characteristic size of the first silicon hole is formed by less than aforementioned grooves 200
Characteristic size, and the depth of the first silicon hole 400 is significantly greater than the depth of groove 200.
Above process those skilled in the art can be reference with the prior art, be implemented using technique appropriate, this
Application is preferably implemented using following two mode, and one of embodiment includes: to deposit on nitration case 106 shown in figure 15
Polysilicon forms the device with cross-section structure shown in Figure 16；The polysilicon except groove 200 is removed, is obtained shown in Figure 17
Polysilicon layer 107；It is sequentially etched nitration case 106 shown in Figure 17, the first dielectric layer 103, interlayer dielectric layer 102 and substrate 100,
The first silicon hole 400 shown in Figure 18 is formed, the above process is that the polysilicon first removed except groove 200 forms polysilicon layer 107,
Etching forms the first silicon hole 400 afterwards.Another embodiment includes: the deposit polycrystalline silicon on nitration case 106 shown in figure 15；According to
Secondary etches polycrystalline silicon, nitration case 106, the first dielectric layer 103, interlayer dielectric layer 102 and substrate 100 form the first silicon hole 400；
The polysilicon except groove 200 is removed, obtains polysilicon layer 107, second of embodiment is to be initially formed shape after the first silicon hole 400
At polysilicon layer 107.No matter use which kind of above-mentioned mode that can obtain structure shown in Figure 19, above embodiment is more in removal
Preferably chemical mechanical polishing method is used to implement when crystal silicon.
After the first silicon hole of shape 400, dielectric barrier layer shown in Figure 21 is set in the first silicon hole 400 shown in Figure 18
108 and conductive layer 109.This is located at the dielectric barrier layer 108 in the first silicon hole 400 and is used for the conductive material in the first through silicon via
It is isolated with substrate 100, avoids the first through silicon via and 100 break-through of substrate, make semiconductor device failure.The application forms above-mentioned
The material of dielectric barrier layer 108 includes but is not limited to silica, silicon oxide carbide or silicon oxynitride, preferably silicon oxide carbide or nitrogen oxidation
Silicon.In order to obtain more preferably dielectric isolation effect, preferably above-mentioned dielectric barrier layer 108 with a thickness of 50~1000nm.On
Stating setting up procedure can be implemented using the common method for forming the first through silicon via in this field.The application is preferably used with lower section
Formula, one way in which include:
It is deposited on the inner wall of the first silicon hole 400 shown in Figure 18, on exposed nitration case 106 and on polysilicon layer 107
Dielectric spacer material obtains the device with cross-section structure shown in Figure 19；Deposition is led in the dielectric spacer material shown in Figure 19
Electric material obtains the device with cross-section structure shown in Figure 20；Remove Figure 20 shown in 106 or more nitration case conductive material and
Dielectric spacer material forms conductive layer 109 and dielectric barrier layer 108 shown in Figure 21.
Another way includes: on the inner wall of the first silicon hole 400 shown in Figure 18, is on exposed nitration case 106 and more
Deposit dielectric isolated material on crystal silicon layer 107；Seed layer is covered (in figure not in the dielectric spacer material in the first silicon hole 400
It shows)；Conductive material is deposited on seed layer and dielectric spacer material；Remove the conductive material and dielectric of 106 or more nitration case
Isolated material forms conductive layer 109 and dielectric barrier layer 108 shown in Figure 21.Wherein, seed layer shape between deposited metal
At sedimentary origin being provided for metal, to improve deposition efficiency and good interface characteristics.
The deposition method of above-mentioned each mode dielectric isolated material and conductive material includes but is not limited to use physical vapor
Sedimentation, chemical vapour deposition technique and plasma deposition, it is preferred to use plasma deposition.Remove conductive material and Jie
It is electrically isolated the preferred chemical-mechanical planarization method of method of material.
After forming conductive layer 109 and dielectric barrier layer 108, the first 103 or more dielectric layer shown in Figure 21 is removed
Nitration case 106 obtains the device with cross-section structure shown in Figure 22.The process of above-mentioned removal nitration case 106 preferably uses chemistry
Wet etching method is implemented.Nitride is selected to select relatively high etachable material to perform etching with oxide etching, such as phosphoric acid.
After removing nitration case 106, polysilicon layer 107 some or all of shown in removal Figure 22 is removing whole polycrystalline
The recess 201 that align structures are formed after silicon layer 107, obtains the device with cross-section structure shown in Figure 23.Align structures include recessed
Metal layer 104, nitration case 106 in slot 200 and the recess 201 above nitration case 106, if polysilicon layer 107 does not have
Being completely removed align structures further includes partial polysilicon layer 107.The process of the above-mentioned part or all of polysilicon layer 107 of removal is adopted
Implemented with selective wet chemical etching, the etching agent of wet etching is preferably tetramethyl ammonium hydroxide solution, and the solution is to polysilicon
Selectivity is higher, and the etches polycrystalline silicon in etching does not etch other materials.During above-mentioned removal polysilicon layer, the
One dielectric layer 103 plays a protective role to interlayer dielectric layer 102 and its with flowering structure, and then avoids in removal polysilicon layer 107
During the semiconductor devices formed is caused to damage.
In order to further illustrate the technical effect of the application, after forming above-mentioned align structures, the shown in Figure 23
One dielectric layer 103, dielectric barrier layer 108, conductive layer 109, contact hole 105, groove 200 metal layer 104 and nitration case 106 on
Form the first metal interconnecting layer 110 shown in Figure 24.The use chemical vapor deposition of above-mentioned first metal interconnecting layer 110, physics
Vapor deposition or plasma deposited metal are formed.Since the upper surface of align structures is lower than the upper surface of interlayer dielectric layer 102,
Recess 201 is formed in 200 position of groove, therefore, in deposited metal, metal needs will fill the recess 201, then
After the deposition for completing metal, since the presence of recess deposits the first metal interconnecting layer 110 being located above align structures also
In small recess, then align structures can be quickly and accurately positioned when further making through silicon via using the align structures
Position, and then alignment mask plate can carry out rapid alignment with align structures, it can be accurate when carrying out the etching of next step
Ground performs etching above established through silicon via, and through silicon via is made to carry out precisely aligning extension in three-dimensional structure.
It can be seen from the above description that the application the above embodiments realize following technical effect:
1) recess, is provided in groove, therefore due to the presence of the recess after forming the first metal interconnecting layer, so that
One metal interconnecting layer needs to fill the recess in production and then forms small recess on the surface of the first metal interconnecting layer, in turn
When using its alignment, it can be quickly found out using the characteristics of its surface irregularity and be directed at the align structures, and improved
It is formed by the degree of registration of through silicon via；
2), the through silicon via production method alignment speed of the application is very fast and accurate, therefore producing efficiency is improved and institute
The levels of precision of obtained through silicon via is higher.
The foregoing is merely preferred embodiment of the present application, are not intended to limit this application, for the skill of this field
For art personnel, various changes and changes are possible in this application.Within the spirit and principles of this application, made any to repair
Change, equivalent replacement, improvement etc., should be included within the scope of protection of this application.
Claims (20)
1. a kind of align structures for through silicon via production, the align structures include:
Substrate (100)；
Interlayer dielectric layer (102) is arranged on the surface of the substrate (100)；
First dielectric layer (103) is arranged on the surface of the interlayer dielectric layer (102) far from the substrate (100)；
Groove (200) is arranged through the interlayer dielectric layer (102) and first dielectric layer (103)；
Metal layer (104), the inner wall along the groove (200) are arranged；
Nitration case (106) is arranged on the metal layer (104), which is characterized in that
The groove (200) has recess (201), and the recess (201) is arranged on the nitration case (106)；
The align structures further include polysilicon layer (107), and the polysilicon layer (107) is arranged in the nitration case (106)
Above, the polysilicon layer (107) is located in the recess (201) and the upper surface of the polysilicon layer (107) is lower than and institute
State the upper surface for the nitration case (106) that interlayer dielectric layer (102) flushes.
2. align structures according to claim 1, which is characterized in that the characteristic size of the groove (200) is W1, depth be
L1, the characteristic size of the polysilicon layer (107) is W2, the upper surface of the polysilicon layer (107) is apart from the substrate (100)
The distance of upper surface is L2, wherein W2For W130~80%；L2For L11~70%.
3. align structures according to claim 2, which is characterized in that W2For W140~70%；L2For L11~60%.
4. align structures according to claim 3, which is characterized in that L2For L15~50%.
5. according to claim 1 to align structures described in any one of 4, which is characterized in that the metal layer (105) is tungsten
Layer.
6. according to claim 1 to align structures described in any one of 4, which is characterized in that the nitration case (106) is silicon nitride
Layer.
7. a kind of production method of through silicon via, comprising:
Step S1 provides chip, the preceding road work of semiconductor that the chip has substrate (100) and is located on the substrate (100)
Skill structure；
Step S2 makes align structures and the first through silicon via on the chip；
Step S3 is directed at first through silicon via with through silicon via mask open using the align structures, to carry out the silicon
The production of through-hole, which is characterized in that the align structures are align structures described in any one of claims 1 to 6；Described half
The preceding road process structure of conductor includes gate structure (101), and the step S2 includes:
Interlayer dielectric layer (102) and are set gradually on the surface with the gate structure (101) of the substrate (100)
One dielectric layer (103)；
It is sequentially etched first dielectric layer (103) and the interlayer dielectric layer (102), forms the groove of the align structures
(200) and be located at the gate structure (101) above conductive trench (300)；
Metal layer (104) and contact hole (105) are correspondingly arranged in the groove (200) and the conductive trench (300)；
Nitration case (106) are set on first dielectric layer (103), the metal layer (104) and contact hole (105)；
Polysilicon layer (107) are set on the nitration case (106) in the groove (200) and etch to form the first silicon hole
(400)；
Setting dielectric barrier layer (108) and conductive layer (109) in first silicon hole (400), form first through silicon via；
Remove the nitration case (106) of first dielectric layer (103) or more；And
The partly or entirely described polysilicon layer (107) of removal forms the recess (201) of the align structures.
8. production method according to claim 7, which is characterized in that first dielectric layer (103) with a thickness of 10~
200nm。
9. production method according to claim 7, which is characterized in that the material for forming first dielectric layer (103) is
The ethyl orthosilicate of silicon nitride, carbon containing silicon nitride or ozone oxidation.
10. production method according to claim 7, which is characterized in that the setting up procedure of first dielectric layer (103) is adopted
Implemented with physical vaporous deposition, chemical vapour deposition technique or plasma deposition.
11. production method according to claim 7, which is characterized in that the metal layer (104) and the contact hole
(105) forming process includes:
In the groove (200), deposited metal in the conductive trench (300) and on first dielectric layer (103)；
Chemical-mechanical planarization is carried out to the metal on first dielectric layer (103), obtains being formed in the groove (200)
The metal layer (104) and the contact hole (105) that is formed in the conductive trench (300).
12. production method according to claim 7, which is characterized in that the nitration case in the groove (200)
(106) polysilicon layer (107) are arranged on and etch to form the process of the first silicon hole (400) and include:
The deposit polycrystalline silicon on the nitration case (106)；
The polysilicon except the groove (200) is removed, the polysilicon layer (107) are obtained；
It is sequentially etched the nitration case (106), first dielectric layer (103), the interlayer dielectric layer (102) and the substrate
(100), first silicon hole (400) is formed；Or
The deposit polycrystalline silicon on the nitration case (106)；
It is sequentially etched the polysilicon, the nitration case (106), first dielectric layer (103), the interlayer dielectric layer
(102) and the substrate (100) first silicon hole (400), is formed；
The polysilicon except the groove (200) is removed, the polysilicon layer (107) are obtained.
13. production method according to claim 12, which is characterized in that the process of the removal polysilicon is using chemical machine
Tool flattening method is implemented.
14. production method according to claim 7, which is characterized in that the setting dielectric barrier layer (108) and conductive layer
(109) process includes:
On the nitration case (106) on the inner wall of first silicon hole (400), exposed and on the polysilicon layer (107)
Deposit dielectric isolated material；
Conductive material is deposited in the dielectric spacer material；
Remove the nitration case (106) or more the conductive material and the dielectric spacer material, form the conductive layer
(109) and the dielectric barrier layer (108)；Or
On the nitration case (106) on the inner wall of first silicon hole (400), exposed and on the polysilicon layer (107)
Deposit dielectric isolated material；
Seed layer is covered in the dielectric spacer material in first silicon hole (400)；
Conductive material is deposited on the seed layer and the dielectric spacer material；
Remove the nitration case (106) or more the conductive material and the dielectric spacer material, form the conductive layer
(109) and the dielectric barrier layer (108).
15. production method according to claim 14, which is characterized in that the dielectric spacer material is silica, carbon oxygen
SiClx or silicon oxynitride.
16. the production method according to claim 7 or 14, which is characterized in that the dielectric barrier layer (108) with a thickness of
50~1000nm.
17. production method according to claim 14, which is characterized in that the process of the deposition conductive material uses physics
Vapour deposition process, chemical vapour deposition technique or plasma deposition are implemented.
18. production method according to claim 14, which is characterized in that conduction more than removal nitration case (106)
The process of material and dielectric spacer material is implemented using chemical mechanical planarization method.
19. production method according to claim 7, which is characterized in that the nitrogen more than removal the first dielectric layer (103)
The process for changing layer (106) is implemented using selective wet chemical etching method.
20. production method according to claim 7, which is characterized in that the part or all of polysilicon layer (107) of removal
Process using selective wet chemical etching implement, the etching agent of the wet etching includes tetramethylammonium hydroxide.
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| US6232200B1 (en) * | 1998-10-22 | 2001-05-15 | United Microelectronics Corp. | Method of reconstructing alignment mark during STI process |
| US20030017707A1 (en) * | 2001-07-19 | 2003-01-23 | Tomio Yamashita | Semiconductor device and method for manufacturing thereof |
| WO2004023551A1 (en) * | 2002-09-04 | 2004-03-18 | Infineon Technologies Ag | Mram mtj stack to conductive line alignment method |
| CN103035511A (en) * | 2011-10-09 | 2013-04-10 | 上海华虹Nec电子有限公司 | Method for producing zero layer photoetching marking of high-voltage device without barrier layers |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6232200B1 (en) * | 1998-10-22 | 2001-05-15 | United Microelectronics Corp. | Method of reconstructing alignment mark during STI process |
| US20030017707A1 (en) * | 2001-07-19 | 2003-01-23 | Tomio Yamashita | Semiconductor device and method for manufacturing thereof |
| WO2004023551A1 (en) * | 2002-09-04 | 2004-03-18 | Infineon Technologies Ag | Mram mtj stack to conductive line alignment method |
| CN103035511A (en) * | 2011-10-09 | 2013-04-10 | 上海华虹Nec电子有限公司 | Method for producing zero layer photoetching marking of high-voltage device without barrier layers |
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