TW201604993A - Etching method of high aspect-ratio structure and manufacturing method of MEMS devices - Google Patents

Abstract

The present invention discloses an etching method of a high aspect-ratio structure and a manufacturing method of MEMS devices. The etching method comprises a main etching process, a transition etching process and an over etching process. The main etching process is provided to etch a semiconductor substrate until reaching the upper position of a target depth, so as to form a first etching hole. The transition etching process is provided to control a process of continually etching the semiconductor substrate until reaching the target depth, so as to form a second etching hole with a critical dimension smaller than that of the first etching hole. The over etching process is provided to etch the side wall of the second etching hole so as to finally form a high aspect-ratio structure with the target depth. The present invention can protect the bottom of the high aspect-ratio structure from notching, so as to avoid the generation of notches during the etching process, thereby increasing the device performance.

Description

High aspect ratio structure etching method and MEMS device manufacturing method

The present invention relates to the technical field of semiconductor integrated circuit fabrication technology, and in particular, to a high aspect ratio structure etching method and a corresponding MEMS device fabrication method.

Deep reactive ion etching (DRIE) is an etching technique based on plasma technology. It is mainly used to process high aspect ratio microstructures with vertical sidewalls and has good verticality. This technology has greatly expanded the processing capability and scope of the physical manufacturing process in the past ten years, and is widely used in micro electro mechanical systems (MEMS) processing technology and emerging 3D interconnection technology. However, in the MEMS high aspect ratio microstructure processing based on SOI technology and the high aspect ratio structure processing of 3D interconnection based on SOI technology, DRIE technology has some effects that are considered to be unfavorable to the etching rate and structural contour, such as lateral etching ( Notching) effect.

The conventional RIE technology applied to MEMS processing technology and 3D interconnect technology realizes high aspect ratio etching based on the principle of Bosch technology. It is mainly composed of two steps: the first step, main etching (Main Etch), Forming the shape of the body of the high aspect ratio structure, in this step most of the crucible is quickly carved out to form a deep groove, mainly affecting the verticality of the body of the high aspect ratio structure; the second step, Over Etch, this step is used The flaws that are not exhausted in the main etching step are removed.

In order to improve the verticality and roughness requirements of the sidewalls of the vias, the existing RIE etched high aspect ratio structures typically employ Bosch techniques. U.S. Patent No. 5,501,893 describes Bosch technology that Bosch technology performs deep hole etching by means of deposition and etching alternately. The specific process is: providing a semiconductor substrate on which a photoresist mask layer having an opening is formed; performing an etching step: an etching gas (such as SF ₆ ) is introduced into the etching chamber, and the etching gas is dissociated For plasma, the semiconductor substrate is etched to form an etched hole; and a deposition step is performed: a deposition gas (for example, CF ₄ , C ₄ F ₈ ) is introduced into the etching chamber, and the deposition gas is dissociated into a plasma. The sidewalls of the etched holes form a polymer that protects the sidewalls of the formed etched holes from being etched during the next etching step, thereby ensuring anisotropy of the entire Bosch etching process; repeating the above etching step and deposition step The high-speed alternate cycle until a high aspect ratio structure is formed in the semiconductor substrate.

However, since electrons have a wider angular distribution than ions, the sidewalls and the mask shield the electrons more than the ions, and therefore, the ions reaching the bottom of the hole are more than electrons. When the main etch is finished (when the etch reaches the yttrium oxide buried layer of the SOI substrate), because yttrium oxide is an insulator, the ionic charge accumulates at the bottom of the trench, causing a difference in the potential at the bottom of the trench, which is accumulated when subsequent ions bombard the bottom of the trench. The repulsion of the charge changes to the bombardment of the sidewalls, causing the bottom of the sidewall to be eroded. A lateral depression (Notching) is produced as shown in Fig. 1.

Therefore, if the lateral etching effect is eliminated in the RIE etching of the MEMS device based on the SOI technology and the 3D interconnection, it becomes an extremely problem to be solved in the industry.

In order to eliminate the etching lateral depression, Chinese Patent ZL 200310122904.3 discloses a two-step over-etching method. The first step is high-pressure over-etching, which is easy to cause high-molecular polymer in the plasma to form on the bottom and bottom of the gate. Passivation of the protective layer, the second step is the general conventional over-etching, which has a slightly lower pressure than the first step to remove the undestroyed ruthenium residue. However, the etching time of the two-step over-etching is difficult to grasp. If the first etching time is longer, the passivation protective layer of the sidewall is thicker, the more the shape is inclined, the less likely the lateral groove appears; The longer the etching time is over the etch, the more vertical the gate is, but the greater the likelihood of lateral grooves appearing. Therefore, the method of this patent is difficult to ensure that there are no lateral grooves, while at the same time making the side wall topography as vertical as possible.

Chinese patent application CN103400800A discloses a Bosch etching method in which an etching step is performed by introducing an etching gas, applying a source RF power source to the reaction chamber to maintain a plasma concentration in the reaction chamber, and applying a first bias power source to the pedestal. Etching a portion of the substrate along the opening to form an etched hole; the depositing step is: introducing a deposition gas, applying a second bias power source to the pedestal, depositing a polymer on the sidewall surface of the etched hole and the surface of the mask layer, and second The frequency of the bias power source is greater than the frequency of the first bias power source. However, the etching method of the patent application requires continuous adjustment of the frequency of the bias power source for the etching and deposition steps, which increases the technical difficulty and cost, and is not conducive to the stability of the process.

SUMMARY OF THE INVENTION The object of the present invention is to remedy the above-mentioned deficiencies of the prior art, and to provide a high aspect ratio structure etching method by adding a one-step transient etching process between a main etching process and an over-etching process to avoid the occurrence of lateral recesses during etching.

To achieve the above object, the present invention provides a high aspect ratio structure etching method comprising the following steps:

Step S01, providing a semiconductor substrate;

Step S02, performing a main etching process, stopping to form a first etching hole when etching the semiconductor substrate to a position above the target depth, the main etching process comprising an etching step and a deposition step of alternating cycles, wherein the first etching hole defines a high depth The body shape of the wide ratio structure;

Step S03, performing a transient etching process to continue etching the semiconductor substrate to the target depth to form a second etching hole having a critical dimension smaller than the first etching hole, the transition etching process including an alternating cycle etching step and a deposition step, wherein the etching The etching/deposition rate ratio of the step and the deposition step is less than the etching/deposition rate ratio of the etching step and the deposition step in the main etching process;

Step S04, performing an over-etching process to etch sidewalls of the second etched holes to form a high aspect ratio structure in the semiconductor substrate that reaches the target depth.

Further, in step S02, the main etching process etches the semiconductor substrate to a height of 2-3 μm above the target depth to stop.

Further, in step S02, the etching depth of the main etching process is controlled by an end point detecting technique or a processing time.

Further, in step S03, the etching depth of the transient etching process is controlled by an etch end point detecting technique or a processing time.

Further, step S01 includes forming a patterned mask layer on the semiconductor substrate; the main etching process, the transition etching process, and the over-etching process each performing an etching process using the patterned mask layer as an etch mask .

Further, the etching/deposition rate ratio of the main etching process is 1:1 to 2:1, and the etching/deposition rate ratio of the transition etching process is 1:1 or less.

Further, in performing the main etching process, the transition etching process, and the over-etching process, the gas flowing into the processing chamber includes an etching gas and a deposition gas, the etching gas is SF ₆ , and the deposition gas is C ₄ F ₈ .

Further, in the main etching process, the transition etching process, and the over-etching process, the pressure, temperature, gas flow rate, and radio frequency source power of the processing chamber are the same; wherein the flow rate of the etching gas is 100 to 2000 sccm, and the flow rate of the deposition gas For the range of 100~2000sccm, the pressure of the processing chamber is 40~120 mTorr, the power of the source RF source is 1500~3000 watts, and the power of the bias RF source is output in pulses and is greater than 300 watts.

The present invention also provides a method for fabricating a MEMS device based on the above-described high aspect ratio structure etching method, comprising the steps of: providing a matrix substrate on which an oxide layer is deposited; providing a semiconductor substrate and interposing the matrix Bonding the substrate to the semiconductor substrate; performing a main etching process to stop forming the first etching hole when the semiconductor substrate is etched to a position above the bottom thereof, the main etching process including an alternating cycle etching step and a deposition step, An etch hole defines a body shape of the high aspect ratio structure; performing a transient etch process to continue etching the semiconductor substrate until the surface of the oxide layer is exposed to form a second etch hole having a critical dimension smaller than the first etch hole, the transition etch The process includes an alternating cycle of etching and deposition steps, wherein an etching/deposition rate ratio of the etching step and the deposition step is less than an etching/deposition rate ratio of the etching step and the deposition step in the main etching process; and performing an over etching process, etching a sidewall of the second etched hole to form a through hole of the semiconductor substrate Aspect ratio structures.

The present invention also provides a method for fabricating another MEMS device based on the above-described high aspect ratio structure etching method, comprising the steps of: providing a matrix substrate on which an oxide layer is formed; forming in the matrix substrate and the oxide layer a MEMS cavity; providing a semiconductor substrate and bonding the matrix substrate to the semiconductor substrate; performing a main etching process to stop forming the first etching hole when the semiconductor substrate is etched to a position above the bottom thereof, the main etching process An alternating etching step and a deposition step are included, the first etching hole defining a body shape of the high aspect ratio structure; performing a transient etching process to continue etching the semiconductor substrate to a bottom thereof to form a key to communicate with the MEMS cavity a second etching hole having a size smaller than the first etching hole, the transition etching process comprising an etching step and a deposition step of alternating cycles, wherein an etching/deposition rate ratio of the etching step and the deposition step is smaller than an etching step in the main etching process and Etching/deposition rate ratio of the deposition step; and performing an overetch process, etching the first Sidewalls of the etched hole through the semiconductor substrate to form a high aspect ratio and the MEMS structure and communicating with the cavity.

The high aspect ratio structure etching method provided by the present invention increases the step of a one-step transient etching process between a conventional main etching process and an over-etching process, wherein the main etching process etches the high aspect ratio structure to the target depth (such as the following layer) The etch stop layer is stopped at the upper position, and then a lower etching/deposition rate etching process is performed to protect the bottom of the high aspect ratio structure from being laterally etched by the overetch process, thereby avoiding lateral formation at the bottom of the high aspect ratio structure. The recess can significantly improve the performance of the device.

2 is a schematic flow chart of a high aspect ratio structure etching method according to the present invention, and FIGS. 3a to 3d are cross-sectional views showing respective steps of an etching method of a high aspect ratio structure. Please refer to FIG. 2 and FIG. 3a to FIG. 3d together. The etching method of the high aspect ratio structure is completed by a deep reactive ion etching (RIE) technique, which specifically includes the following steps:

In step S01, please refer to FIG. 3a to provide a semiconductor substrate 10.

In this step, the mask layer 11 is formed on the semiconductor substrate and patterned, and a window 11a exposing the surface of the semiconductor substrate is formed in the mask layer. The material of the mask layer may be selected from the group consisting of ruthenium oxide, tantalum nitride or a multilayer structure thereof, or a metal hard mask material such as titanium nitride, etc., which is not limited by the invention. The patterning of the mask layer can be achieved by conventional photolithography etching, which will not be described herein.

In step S02, referring to FIG. 3b, a main etching process is performed, which stops when the semiconductor substrate is etched to a position above the target depth to form a first etching hole.

In this step, the main etching process is a Bosch etching, including an etching step and a deposition step of alternating cycles. The specific process is as follows: the etching step is performed by plasma dry etching, and an etching gas such as SF _{6 is introduced} into the processing chamber, and the etching gas is ionized into a plasma to expose the exposed portion of the semiconductor substrate that is not covered by the mask layer. Etching, forming an etched hole; performing a deposition step to introduce a deposition gas into the etch chamber, such as C ₄ F ₈ , the deposition gas is ionized into a plasma, forming a polymer on the sidewall of the etched hole, the polymer is in the next etching step The sidewalls of the etched holes that have been formed are protected from etching, thereby ensuring the anisotropy of the entire Bosch etching technique. The above etching step and deposition step are repeated until the first etching hole 12 is formed in the semiconductor substrate as shown in FIG. 3b. It should be noted that the first etch hole 12 defines the shape of the finally formed high aspect ratio structure, but the depth is smaller than the target depth of the high aspect ratio structure, that is, when etched to a position above the target depth, the main etch The etching process is stopped to leave a portion of the thickness of the semiconductor substrate to be removed by the transient etching process and the overetch process. Preferably, the main etching process is to etch the semiconductor substrate to a height of 2-3 μm above the target depth, and the etching depth of the main etching process can be determined by the end point detection technique or the processing time control.

During the main etch process, the etch/deposition rate ratio is 1:1 to 2:1, which results in a faster etch rate, so the etched first etched via has a higher profile.

In step S03, referring to FIG. 3c, a transition etch process is performed to continue etching the semiconductor substrate to a target depth to form a second etch hole having a critical dimension smaller than the first etch hole.

In this step, the transition etch process is also a Bosch technique, including an alternating cycle of etching and deposition steps, and the mask layer remains as a mask for the transient etch process. Wherein, the etching step is performed by plasma dry etching, the etching gas is still selected by SF ₆ , and the deposition gas in the deposition step is still CF ₄ , and the etching step and the deposition step are alternately cycled. It is noted that the etching step and the deposition step in this step are required. The etch/deposition rate ratio is less than the etch/deposition rate ratio of the etch step and the deposition step in the main etch process, and the preferred etch/deposition rate ratio is less than or equal to 1:1. The transition etch process etches the semiconductor substrate along the first etch hole and forms a second dimension at the bottom of the first etch hole 12 that is less than a critical dimension of the first etched hole (ie, a critical dimension of the high aspect ratio structure) The hole 13 is etched as shown in Fig. 3c. The etch depth of the transient etch process can be determined by endpoint detection techniques or processing time control. The first etching hole 12 and the second etching hole 13 constitute a stepped hole. Generally, a portion of the semiconductor substrate material remains at the bottom sidewall of the second etching hole 13. Since the etching/deposition rate in this step is lower than that in the main etching process of step S01, the overall etching rate is slowed down, and the polymer formed in the deposition step is more formed on the sidewall of the second etching hole, which can offset the subsequent The bottom lateral depression caused by the over-etching process.

In step S03, referring to FIG. 3d, an over Etch process is performed to etch the sidewalls of the second etched holes to form a high aspect ratio structure of the target depth in the semiconductor substrate.

In this step, the mask layer is still used as an etch mask, and a Bosch technique including an alternate cycle of etching and deposition steps is still employed. Wherein, the etching step is performed by plasma dry etching, the etching gas is still selected by SF ₆ , the deposition gas in the deposition step is still CF ₄ , and the etching step and the deposition step are alternately cycled. In this step, the etching/deposition rate ratio of the etching step and the deposition step is greater than the etching/deposition rate ratio of the etching step and the deposition step in the transient etching process, for example, the same etching/deposition rate ratio that can be used for the main etching process, over etching The duration of the process is set according to the technical requirements and the etch/deposition rate ratio, which is the same as the prior art overetch process time, and generally occupies at least 20% of the entire high aspect ratio structure etch time. The transition etch process etches the sidewall of the second etched via 12, and also includes the semiconductor substrate material remaining at the bottom of the second etched via. Since the critical dimension of the second etched hole is smaller than the first etched hole, the lateral etch of the sidewall of the second etched via sidewall by the over etch process can remove the protruding step of the stepped via, so that the over etch process is finally formed. The high aspect ratio structure 14 of the target depth is achieved, and the bottom of the high aspect ratio structure does not create lateral grooves, thereby ensuring the integrity of the sidewalls of the high aspect ratio structure.

In the three steps of performing the main etching process, the transition etching process, and the over-etching process, the process parameters such as the pressure, temperature, gas flow rate, and RF source power of the processing chamber can be set to be the same, wherein the pressure range of the processing chamber is 40~120 mTorr, preferably 70 mTorr; the source RF source has a power of 1500~3000 watts, preferably 1800 watts; the bias RF source is pulsed and the power is greater than 300 watts, pulse duty cycle About 10%. The flow rate of the etching gas SF ₆ is 100 to 2000 sccm, and the flow rate of the deposition gas C ₄ F ₈ is 100 to 2000 sccm, preferably 1000 sccm.

The etching method of the high aspect ratio structure of the present invention can be applied to the preparation of the isolation trench and the fixed electrode of the MEMS device, and can also be applied to the preparation of the through hole TSV of the 3D interconnection. Next, the fabrication of the MEMS device isolation trench and the fixed electrode to which the high aspect ratio structure etching method of the present invention is applied will be described in detail with reference to specific embodiments. Example 1

In this embodiment, the isolation trench of the MEMS device based on the SOI technology is formed by applying the high aspect ratio structure etching method described above.

First, please refer to Figure 4a, providing a first semiconductor substrate 100, the first semiconductor substrate as a matrix substrate, also formed an oxide layer 101 thereon.

Then, referring to FIG. 4b, the second semiconductor substrate 200 is provided and bonded to one side of the first semiconductor substrate 100 having an oxide layer. The gluing technique is melt gluing or gluing, and the gluing method includes planarizing the surfaces of the first semiconductor substrate and the second semiconductor substrate, performing cleaning to remove surface contaminants, and placing the first and second semiconductor substrates relative to each other. Apply a certain pressure in a high temperature environment to combine the two. Specific process methods are well known to those skilled in the art and will not be described herein. The glued first semiconductor substrate, the oxide layer and the second semiconductor substrate form an SOI structure substrate, and serve as a top layer, an insulating layer and an underlayer layer, respectively.

Next, referring to FIG. 4c, the high aspect ratio structure 201 is etched in the second semiconductor substrate 200, including the foregoing main etching process step, the transient etching process step, and the over-etching process step, and the specific steps and processes of each etching technique. The parameters are basically the same as described above and will not be described in detail here. It should be noted that in the present embodiment, the target depth of the high aspect ratio structure is the oxide layer 101 reaching the SOI substrate, that is, equivalent to the thickness of the second semiconductor substrate. Specifically, when the main etching process step stops at a position above the bottom of the second semiconductor substrate 200 (ie, the upper surface of the oxide layer 101), the first etching hole defining the shape of the high aspect ratio structure body is formed. The transient etching process step continues to etch the second semiconductor substrate 200 to the bottom thereof along the first etching hole, stops at the oxide layer and exposes a portion of the upper surface of the oxide layer 101, and forms a second etching hole having a smaller critical dimension. The oxide layer 101 here serves as an etch stop layer, and a portion of the second semiconductor substrate material remains on the surface of the oxide layer after the transient etching process. The over-etching process etches the sidewalls of the second etched holes (including the second semiconductor substrate material remaining on the surface of the oxide layer 101), and finally etches a high aspect ratio structure that penetrates the second semiconductor substrate and has a uniform morphology. As shown in Fig. 4d, the bottom sidewall of the high aspect ratio structure has a smooth topography, which eliminates the occurrence of lateral etching in the prior art where DRIE etched SOI wafers are applied.

Finally, an isolation structure is formed in the high aspect ratio structure to form an isolation structure of the MEMS device based on SOI technology. Example 2

This embodiment forms a fixed electrode of a MEMS device based on SOI technology by applying the etching method of the high aspect ratio structure of the present invention. This embodiment can be implemented in combination with Embodiment 1 or independently.

First, please refer to Figure 5a, providing a first semiconductor substrate 100, the first semiconductor substrate as a matrix substrate, also formed an oxide layer 101 thereon.

Next, a recess 102 is formed in the first semiconductor substrate 100 and the oxide layer 101, which serves as a MEMS cavity of the MEMS device.

Then, referring to FIG. 5b, the second semiconductor substrate 200 is provided and glued to one side of the first semiconductor substrate 100 having a groove. The gluing technique is melt gluing or gluing. The glued first semiconductor substrate, the oxide layer and the second semiconductor substrate form a substrate of an SOI structure, and serve as a top layer of a SOI structure substrate, an insulating layer, and an underlayer layer, respectively.

Next, referring to FIG. 5c, a high aspect ratio structure 201 is etched at a position opposite to the MEMS cavity in the second semiconductor substrate 200, which includes the foregoing main etching process step, a transient etching process step, and an over etching process step, each of which The specific steps and process parameters of the etching technique are substantially the same as those described above and will not be described in detail herein. It should be noted that the target depth of the high aspect ratio structure in this embodiment is to reach the MEMS cavity, that is, the thickness of the second semiconductor substrate. Specifically, when the main etching process step is etched to the upper position of the bottom of the second semiconductor substrate 200, the first etching hole defining the shape of the high aspect ratio structure body is formed. The transition etch process step continues to etch the second semiconductor substrate 200 to the bottom of the second semiconductor substrate along the first etch hole to form a second etch hole that is in communication with the MEMS cavity and has a smaller critical dimension than the first etch hole. The overetching process etches the sidewalls of the second etched via to form a high aspect ratio structure that is contiguous throughout the second semiconductor substrate and that is in line with the MEMS cavity. Thus, the second semiconductor material formed with the high aspect ratio structure can serve as a fixed electrode of the MEMS device based on SOI technology.

In summary, the present invention provides a high aspect ratio structure etching method by adding a one-step transient etching step between conventional main etching and over etching, wherein the main etching process etches the high aspect ratio structure to the target depth. The upper position is stopped, followed by a further etching process with a lower etching/deposition rate ratio to avoid lateral etching caused by subsequent over-etching processes to create inward depressions at the bottom of the high aspect ratio structure, thereby improving device performance.

The present invention has been described in terms of the preferred embodiments of the present invention, and the present invention is intended to be illustrative only, and is not intended to limit the scope of the invention. To make a number of changes and refinements, the scope of protection claimed by the present invention shall be as described in the scope of the invention patent application.

S01~S04‧‧‧Steps
10‧‧‧Semiconductor substrate
11‧‧‧ mask layer
11a‧‧‧ window
12‧‧‧First etched hole
13‧‧‧Second etched hole
14, 201‧‧‧ high aspect ratio structure
100‧‧‧First semiconductor substrate
101‧‧‧Oxide layer
102‧‧‧ Groove
200‧‧‧second semiconductor substrate

The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which: FIG. 1 is a bottom of a high aspect ratio structure formed by the existing Bosch technique. 2 is a schematic flow chart of an etching method of a high aspect ratio structure of the present invention; FIGS. 3a to 3d are schematic cross-sectional views showing steps of an etching method of a high aspect ratio structure of the present invention; 4D is a schematic cross-sectional view showing a method of fabricating a MEMS device using an etching method of a high aspect ratio structure according to an embodiment of the present invention; and FIGS. 5a to 5c are diagrams showing a MEMS device using an etching method using a high aspect ratio structure according to another embodiment of the present invention; Schematic diagram of the section.

S01~S04‧‧‧Steps

Claims (10)

An etching method for a high aspect ratio structure, comprising the steps of: providing a semiconductor substrate; performing a main etching process, stopping the semiconductor substrate to a position above a target depth to form a first etching hole, the main etching process An etching step including an alternating cycle and a deposition step, the first etching hole defining a body shape of the high aspect ratio structure; performing a transition etching process to continue etching the semiconductor substrate to the target depth to form a critical dimension smaller than the first etching a second etch hole of the hole, the etch process comprising alternating cycles and the depositing step, wherein an etch/deposition rate ratio of the etch step and the deposit step is less than the etch step and the deposit in the main etch process An etching/deposition rate ratio of the step; and performing an over-etching process to etch a sidewall of the second etched hole to form a high aspect ratio structure in the semiconductor substrate to the target depth. The method of etching a high aspect ratio structure according to claim 1, wherein the main etching process etches the semiconductor substrate to a height of 2-3 μm above the target depth. An etching method of a high aspect ratio structure as described in claim 2, wherein the etching depth of the main etching process is controlled by an endpoint detection technique or a processing time. The etching method of the high aspect ratio structure according to claim 1, wherein the etching depth of the transient etching process is controlled by an etching end point detecting technique or a processing time. The method for etching a high aspect ratio structure according to claim 1, further comprising: forming a patterned mask layer on the semiconductor substrate; the main etching process, the transition etching process, and the over etching process are both The etching technique is performed with the patterned mask layer as an etch mask. The etching method of the high aspect ratio structure according to claim 1, wherein the etching/deposition rate ratio of the main etching process is 1:1 to 2:1, and the etching/deposition rate ratio of the transition etching process is less than or equal to 1:1. The method of etching a high aspect ratio structure according to claim 1, wherein the gas flowing into the processing chamber includes an etching gas and a gas during the main etching process, the transition etching process, and the over etching process. A deposition gas, the etching gas is SF ₆ , and the deposition gas is C ₄ F ₈ . The method of etching a high aspect ratio structure according to claim 7, wherein the main etching process, the transition etching process, and the pressure, temperature, gas flow rate, and RF source power of the processing chamber in the over etching process are both The same; the flow rate of the etching gas is 100~2000sccm, the flow rate of the deposition gas is 100~2000sccm, the pressure range of the processing chamber is 40~120 mTorr, the power of the source RF source is 1500~3000 watt, the bias RF source Power is output in pulses and is greater than 300 watts. A manufacturing method of a MEMS device, comprising the steps of: providing a matrix substrate on which an oxide layer is deposited; providing a semiconductor substrate and bonding the matrix substrate to the semiconductor substrate; performing a main etching process to etch the semiconductor Stopping to form a first etched hole when the substrate is in an upper position at the bottom thereof, the main etch process includes an etch step and a deposition step of alternating cycles, the first etch hole defining a body shape of the high aspect ratio structure; performing a transition An etching process, continuing to etch the semiconductor substrate until the surface of the oxide layer is exposed to form a second etch hole having a critical dimension smaller than the first etch hole, the etch process comprising an etch step and a deposition step of alternating cycles, wherein the etch An etching/deposition rate ratio of the step and the depositing step is less than an etching/deposition rate ratio of the etching step and the deposition step in the main etching process; and performing an over-etching process to etch sidewalls of the second etching hole to form A high aspect ratio structure penetrating the semiconductor substrate. A method of fabricating a MEMS device, comprising the steps of: providing a matrix substrate, forming an oxide layer on the matrix substrate; forming a MEMS cavity in the matrix substrate and the oxide layer; providing a semiconductor substrate and the matrix substrate Gluing with the semiconductor substrate; performing a main etching process to stop etching the semiconductor substrate to a position above the bottom thereof to form a first etching hole, the main etching process including an etching step and a deposition step of alternating cycles, the first etching process An etch hole defines a body shape of the high aspect ratio structure; performing a transition etch process to continue etching the semiconductor substrate to a bottom thereof to form a second etch hole having a critical dimension smaller than the first etch hole and communicating with the MEMS cavity, The transition etch process includes an etch step and a deposition step of alternating cycles, wherein an etch/deposition rate ratio of the etch step and the deposit step is less than an etch/deposition rate of the etch step and the deposition step in the main etch process And performing an etching process to etch sidewalls of the second etched holes to form a dry half Substrate and a high aspect ratio MEMS structure in communication with the cavity.