CN103811408B - A kind of deep silicon etching method for forming through hole - Google Patents
A kind of deep silicon etching method for forming through hole Download PDFInfo
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- CN103811408B CN103811408B CN201210445649.5A CN201210445649A CN103811408B CN 103811408 B CN103811408 B CN 103811408B CN 201210445649 A CN201210445649 A CN 201210445649A CN 103811408 B CN103811408 B CN 103811408B
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
- B81C1/00619—Forming high aspect ratio structures having deep steep walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
- B81C2201/0111—Bulk micromachining
- B81C2201/0112—Bosch process
Abstract
The present invention provides a kind of deep hole silicon etching method, is arranged in plasma processing chamber by pending silicon chip, and silicon chip surface includes patterned mask layer, is passed through the first reacting gas and performs etching silicon chip to be formed and have the opening of undercutting pattern to first degree of depth.Subsequently into alternately etching and the main etching stage of sidewall protection, after completing the main etching stage, form the sidewall with substantially vertical sidewall profile.
Description
Technical field
The present invention relates to Cement Composite Treated by Plasma field, particularly relate to a kind of deep hole silicon etching method to obtain more
Good sidewall profile.
Background technology
In technical field of manufacturing semiconductors, at MEMS(Micro-Electro-Mechanical Systems,
MEMS) and the field such as 3D encapsulation technology, it usually needs the materials such as silicon are carried out deep via etching.
Such as, in crystalline silicon lithographic technique, the degree of depth of deep silicon through hole (Through-Silicon-Via, TSV) reaches
To hundreds of micron, its depth-to-width ratio even much larger than 10, deep reaction ion etching method is generally used to etch
Body silicon is formed.Described silicon materials are mainly monocrystal silicon.The hole that the most oriented etching is formed after completing etching
Or in groove fill conductor material such as copper, fill method can be utilize chemical vapor deposition (CVD) or
Physical vapor deposition (PVD) process.Owing to the copper product of above-mentioned deposition deposits from the top down, institute
Most preferably need trapezoid-shaped openings with the TSV hole opening shape that etching is formed, or there is opening of vertical sidewall
Mouthful.
Existing typical lithographic technique is to utilize etching-deposition step alternately quickly to carve silicon
Erosion, etching method is again Bosch etching method at the moment.When using bosch etching method to be etched, shape
The hole sidewalls become is slight arc (bowing).Profile as shown in Figure 1a, etching is formed
Hole is all less than interlude diameter in top and bottom.Wherein enlarged drawing such as Fig. 1 b of the top opening part
Shown etachable material Rotating fields includes: mask layer 10(such as photoresist PR), be to treat below mask layer 10
The crystalline silicon material layer 20 of etching, etching forms hole 200.Such hatch frame is unfavorable for next step
Conductive material deposition, the less opening sidewalls in top can stop the further of conductive material in the hole of lower section
Deposition, it is likely that cavity can be yet suffered from hole after hole carries out conductive material filling step.This
The existence of a little cavitys not only can deteriorate conductive characteristic and the circuit needing conducting even can be caused to disconnect.By passing
In system Bosch etching method, the regulation of adjustable parameter cannot eliminate this disadvantageous sidewall profile.This results in
The hole using traditional B osch etching method to be formed brings problem in following process, ultimately results in whole product
Discarding of product, causes the biggest waste and loss.So industry needs a kind of simple and effective lithographic method
Improve deep hole silicon etching method.
Summary of the invention
It is an object of the invention to provide the hole pattern that a kind of deep hole silicon etching method makes etching be formed to be more suitable for
Fill in follow-up conductive material.Described deep hole silicon etching method is used for etching silicon chip, described silicon chip
On include a patterned mask layer, described lithographic method includes: the first etch stages, with described figure
The mask layer changed is the opening that mask etching silicon chip forms first degree of depth, between the sidewall of described opening both sides
It is gradually reduced away from from top down, terminates laggard etch stages of becoming owner of, described main quarter in the first etch stages
The erosion stage includes etching alternately and deposition step, is passed through etching gas to silica-based in etch step
Sheet performs etching, and is passed through fluorocarbon gases and carries out the opening sidewalls of etching formation in deposition step
Protection, the described main etching stage, etching silicon chip was from described first degree of depth to second degree of depth, made described the simultaneously
The sidewall separation of one depth increases.
Wherein said patterned mask layer has the first critical size, described after completing the main etching stage
Mask layer has the second critical size, described second critical size be more than described first critical size, first
Critical size is selected from 4-6um, and the second critical size is selected from 7-8um.
The etching gas of the first etch stages includes SF6, C4F8, O2.On the opening of described first degree of depth
Spacing between the wall of side is more than described first critical size.
Second degree of depth of wherein said main etching stage etching is more than 30um.Quarter in the main etching stage
The etching gas that erosion step is passed through is selected from one of SF6 and NF3.
Spacing between the sidewall separation of described first degree of depth opening open upper end sidewall less than 1.1 times, its
In first degree of depth more than 1um less than 6um.
Accompanying drawing explanation
Fig. 1 a is the overall generalized section that in prior art, etching forms deep silicon through hole；
Fig. 1 b is the close-up schematic view that in prior art, etching forms deep silicon through hole upper end；
On the deep silicon through hole that the lithographic method that Fig. 2 provides for utilizing the present invention is formed in etching pilot process
End close-up schematic view；
The lithographic method that Fig. 3 provides for utilizing present invention local of deep silicon through hole upper end when having etched is put
Big schematic diagram；
The lithographic method that Fig. 4 provides for utilizing the present invention completes the section of local, deep silicon through hole upper end during etching
Figure.
Detailed description of the invention
Below in conjunction with Fig. 2～Fig. 4, by preferred specific embodiment, describe the present invention in detail.
As in figure 2 it is shown, first carry out sidewall profile in etching process relative to prior art
Pre-corrected etches, and before carrying out follow-up deep hole silicon etching, first etching forms a undercutting pattern
(undercut), this undercutting, with suitable dimension, has one in mask layer following table towards the formation of hole both sides
Depthkeeping degree laterally etched.Mask layer 10 has distance D1 in the side-walls of opening part, namely mask
Layer CD a size of D1 now, the opening two of mask layer is namely close in the upper end of the hole that etching is formed
Side sidewall distance is D20, and wherein D20 is more than D1.The concrete D20 numerical value more than D1 can basis
Integral processing adjusts, and the difference of D20-D1 is offset follow-up at least above 1um to guarantee compensation
The pattern skew formed in etching.The difference of such as D20-D1 may be greater than 1um and is less than 6um,
That excellent can be 2-4um.The selection of this degree of depth is with the bowing that can be formed with follow-up main etch stages
The degree of depth that sidewall profile phase opening highlights offsets is advisable.At silicon chip after the etching completing undercutting pattern
One opening with certain depth of upper formation, this degree of depth can adjust etching technics as required and select
Select, typically want sufficiently large such as larger than 2um, the opening of formation both sides sidewall at upper-end contact mask layer
Spacing is more than the mask layer extended distance of top.The spacing of opening both sides sidewall is gradually reduced from top to bottom,
There is at the first depth H 1 of near-bottom first space D 21.Undercutting pattern is formed in etching
Time can use a variety of etching technics, mainly use SF6 can also use NF3 as etching gas
Deng etching gas, other fluorocarbons such as C4F8 and O2 is as auxiliary etch gas.As above-mentioned in used
Gas, under 50 millitorr air pressure, is passed through the SF6 gas of 1000sccm, the C4F8 gas of 150sccm
And the O2 gas of 50sccm, above-mentioned reacting gas is lighted plasma after being passed through reaction chamber, is continued
Within 10 seconds, just can form the undercutting pattern shown in Fig. 2.Except above-mentioned etching technics, other a lot of etching technics
Can be used to form described undercutting pattern such as: (1) air pressure is set as 100mT, be passed through 500sccm stream
The SF6 gas of amount and the O2 of 920sccm are passed through the C4F8 gas of 200sccm simultaneously and continue 15 seconds;
(2) air pressure is 150mt, is passed through the SF6 gas of 1500sccm flow, and the C4F8 of 800sccm
The O2 of gas and 600sccm continues 15 seconds;(3) maintain 150mT air pressure, be passed through 500sccm's
The C4F8 of O2 and 900sccm of SF6,800sccm maintains 15s.
After forming the undercutting pattern shown in Fig. 2, it is put into main etch step, uses traditional deep silicon
Via etch method such as Bosch etching method etches downwards, and replace utilizes the tropisms such as etching gas is carried out downwards
Etching certain depth, then protects at the hole sidewalls formed whole etching with fluorocarbon,
Subsequently enter the circulation of next etching-sidewall protection, until etching reaches the required degree of depth.Its
Middle etching and deposition step can complete once alternately to reduce the degree of roughness of sidewall within 2 seconds.Figure
2 Hole 200 sidewalls actually include the concavo-convex small striped alternately that a large amount of alternately etching is formed, by
In the inventive method not being impacted not shown in all figures.As shown in Figure 2 with photoresist as mask
Below etching during silicon the figure extended distance on photoresist from initial D1, namely critical size
D1(critical dimension) start etching downwards, owing to technique needs, open in downward etching process
Mouth distance needs to be gradually increased the last D2 etching completion status into as shown in Figure 3.When wherein starting
D1 can be 5um, to etching complete time D2 can be 7um, this just requires covering in etching process
The polymeric deposit of the formation on film layer 10 surface can not be the thickest, so the gas of C4F8 in etching gas
Content can not be the highest.Will also result in what etching was formed while polymeric layer is the thickest on mask layer 10 surface
The polymeric layer of hole sidewalls protection also will not be the thickest, so the phenomenon that partial sidewall is etched can be there is.
Downwardly extending process in etching from hole 200 upper opening, the distance of the mask layer opening of top also exists
Gradually extend to D2 from D1.This can cause the mask open when etching top silicon material layer little so corresponding
The hole diameter that formed of etching less, when etching the most further, mask open becomes big, accordingly
The hole value footpath of formation become big.Final in etching process, define that upper opening diameter is little and bottom is opened
The mouth the most this sidewall profile wished to of diameter.After applying the present inventive method, due to sidewall profile
Carried out pre-corrected, define shown in Fig. 2 undercutting pattern opening, so main etch step be
Start to etch downwards at the first depth H 1 shown in Fig. 2, when starting to etch between the first depth sidewall
Away from remaining D21.Along with the carrying out of etching is until the second whole etching of depth completes.Due to top
Mask layer critical size in long etching process is becoming big, so the main etching stage still can
Occur what the phenomenon of arc (bowing) sidewall, described curved wall pattern were formed in etching with the first step
Undercutting pattern compensates mutually, until completing the sidewall separation of the first depth to be made to reach D22 during etching,
D22 is more than aforementioned D21, and D22 with above and below the size of sidewall separation close.So opening
Mouth sidewall entirety pattern is the most perpendicular downwards, and subsequent deposition process will not cause the impact that do not works.Due to
Above-mentioned curved wall pattern gradually forms, so only just can compare etching depth is sufficiently large when
More apparent, etching depth of the present invention can reach more than 100um, the most greatly.Certainly the degree of depth is more than 30um
Time just can observe above-mentioned curved wall, the present invention can also be applied to put by the regulation of etch process parameters
The only incomplete problem of filling of subsequent filling stage.
It is that the ability present invention completes structural representation during etching as shown in Figure 3.Fig. 4 be actual application this
The material layer profile that bright method etching obtains.This is understood: invention is carrying out first step shape from Fig. 3 or 4
The effect superposition of silicon material layer 200 can be eliminated existing by both to carry out traditional etching again after becoming undercutting pattern
The part having technology etching hole 200 opening to extend internally, so prevents from follow-up conduction material
Material filling process is formed in packing material the result of cavity.The step formed due to described undercut etch is adopted
With traditional deep hole silicon etching gas, and the time carried out is the shortest only about 10 seconds, and the most existing
Some system hardwares do not have extra demand, thus use the present invention can not increase extra cost and
Simple method is utilized to realize the correction to sidewall profile under the front topic of time.
Present invention could apply to Capacitance Coupled (CCP) type plasma treatment appts or inductive type
(ICP) plasma treatment appts
Although present disclosure has been made to be discussed in detail by above preferred embodiment, but it should understanding
It is not considered as limitation of the present invention to the description above.Read above-mentioned those skilled in the art
After content, multiple amendment and replacement for the present invention all will be apparent from.Therefore, the present invention
Protection domain should be limited to the appended claims.
Claims (9)
1. a deep hole silicon etching method, is used for etching silicon chip, described silicon chip includes one patterned covers
Film layer, described lithographic method includes
First etch stages, forms first with described patterned mask layer for mask etching silicon chip deep
The opening of degree (H1), the spacing of described opening both sides sidewall is gradually reduced from top down, and
First depth has the first side wall spacing (D21),
Terminate laggard etch stages of becoming owner of in the first etch stages, the described main etching stage include replacing into
The etching of row and deposition step, be passed through etching gas in etch step and perform etching silicon chip,
Deposition step is passed through fluorocarbon gases the opening sidewalls of etching formation is protected, described master
Etch stages, described opening to second degree of depth, makes described first deep from described first deep etching simultaneously
The first side wall spacing at degree increases to the second spacing (D22)；
Described patterned mask layer has the first critical size in the first etch stages, completes main quarter
After the erosion stage, described mask layer has the second critical size, and described second critical size is more than described first
Critical size.
2. lithographic method as claimed in claim 1, it is characterised in that the etching gas of described first etch stages
Body includes SF6, C4F8, O2.
3. lithographic method as claimed in claim 1, it is characterised in that the of described main etching stage etching
Two degree of depth are more than 30um.
4. lithographic method as claimed in claim 1, it is characterised in that the etching step in the described main etching stage
Suddenly the etching gas being passed through is selected from one of SF6 and NF3.
5. lithographic method as claimed in claim 1, it is characterised in that described first etch stages formed the
Spacing (D20) between one degree of depth open upper end sidewall is more than described first critical size (D1) 1um
Above.
6. lithographic method as claimed in claim 1, it is characterised in that described first etch stages formed the
Spacing between one degree of depth open upper end sidewall is more than described first critical size, and difference is more than 1um
Less than 6um.
7. lithographic method as claimed in claim 1, it is characterised in that described first critical size is selected from 4-6um,
Second critical size is selected from 7-8um.
8. lithographic method as claimed in claim 1, it is characterised in that the hypomere side of described first degree of depth opening
Wall is smaller than the spacing between the open upper end sidewall of 1.1 times.
9. lithographic method as claimed in claim 1, it is characterised in that described first degree of depth is more than 2um.
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105448697B (en) * | 2014-07-18 | 2018-05-01 | 中微半导体设备(上海)有限公司 | The lithographic method of high aspect ratio structure and the production method of MEMS device |
| CN105720003B (en) * | 2014-12-03 | 2019-01-18 | 北京北方华创微电子装备有限公司 | Deep silicon hole lithographic method |
| CN108648994A (en) * | 2018-05-15 | 2018-10-12 | 长江存储科技有限责任公司 | Forming method, groove structure and the memory of groove structure |
| CN110937567B (en) * | 2018-09-21 | 2022-12-13 | 国家纳米科学中心 | Silicon-based quadrangular frustum pyramid-shaped micro through hole array, and preparation method and application thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4814041A (en) * | 1986-10-08 | 1989-03-21 | International Business Machines Corporation | Method of forming a via-hole having a desired slope in a photoresist masked composite insulating layer |
| CN101962773A (en) * | 2009-07-24 | 2011-02-02 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Deep silicon etching method |
| CN102398887A (en) * | 2010-09-14 | 2012-04-04 | 中微半导体设备(上海)有限公司 | Deep hole silicon etching method |
| CN102543836A (en) * | 2010-12-21 | 2012-07-04 | 无锡华润上华半导体有限公司 | Method for etching through hole |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20100090974A (en) * | 2009-02-09 | 2010-08-18 | 삼성전자주식회사 | Methods of forming a semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4814041A (en) * | 1986-10-08 | 1989-03-21 | International Business Machines Corporation | Method of forming a via-hole having a desired slope in a photoresist masked composite insulating layer |
| CN101962773A (en) * | 2009-07-24 | 2011-02-02 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Deep silicon etching method |
| CN102398887A (en) * | 2010-09-14 | 2012-04-04 | 中微半导体设备(上海)有限公司 | Deep hole silicon etching method |
| CN102543836A (en) * | 2010-12-21 | 2012-07-04 | 无锡华润上华半导体有限公司 | Method for etching through hole |
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Address after: 201201 No. 188 Taihua Road, Jinqiao Export Processing Zone, Pudong New Area, Shanghai Patentee after: Medium and Micro Semiconductor Equipment (Shanghai) Co., Ltd. Address before: 201201 No. 188 Taihua Road, Jinqiao Export Processing Zone, Pudong New Area, Shanghai Patentee before: Advanced Micro-Fabrication Equipment (Shanghai) Inc. |
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