CN105720002A - Oblique hole etching method - Google Patents
Oblique hole etching method Download PDFInfo
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- CN105720002A CN105720002A CN201410727656.3A CN201410727656A CN105720002A CN 105720002 A CN105720002 A CN 105720002A CN 201410727656 A CN201410727656 A CN 201410727656A CN 105720002 A CN105720002 A CN 105720002A
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Abstract
The invention provides an oblique hole etching method for etching an oblique hole in the surface of a silicon wafer. The entire etching process is divided into two steps which are a first etching step of using a fluorocarbon-based gas as the etching gas for removing a natural oxide layer formed on the surface of the silicon wafer; and a second etching step of using SF6 as the etching gas, O2 as the protection gas and HBr and He as the auxiliary gas, and setting the flow ratio of O2 and SF6, process pressure, top electrode power, bottom electrode power and temperature of the silicon wafer to etch and form a desired V-shaped hole. The oblique hole etching method provided by the invention can used for obtaining the desired V-shaped hole of which the side wall is straight, the top is not curved, the line width is not reduced and the depth is relatively high.
Description
Technical field
The present invention relates to microelectronics technology, particularly to a kind of inclined hole lithographic method.
Background technology
3D encapsulation is in different types of Integration ofTechnology to single package, will to replace long 2D interconnection with short perpendicular interconnection, have the reduction advantage such as ghost effect and power consumption.3DTSV (ThroughSiliconVia, silicon through hole) is by making vertical conducting between chip and chip, between wafer and wafer, it is achieved the state-of-the-art technology of interconnection between chip.The etching technics of inclined hole is the important means being capable of TSV and encapsulation field at present, this is because: for straight hole, especially there is the straight hole of certain depth-to-width ratio, the difficulty that after strengthening, the PVD in road fills, and inclined hole, especially the inclined hole of high-aspect-ratio is more beneficial for the PVD filling in rear road.
Existing inclined hole lithographic method is to adopt SF6、C4F8And O2Mixing gas as etching gas on silicon chip single step etching inclined hole.Typical technological parameter is: chamber pressure is 100mT；SF6Throughput be 700sccm；C4F8Throughput be 100sccm；O2Throughput be 50sccm；Upper electrode power is 2000W；Lower electrode power is 20W.Fig. 1 is the electron-microscope scanning figure of the inclined hole adopting existing inclined hole lithographic method to obtain.As shown in Figure 1, there is following defect in actual applications in above-mentioned inclined hole lithographic method:
One, due to C4F8A large amount of additions, the CF group being generated by can make inclined hole sidewall roughness, top side wall zigzag pattern occur from mask effect.Meanwhile, higher ion bombardment energy also can make inclined hole sidewall roughness.
They are two years old, it is thus achieved that the depth-to-width ratio less (about 1:1) of inclined hole, and in etching process, along with the increase of etching depth, it is easy to occur that etching stops.
They are three years old, owing to being subject to opening size restriction and mask blocks, air-flow can form quiescent centre, a flow field at inclined hole top, cause that gas is long in the inclined hole top holdup time, thus not only causing top side wall that buckling phenomenon (bowing) occurs, but also bigger line width loss can occur at inclined hole top.
Summary of the invention
It is contemplated that at least solve one of technical problem of existence in prior art, it is proposed that a kind of inclined hole lithographic method, it is possible not only to obtain desirable " V " shape hole, it may be assumed that sidewall is straight and top is without bending, without line width loss, and the depth-to-width ratio of inclined hole is higher.
There is provided a kind of inclined hole lithographic method for realizing the purpose of the present invention, for etching inclined hole on silicon chip surface, whole etching process is divided into two steps by it, is respectively as follows:
First etch step, adopts carbon fluorine type gas as etching gas, for removing the natural oxidizing layer formed on described silicon chip surface；
Second etch step, adopts SF6、O2, HBr and He as etching gas, concurrently set corresponding technological parameter, for etching formed desirable " V " shape hole；Described technological parameter includes described O2And SF6Flow-rate ratio, operation pressure, upper electrode power, lower electrode power and silicon temperature.
Preferably, described carbon fluorine type gas includes CF4And CHF3In at least one.
Preferably, operation pressure and lower electrode power that described first etch step adopts are set to: make anisotropic etching increase, quickly to remove described natural oxidizing layer.
Preferably, the span of described operation pressure is at 4～10mT, and the span of described lower electrode power is at 60～120W.
Preferably, described second etch step adopts operation pressure and described O2And SF6Flow-rate ratio be set to: improve the ionization level of described etching gas, improve the protection to sidewall simultaneously and form it into V shaped hole pattern.
Preferably, the span of described operation pressure at 20～40mT, described O2And SF6The span of flow-rate ratio at 1.2:1～2:1.
Preferably, described O2The span of flow at 20～35sccm, described SF6The span of flow at 15～30sccm.
Preferably, the span of the flow of described He is at 40～100sccm, and the span of the flow of described HBr is at 6～10sccm.
Preferably, described second etch step adopts upper electrode power and lower electrode power are set to: make sidewall straight.
Preferably, the span of described upper electrode power is at 450～550W, and the span of described lower electrode power is at 20～60W.
Preferably, the span of the silicon temperature that described second etch step adopts is at-10～0 DEG C.
The method have the advantages that
Inclined hole lithographic method provided by the invention, whole etching process is divided into two steps by it, and wherein, the first etch step adopts carbon fluorine type gas as etching gas, for removing the natural oxidizing layer formed on silicon chip surface；Second etch step adopts SF6、O2, HBr and He as etching gas, concurrently set corresponding technological parameter, i.e. O2And SF6Flow-rate ratio, operation pressure, upper electrode power, lower electrode power and silicon temperature, form desirable " V " shape hole for etching, i.e. sidewall is straight and top is without bending, without line width loss, and the depth-to-width ratio of inclined hole is higher.
Accompanying drawing explanation
Fig. 1 is the scanning electron microscope (SEM) photograph of the inclined hole adopting existing inclined hole lithographic method to obtain；
Fig. 2 is the FB(flow block) of inclined hole lithographic method provided by the invention；And
Fig. 3 is the scanning electron microscope (SEM) photograph of the inclined hole adopting inclined hole lithographic method provided by the invention to obtain.
Detailed description of the invention
For making those skilled in the art be more fully understood that technical scheme, below in conjunction with accompanying drawing, inclined hole lithographic method provided by the invention is described in detail.
The whole process etching inclined hole on silicon chip surface is: pass into etching gas and assist gas to reaction chamber, and open upper electrode supply (such as radio-frequency power supply), upper electrode supply is for being applied with electrode power to reaction chamber, so that the etching gas in reaction chamber excites formation plasma；Opening bottom electrode power supply, bottom electrode power supply is for applying lower electrode power to silicon chip, so that plasma etching silicon chip, until forming the inclined hole with predetermined etching depth on the surface to be etched of silicon chip.In actual applications, inductively coupled plasma (InductivelyCoupledPlasma, hereinafter referred to as ICP) equipment is generally adopted to carry out above-mentioned etching technics.
Fig. 2 is the FB(flow block) of inclined hole lithographic method provided by the invention.Referring to Fig. 2, inclined hole lithographic method provided by the invention, for etching inclined hole on silicon chip surface, whole etching process is divided into two steps by it, is respectively as follows:
First etch step, adopts carbon fluorine type gas as etching gas, for removing the natural oxidizing layer formed on institute's silicon chip surface；
Second etch step, adopts SF6、O2, HBr and He as etching gas, concurrently set corresponding technological parameter, i.e. O2And SF6Flow-rate ratio, operation pressure, upper electrode power, lower electrode power and silicon temperature, form desirable " V " shape hole for etching.
In the first etch step, comprising F due in the plasma that formed by carbon fluorine type gas, it can react with the natural oxidizing layer on silicon chip surface, to be consumed by this natural oxidizing layer.Thus, by carrying out above-mentioned first etch step at the etching initial stage, it is possible to avoid occurring in subsequent etching process that because of the existence of natural oxidizing layer top side wall produces " incision phenomenon " (undercut), and then line width loss can be reduced.Above-mentioned carbon fluorine type gas preferably employs the gas that carbon/fluorine is smaller, for instance CF4And CHF3In at least one.
Preferably, operation pressure and lower electrode power that above-mentioned first etch step adopts are set to: make anisotropic etching increase, quickly to remove natural oxidizing layer.All being conducive to due to relatively low operation pressure and higher lower electrode power increasing anisotropic etching, therefore, the span of operation pressure is at 4-10mT, it is preferred to 7mT；The span of lower electrode power is at 60～120W, it is preferred to 80W.Operation pressure and lower electrode power value in above-mentioned span all can realize quickly removing the purpose of natural oxidizing layer.
In a second etching step, SF6And O2For main etching gas；HBr and He is assist gas.Wherein, SF6It is mainly used in silicon substrate is played the effect of etching；O2For forming protective layer at sidewall.Preferably, operation pressure and O2And SF6Flow-rate ratio be set to: improve etching gas ionization level, improve the protective effect to sidewall simultaneously.Due to O2And SF6Flow-rate ratio more big, the protective effect of sidewall is more strong, simultaneously because higher operation pressure can make etching gas ionize more fully, i.e. ionization level improve, therefore, by when higher operation pressure, suitably improving O2And SF6Flow-rate ratio, it is possible to while improving the ionization level of etching gas, improve protection to sidewall, thus obtaining desirable " V " shape hole shape looks.O2And SF6The span of flow-rate ratio at 1.2:1～2:1, it is preferred to 1.5:1；The span of operation pressure is at 20-40mT, it is preferred to 32mT.Operation pressure and O2And SF6Flow-rate ratio value in above-mentioned span all can realize improving the ionization level of described etching gas, improve the effect of the protection to sidewall simultaneously.On this basis, O2The span of flow at 20～35sccm, it is preferred to 26sccm；SF6The span of flow at 15～30sccm, it is preferred to 18sccm.
HBr and He as assist gas, is possible not only to change the gas gross in reaction chamber, and can so that being more evenly distributed of process gas, such that it is able to improve process uniformity.Meanwhile, HBr can also play raising etch rate, raising etching selection ratio and protective side wall top and avoid producing the effect of buckling phenomenon (bowing).Thus, the second etch step is by adopting SF6、O2, HBr and He is as etching gas, it is possible to play the effect modifying sidewall profile, ultimately form desirable " V " shape hole.The span of the flow of He is at 40～100sccm, it is preferred to 50sccm.The span of the flow of HBr is at 6～10sccm, it is preferred to 8sccm.
It is further preferred that the upper electrode power that adopts of the second etch step and lower electrode power are set to: make sidewall straight.Owing to relatively low upper electrode power and lower electrode power can be avoided producing buckling phenomenon in top side wall, it is thus achieved that straight sidewall.Therefore, the span of upper electrode power is at 450～550W, it is preferred to 500W.The span of lower electrode power is at 20～60W, it is preferred to 30W.
Additionally, it is preferred that, the silicon temperature that the second etch step adopts is set to: be conducive at deposited on sidewalls protective layer.In actual applications, silicon temperature is generally controlled by cooler (chiller), and here, silicon temperature refers to the chilling temperature of cooler.Owing to the height of silicon temperature is also the key factor affecting silicon hole pattern, and, this silicon temperature is more low, is more conducive to the deposition of side wall protective layer, and therefore, the span of silicon temperature is at-10～0 DEG C, it is preferred to 0 DEG C.
Inclined hole lithographic method provided by the invention is adopted to perform etching experiment below.Specifically, this etching technological parameter of adopting of experiment particularly as follows:
In the first etch step, adopt CHF3As etching gas, its flow is 80sccm；Operation pressure is 7mT；Upper electrode power is 350W；Lower electrode power is 80W；Silicon temperature is 0 DEG C；Process time is 7s.
In a second etching step, SF is adopted6、O2, HBr and He is as etching gas, SF6Flow be 18sccm；O2Flow be 26sccm；The flow of HBr is 8sccm；The flow of He is 50sccm；Operation pressure is 32mT；Upper electrode power is 500W；Lower electrode power is 30W；Silicon temperature is 0 DEG C；Process time is 600s.
Adopt inclined hole lithographic method provided by the invention to perform etching technique with above-mentioned technological parameter, it is thus achieved that silicon hole pattern as shown in Figure 3.As seen from the figure, inclined hole lithographic method provided by the invention is adopted, it is possible to obtain desirably " V " shape hole, i.e. sidewall is straight and top is without bending, without line width loss, and the depth-to-width ratio of inclined hole is up to 10:1～15:1.
It is understood that the principle that is intended to be merely illustrative of the present of embodiment of above and the illustrative embodiments that adopts, but the invention is not limited in this.For those skilled in the art, without departing from the spirit and substance in the present invention, it is possible to make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (11)
1. an inclined hole lithographic method, for etching inclined hole, it is characterised in that whole etching process is divided into two steps, is respectively as follows: on silicon chip surface
First etch step, adopts carbon fluorine type gas as etching gas, for removing the natural oxidizing layer formed on described silicon chip surface；
Second etch step, adopts SF6、O2, HBr and He as etching gas, concurrently set corresponding technological parameter, for etching formed desirable " V " shape hole；Described technological parameter includes described O2And SF6Flow-rate ratio, operation pressure, upper electrode power, lower electrode power and silicon temperature.
2. inclined hole lithographic method as claimed in claim 1, it is characterised in that described carbon fluorine type gas includes CF4And CHF3In at least one.
3. inclined hole lithographic method as claimed in claim 1, it is characterised in that operation pressure and lower electrode power that described first etch step adopts are set to: make anisotropic etching increase, quickly to remove described natural oxidizing layer.
4. inclined hole lithographic method as claimed in claim 3, it is characterised in that the span of described operation pressure is at 4～10mT, and the span of described lower electrode power is at 60～120W.
5. inclined hole lithographic method as claimed in claim 1, it is characterised in that operation pressure that described second etch step adopts and described O2And SF6Flow-rate ratio be set to: improve the ionization level of described etching gas, improve the protection to sidewall simultaneously and form it into V shaped hole pattern.
6. inclined hole lithographic method as claimed in claim 5, it is characterised in that the span of described operation pressure at 20～40mT, described O2And SF6The span of flow-rate ratio at 1.2:1～2:1.
7. inclined hole lithographic method as claimed in claim 6, it is characterised in that described O2The span of flow at 20～35sccm, described SF6The span of flow at 15～30sccm.
8. inclined hole lithographic method as claimed in claim 1, it is characterised in that the span of the flow of described He is at 40～100sccm, and the span of the flow of described HBr is at 6～10sccm.
9. inclined hole lithographic method as claimed in claim 1, it is characterised in that upper electrode power and lower electrode power that described second etch step adopts are set to: make sidewall straight.
10. inclined hole lithographic method as claimed in claim 9, it is characterised in that the span of described upper electrode power is at 450～550W, and the span of described lower electrode power is at 20～60W.
11. inclined hole lithographic method as claimed in claim 1, it is characterised in that the span of the silicon temperature that described second etch step adopts is at-10～0 DEG C.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111128715A (en) * | 2019-12-27 | 2020-05-08 | 爱特微(张家港)半导体技术有限公司 | Method for etching deep groove |
| TWI784796B (en) * | 2020-11-16 | 2022-11-21 | 大陸商北京北方華創微電子裝備有限公司 | Etching method of silicon wafer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101446760A (en) * | 2007-11-30 | 2009-06-03 | 台湾积体电路制造股份有限公司 | Double patterning strategy for contact hole and trench |
| US20100310995A1 (en) * | 2009-02-11 | 2010-12-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Double patterning strategy for contact hole and trench in photolithography |
| CN102142377A (en) * | 2011-01-30 | 2011-08-03 | 福建福顺微电子有限公司 | Production method of silicon groove of power MOS (Metal Oxide Semiconductor) device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101446760A (en) * | 2007-11-30 | 2009-06-03 | 台湾积体电路制造股份有限公司 | Double patterning strategy for contact hole and trench |
| US20100310995A1 (en) * | 2009-02-11 | 2010-12-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Double patterning strategy for contact hole and trench in photolithography |
| CN102142377A (en) * | 2011-01-30 | 2011-08-03 | 福建福顺微电子有限公司 | Production method of silicon groove of power MOS (Metal Oxide Semiconductor) device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111128715A (en) * | 2019-12-27 | 2020-05-08 | 爱特微(张家港)半导体技术有限公司 | Method for etching deep groove |
| TWI784796B (en) * | 2020-11-16 | 2022-11-21 | 大陸商北京北方華創微電子裝備有限公司 | Etching method of silicon wafer |
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