CN102142377A - Production method of silicon groove of power MOS (Metal Oxide Semiconductor) device - Google Patents

Production method of silicon groove of power MOS (Metal Oxide Semiconductor) device Download PDF

Info

Publication number
CN102142377A
CN102142377A CN2011100327857A CN201110032785A CN102142377A CN 102142377 A CN102142377 A CN 102142377A CN 2011100327857 A CN2011100327857 A CN 2011100327857A CN 201110032785 A CN201110032785 A CN 201110032785A CN 102142377 A CN102142377 A CN 102142377A
Authority
CN
China
Prior art keywords
etching
silicon trench
metal oxide
oxide semiconductor
flow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011100327857A
Other languages
Chinese (zh)
Other versions
CN102142377B (en
Inventor
张鹏
熊爱华
梅海军
李豪
林立桂
林善彪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
FUJIAN FUSHUN MICROELECTRONIC Co Ltd
Original Assignee
FUJIAN FUSHUN MICROELECTRONIC Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by FUJIAN FUSHUN MICROELECTRONIC Co Ltd filed Critical FUJIAN FUSHUN MICROELECTRONIC Co Ltd
Priority to CN 201110032785 priority Critical patent/CN102142377B/en
Publication of CN102142377A publication Critical patent/CN102142377A/en
Application granted granted Critical
Publication of CN102142377B publication Critical patent/CN102142377B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

The invention relates to a production method of a silicon groove of a power MOS (Metal Oxide Semiconductor) device. The production method is characterized by comprising the following steps of: (1) etching an LPSiN masking layer; and (2) etching the silicon groove. The method is simple to operate, and is easy to control; and the shape and appearance of the groove can be controlled by only needing to control the etching time of each step in the etching process of the silicon groove.

Description

A kind of power MOS (Metal Oxide Semiconductor) device silicon trench manufacture method
Technical field
The present invention relates to a kind of power MOS (Metal Oxide Semiconductor) device silicon trench manufacture method.
Background technology
Along with the power MOS (Metal Oxide Semiconductor) device more applications to electronic equipments such as communication and portable personal computer, also improve constantly for the requirement of the power loss of power MOS (Metal Oxide Semiconductor) device.On designs, need constantly dwindle the size of each unit component, improve the device integrated level.Yet also more and more higher to the requirement of processes along with constantly dwindling of the size of primitive unit cell, particularly in the semiconductor structure of different size deep trench, the control of doing ditch depth after carving and pattern becomes the key factor of decision properties of product.
The deep groove structure high-power MOS tube has become the trend of high-power MOS tube development.Present most high-performance high-power MOS tube all is to adopt this kind structure.
Therefore how manufacturer utilizes existing resource own to realize that etching groove has become the most important thing.。
Summary of the invention
The object of the present invention is to provide a kind of power MOS (Metal Oxide Semiconductor) device silicon trench manufacture method, this method is simple to operate, is easy to control, and only needing the etch period of each step in the control silicon trench etching process is the pattern of may command groove.
Technical program of the present invention lies in: a kind of power MOS (Metal Oxide Semiconductor) device silicon trench manufacture method is characterized in that: carry out according to the following steps:
1) carries out the etching of LPSiN masking layer;
2) carry out the etching of silicon trench.
The etching of described LPSiN masking layer is carried out according to the following steps: a) residual LPSiN surface glue counterdie behind the removal photoetching development, etch amount is 100
Figure 2011100327857100002DEST_PATH_IMAGE001
~ 500
Figure 42141DEST_PATH_IMAGE001
B) the stable step, the adjusting process parameter, steady pressure is so that main etching can repid discharge and stable when beginning; C) main etching carries out etching to the LPSiN layer, and etching speed is 1000
Figure 896965DEST_PATH_IMAGE001
/ min ~ 3000
Figure 676702DEST_PATH_IMAGE001
/ min, etching homogeneity≤2.0, figure section gradient α 〉=86 °, etch period is controlled by the end point determination method; D) over etching, etch period are 10% ~ 40% of step c); E) thin oxide layer etching is 20 seconds ~ 60 seconds according to the thickness etch period of thin oxide layer.
Technological parameter in the described step a) process is O 2Flow 1SCCM ~ 10SCCM, He ~ O 2Flow 5SCCM ~ 20SCCM, etch chamber pressure 20mtorr ~ 50mtorr, radio-frequency power 100W ~ 200W.
Technological parameter in the described step b) process is SF 6Flow 40SCCM ~ 80SCCM, etch chamber pressure 80mtorr ~ 120mtorr, magnetic field intensity 20GAUSS ~ 60GAUSS.
Technological parameter in the described step c) process is SF 6Flow 40SCCM ~ 80SCCM, etch chamber pressure 80mtorr ~ 120mtorr, magnetic field intensity 20GAUSS ~ 60GAUSS, radio-frequency power 100W ~ 300W, described end point determination method is a spectra methods.
Technological parameter in the described step d) process is SF 6Flow 40SCCM ~ 80SCCM, HBr flow 0 ~ 20SCCM, etch chamber pressure 80mtorr ~ 120mtorr, magnetic field intensity 20GAUSS ~ 60GAUSS, radio-frequency power 100W ~ 300W.
Technological parameter in the described step e) process is CF 4Flow 15SCCM ~ 50SCCM, etch chamber pressure 50mtorr ~ 150mtorr, radio-frequency power 100W ~ 500W.
The etching of described silicon trench is carried out according to the following steps: A) removing surface, and the natural oxidizing layer of removal silicon face, process conditions are CF 4Flow 15SCCM ~ 50SCCM, etch chamber pressure 50mtorr ~ 150mtorr; Radio-frequency power 100W ~ 500W, etch period are 5 seconds ~ 20 seconds, and etch amount is 50
Figure 71911DEST_PATH_IMAGE001
~ 200
Figure 886283DEST_PATH_IMAGE001
B) first step main etching, process conditions are Cl 2Flow 30SCCM ~ 70SCCM, HBr flow 20SCCM ~ 40SCCM, etch chamber pressure 50mtorr ~ 150mtorr, magnetic field intensity 10GAUSS ~ 40GAUSS, radio-frequency power 100W ~ 400W, etching depth are X; C) the second step main etching, process conditions are Cl 2Flow 30SCCM ~ 70SCCM, HBr flow 20SCCM ~ 60SCCM, etch chamber pressure 50mtorr ~ 150mtorr, magnetic field intensity 20GAUSS ~ 60GAUSS, radio-frequency power 100W ~ 400W, etching depth are Y.
Silicon trench etching depth Z=X+Y, X=3/5Z wherein, Y=2/5Z.
Described silicon trench section inclination angle beta is at 86 ° ~ 90 °.
Description of drawings
Fig. 1 is the pattern after residual surperficial glue-line is removed in the LPSiN masking layer etching process.
Fig. 2 is the pattern before the main etching in the LPSiN masking layer etching process.
Fig. 3 is the pattern behind the main etching in the LPSiN masking layer etching process.
Fig. 4 is the pattern after the thin oxide layer etching in the LPSiN masking layer etching process.
Fig. 5 is the pattern after LPSiN masking layer etching is finished.
Fig. 6 is the pattern before adjusting behind the two step main etchings in the silicon trench etching process.
Fig. 7 be in the silicon trench etching process two the step main etchings after adjusted pattern.
Fig. 8 is the pattern before the little groove in bottom is adjusted in the silicon trench etching process.
Fig. 9 is the adjusted pattern of the little groove in bottom in the silicon trench etching process.
Shown in the number in the figure: 1, Si layer 2, SiO 2Layer 3, LPSiN 4, surperficial glue-line.
Embodiment
A kind of power MOS (Metal Oxide Semiconductor) device silicon trench manufacture method is characterized in that: carry out according to the following steps: the etching of 1) carrying out the LPSiN masking layer; 2) carry out the etching of silicon trench.
Because photoresist resistance to corrosion deficiency in silicon is deep plough groove etched, and very easily forming polymer in the plasma etching process is attached on silicon face and reduces etch rate, this polymer can be attached on trenched side-wall in a large number influences the groove pattern, is difficult to form desirable silicon trench.For addressing the above problem, the present invention selects for use certain thickness LPSiN layer to replace photoresist to do the masking layer of follow-up silicon trench etching, and masking layer thickness determines by gash depth, the general available following formula D that converts 1=1/8D 2, D 1Be LPSiN thickness, D 2Convenient follow-up groove morphology control LPSiN layer thickness is gash depth, for should be not less than 1000
Figure 895697DEST_PATH_IMAGE001
The etching of described LPSiN masking layer is carried out according to the following steps: a) residual LPSiN surface glue counterdie behind the removal photoetching development, etch amount is 100
Figure 162730DEST_PATH_IMAGE001
~ 500
Figure 361630DEST_PATH_IMAGE001
B) the stable step, the adjusting process parameter, steady pressure is so that main etching can repid discharge and stable when beginning; C) main etching carries out etching to the LPSiN layer, and etching speed is 1000
Figure 30509DEST_PATH_IMAGE001
/ min ~ 3000
Figure 23872DEST_PATH_IMAGE001
/ min, etching homogeneity≤2.0, figure section gradient α 〉=86 °, etch period is controlled by the end point determination method; D) over etching, etch period are 10% ~ 40% of step c); E) thin oxide layer etching is 20 seconds ~ 60 seconds according to the thickness etch period of thin oxide layer.
Described step a) mainly remains in LPSiN inner surface glue counterdie after removing photoetching development, so that control the pattern of masking layer better, guarantee the pattern of photoresist, and the technological parameter in the process is O 2Flow 1SCCM ~ 10SCCM, He ~ O 2Flow 5SCCM ~ 20SCCM, etch chamber pressure 20mtorr ~ 50mtorr, radio-frequency power 100W ~ 200W Figure 1 shows that the pattern after surperficial glue-line is removed.
Its process conditions of described step b) are consistent with main etching, and this goes on foot no radio-frequency power, only plays the pressure stability effect, so that main etching can repid discharge and stable when beginning, the technological parameter in the process is SF 6Flow 40SCCM ~ 80SCCM, etch chamber pressure 80mtorr ~ 120mtorr, magnetic field intensity 20GAUSS ~ 60GAUSS.
Described step c) mainly solves the etching of LPSiN and the control of pattern, acting as of magnetic field is thereby that the basis makes the plasma running route as far as possible perpendicular to the pattern of silicon chip surface control figure with the electromagnetic principle, etch rate and etching homogeneity can be realized by in the adjusting process condition gas ratio, etch chamber pressure and radio-frequency power, figure section gradient can realize by adjusting etch chamber pressure and magnetic field intensity, Fig. 2 and Fig. 3 are the variation of pattern before and after adjusting, and the technological parameter in the process is SF 6Flow 40SCCM ~ 80SCCM, etch chamber pressure 80mtorr ~ 120mtorr, magnetic field intensity 20GAUSS ~ 60GAUSS, radio-frequency power 100W ~ 300W, described end point determination method is a spectra methods.
Technological parameter in the described step d) process is SF 6Flow 40SCCM ~ 80SCCM, HBr flow 0 ~ 20SCCM, etch chamber pressure 80mtorr ~ 120mtorr, magnetic field intensity 20GAUSS ~ 60GAUSS, radio-frequency power 100W ~ 300W.
Technological parameter in the described step e) process is CF 4Flow 15SCCM ~ 50SCCM, etch chamber pressure 50mtorr ~ 150mtorr, radio-frequency power 100W ~ 500W, the profile after the etching form the LPSiN masking layer of band figure, as shown in Figure 5 as shown in Figure 4 after final surperficial glue-line is removed.
In the etching process to dark silicon ditch, along with the increasing of gash depth, it is big that the etching difficulty also becomes thereupon.It is big that gash depth becomes, plasma is difficult to enter channel bottom, the polymer aggregational that forms in the etching process plays barrier effect at trenched side-wall to etching, intensification along with groove, this the more obvious of change that stop, therefore deep plough groove etched process to gash depth and morphology control become very difficult, so the present invention realizes control to gash depth and pattern by two step etchings.
The etching of described silicon trench is carried out according to the following steps:
A) removing surface, this step purpose is to remove the silicon face natural oxidizing layer, owing to carve the silicon process to SiO 2Etching mainly by promptly realizing SiO that physical etchings realizes by plasma bombardment 2Etching, so etch rate is extremely slow, the existence of natural oxidizing layer is very big to subsequent etching influence, therefore needs this step to remove, process conditions are CF 4Flow 15SCCM ~ 50SCCM, etch chamber pressure 50mtorr ~ 150mtorr; Radio-frequency power 100W ~ 500W, etch period are 5 seconds ~ 20 seconds, and etch amount is 50
Figure 715885DEST_PATH_IMAGE001
~ 200
Figure 452897DEST_PATH_IMAGE001
B) first step main etching, process conditions are Cl 2Flow 30SCCM ~ 70SCCM, HBr flow 20SCCM ~ 40SCCM, etch chamber pressure 50mtorr ~ 150mtorr, magnetic field intensity 10GAUSS ~ 40GAUSS, radio-frequency power 100W ~ 400W, etching depth are X;
C) the second step main etching, process conditions are Cl 2Flow 30SCCM ~ 70SCCM, HBr flow 20SCCM ~ 60SCCM, etch chamber pressure 50mtorr ~ 150mtorr, magnetic field intensity 20GAUSS ~ 60GAUSS, radio-frequency power 100W ~ 400W, etching depth are Y.
Set the groove that the different time can obtain different depth, suppose that the silicon trench etching depth is Z, first step etch amount is X, and the second step etch amount is Y, silicon trench etching depth Z=X+Y, and X=3/5Z wherein, Y=2/5Z is by adjusting Cl 2The pattern that can control groove with HBr ratio, magnetic field intensity is ditch grooved profile angle of inclination, and the silicon trench section inclination angle beta of etching of the present invention is at 86 ° ~ 90 °, and the pattern before and after adjusting is gone into Figure 6 and Figure 7.
Cl of the present invention 2Gas is for carving the main component of silicon, HBr mainly provides Br ﹢ ion, under the effect in magnetic field, mainly show as physical characteristic, can remove the polymer of etching process attached to silicon face and sidewall, its content plays main influence to the groove pattern, under the situation of other parameter constant, the set amount that the present invention second goes on foot HBR in the main etching is 1.5 times ~ 3 times of first step main etching.
In etching process at channel bottom little groove phenomenon appears very easily, after energising can point discharge phenomenon just appear at little groove, this is the one of the main reasons of component failure unusually, the present invention can improve and eliminates little groove phenomenon by adjusting etch chamber pressure, the etch chamber pressure setting of noting the first step main etching and the second step main etching should be consistent, and adjusts front and back as Fig. 8 and Fig. 9.
After the etching on the LPSIN surface and trenched side-wall can residual polyalcohol, this polymer can remove with a certain proportion of hydrofluoric acid
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.

Claims (10)

1. power MOS (Metal Oxide Semiconductor) device silicon trench manufacture method is characterized in that: carry out according to the following steps:
1) carries out the etching of LPSiN masking layer;
2) carry out the etching of silicon trench.
2. a kind of power MOS (Metal Oxide Semiconductor) device silicon trench manufacture method according to claim 1, it is characterized in that: the etching of described LPSiN masking layer is carried out according to the following steps:
A) residual LPSiN surface glue counterdie behind the removal photoetching development, etch amount is 100
Figure 2011100327857100001DEST_PATH_IMAGE002
~ 500
B) the stable step, the adjusting process parameter, steady pressure is so that main etching can repid discharge and stable when beginning;
C) main etching carries out etching to the LPSiN layer, and etching speed is 1000
Figure 889220DEST_PATH_IMAGE002
/ min ~ 3000
Figure 130845DEST_PATH_IMAGE002
/ min, etching homogeneity≤2.0, figure section gradient α 〉=86 °, etch period is controlled by the end point determination method;
D) over etching, etch period are 10% ~ 40% of step c);
E) thin oxide layer etching is 20 seconds ~ 60 seconds according to the thickness etch period of thin oxide layer.
3. a kind of power MOS (Metal Oxide Semiconductor) device silicon trench manufacture method according to claim 2, it is characterized in that: the technological parameter in the described step a) process is O 2Flow 1SCCM ~ 10SCCM, He ~ O 2Flow 5SCCM ~ 20SCCM, etch chamber pressure 20mtorr ~ 50mtorr, radio-frequency power 100W ~ 200W.
4. a kind of power MOS (Metal Oxide Semiconductor) device silicon trench manufacture method according to claim 2, it is characterized in that: the technological parameter in the described step b) process is SF 6Flow 40SCCM ~ 80SCCM, etch chamber pressure 80mtorr ~ 120mtorr, magnetic field intensity 20GAUSS ~ 60GAUSS.
5. a kind of power MOS (Metal Oxide Semiconductor) device silicon trench manufacture method according to claim 2, it is characterized in that: the technological parameter in the described step c) process is SF 6Flow 40SCCM ~ 80SCCM, etch chamber pressure 80mtorr ~ 120mtorr, magnetic field intensity 20GAUSS ~ 60GAUSS, radio-frequency power 100W ~ 300W, described end point determination method is a spectra methods.
6. a kind of power MOS (Metal Oxide Semiconductor) device silicon trench manufacture method according to claim 2, it is characterized in that: the technological parameter in the described step d) process is SF 6Flow 40SCCM ~ 80SCCM, HBr flow 0 ~ 20SCCM, etch chamber pressure 80mtorr ~ 120mtorr, magnetic field intensity 20GAUSS ~ 60GAUSS, radio-frequency power 100W ~ 300W.
7. a kind of power MOS (Metal Oxide Semiconductor) device silicon trench manufacture method according to claim 2, it is characterized in that: the technological parameter in the described step e) process is CF 4Flow 15SCCM ~ 50SCCM, etch chamber pressure 50mtorr ~ 150mtorr, radio-frequency power 100W ~ 500W.
8. a kind of power MOS (Metal Oxide Semiconductor) device silicon trench manufacture method according to claim 1, it is characterized in that: the etching of described silicon trench is carried out according to the following steps:
A) removing surface, the natural oxidizing layer of removal silicon face, process conditions are CF 4Flow 15SCCM ~ 50SCCM, etch chamber pressure 50mtorr ~ 150mtorr; Radio-frequency power 100W ~ 500W, etch period are 5 seconds ~ 20 seconds, and etch amount is 50
Figure 343652DEST_PATH_IMAGE002
~ 200
B) first step main etching, process conditions are Cl 2Flow 30SCCM ~ 70SCCM, HBr flow 20SCCM ~ 40SCCM, etch chamber pressure 50mtorr ~ 150mtorr, magnetic field intensity 10GAUSS ~ 40GAUSS, radio-frequency power 100W ~ 400W, etching depth are X;
C) the second step main etching, process conditions are Cl 2Flow 30SCCM ~ 70SCCM, HBr flow 20SCCM ~ 60SCCM, etch chamber pressure 50mtorr ~ 150mtorr, magnetic field intensity 20GAUSS ~ 60GAUSS, radio-frequency power 100W ~ 400W, etching depth are Y.
9. a kind of power MOS (Metal Oxide Semiconductor) device silicon trench manufacture method according to claim 8 is characterized in that: silicon trench etching depth Z=X+Y, X=3/5Z wherein, Y=2/5Z.
10. a kind of power MOS (Metal Oxide Semiconductor) device silicon trench manufacture method according to claim 8 is characterized in that: described silicon trench section inclination angle beta is at 86 ° ~ 90 °.
CN 201110032785 2011-01-30 2011-01-30 Production method of silicon groove of power MOS (Metal Oxide Semiconductor) device Active CN102142377B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201110032785 CN102142377B (en) 2011-01-30 2011-01-30 Production method of silicon groove of power MOS (Metal Oxide Semiconductor) device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201110032785 CN102142377B (en) 2011-01-30 2011-01-30 Production method of silicon groove of power MOS (Metal Oxide Semiconductor) device

Publications (2)

Publication Number Publication Date
CN102142377A true CN102142377A (en) 2011-08-03
CN102142377B CN102142377B (en) 2013-04-17

Family

ID=44409798

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201110032785 Active CN102142377B (en) 2011-01-30 2011-01-30 Production method of silicon groove of power MOS (Metal Oxide Semiconductor) device

Country Status (1)

Country Link
CN (1) CN102142377B (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105720002A (en) * 2014-12-03 2016-06-29 北京北方微电子基地设备工艺研究中心有限责任公司 Oblique hole etching method
CN107887270A (en) * 2017-11-14 2018-04-06 扬州扬杰电子科技股份有限公司 The lithographic method of groove on a kind of chip
CN109390227A (en) * 2017-08-08 2019-02-26 天津环鑫科技发展有限公司 A kind of lithographic method of small line width vertical-type groove
CN111261509A (en) * 2018-11-30 2020-06-09 宁波比亚迪半导体有限公司 Method for etching a trench in a silicon substrate and use thereof
CN113571414A (en) * 2021-09-24 2021-10-29 广州粤芯半导体技术有限公司 Method for manufacturing semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5409563A (en) * 1993-02-26 1995-04-25 Micron Technology, Inc. Method for etching high aspect ratio features
JP3000337B2 (en) * 1994-06-16 2000-01-17 エルジイ・セミコン・カンパニイ・リミテッド Method for forming separation film of semiconductor device
CN1610967A (en) * 2001-05-24 2005-04-27 国际商业机器公司 Structure and method to preserve STI during etching
US7960286B2 (en) * 2009-06-17 2011-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Narrow channel width effect modification in a shallow trench isolation device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5409563A (en) * 1993-02-26 1995-04-25 Micron Technology, Inc. Method for etching high aspect ratio features
JP3000337B2 (en) * 1994-06-16 2000-01-17 エルジイ・セミコン・カンパニイ・リミテッド Method for forming separation film of semiconductor device
CN1610967A (en) * 2001-05-24 2005-04-27 国际商业机器公司 Structure and method to preserve STI during etching
US7960286B2 (en) * 2009-06-17 2011-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Narrow channel width effect modification in a shallow trench isolation device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105720002A (en) * 2014-12-03 2016-06-29 北京北方微电子基地设备工艺研究中心有限责任公司 Oblique hole etching method
CN105720002B (en) * 2014-12-03 2019-04-23 北京北方华创微电子装备有限公司 Inclined hole lithographic method
CN109390227A (en) * 2017-08-08 2019-02-26 天津环鑫科技发展有限公司 A kind of lithographic method of small line width vertical-type groove
CN109390227B (en) * 2017-08-08 2020-09-29 天津环鑫科技发展有限公司 Etching method of small-linewidth vertical groove
CN107887270A (en) * 2017-11-14 2018-04-06 扬州扬杰电子科技股份有限公司 The lithographic method of groove on a kind of chip
CN111261509A (en) * 2018-11-30 2020-06-09 宁波比亚迪半导体有限公司 Method for etching a trench in a silicon substrate and use thereof
CN113571414A (en) * 2021-09-24 2021-10-29 广州粤芯半导体技术有限公司 Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
CN102142377B (en) 2013-04-17

Similar Documents

Publication Publication Date Title
CN102142377B (en) Production method of silicon groove of power MOS (Metal Oxide Semiconductor) device
JP2013080909A (en) Etch process for 3d flash structures
CN100595895C (en) Silicon groove forming method and device
CN107112232A (en) Plasma-etching method
CN103950887B (en) A kind of dark silicon etching method
CN103915330A (en) Substrate etching method
CN103035501B (en) A kind of preparation method avoiding the polysilicon trench gate in cavity
WO2009042453A3 (en) Profile control in dielectric etch
TW200520089A (en) Etch with ramping
CN103515176A (en) Seasoning method and etching method
CN103208421A (en) Method for improving etching selection ratio of silicon nitride layer to oxide layer
CN101599429B (en) Method for forming side wall
TW201304001A (en) Method for providing high etch rate
TWI571928B (en) Method of hard mask cd control by ar sputtering
CN100397586C (en) Polycrystalline silicon pulse etching process for improving anisotropy
CN108573867A (en) Silicon deep hole lithographic method
CN103413779B (en) Silicon etching method for forming through hole
CN100371278C (en) Multicrystal silicon etching process capable of avoiding forming burr on channel bottom
CN105097494B (en) Lithographic method
CN104599943A (en) Tantalum nitride reaction ion etching method
CN105720002B (en) Inclined hole lithographic method
CN101562134A (en) Method for preparing tunnel window
CN103077920A (en) Dry etching method of improving horizontal opening of through silicon hole
CN100377315C (en) Silicon gate etching method
CN105720003B (en) Deep silicon hole lithographic method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant