CN103811408A - Depth through silicon via etching method - Google Patents
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- CN103811408A CN103811408A CN201210445649.5A CN201210445649A CN103811408A CN 103811408 A CN103811408 A CN 103811408A CN 201210445649 A CN201210445649 A CN 201210445649A CN 103811408 A CN103811408 A CN 103811408A
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- 238000005530 etching Methods 0.000 title claims abstract description 113
- 238000000034 method Methods 0.000 title claims abstract description 50
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 33
- 239000010703 silicon Substances 0.000 title claims abstract description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 239000007789 gas Substances 0.000 claims description 24
- 230000008021 deposition Effects 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 abstract 1
- 229920001296 polysiloxane Polymers 0.000 abstract 1
- 239000012495 reaction gas Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 22
- 238000000151 deposition Methods 0.000 description 9
- 239000004020 conductor Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 239000002210 silicon-based material Substances 0.000 description 4
- 238000012937 correction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000013047 polymeric layer Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 208000002925 dental caries Diseases 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 230000010415 tropism Effects 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
- B81C1/00619—Forming high aspect ratio structures having deep steep walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
- B81C2201/0111—Bulk micromachining
- B81C2201/0112—Bosch process
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Plasma & Fusion (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention provides a depth through silicon via etching method; a processed silicon sheet is arranged in a plasma process chamber; the surface of the silicone sheet comprises a patterning mask layer; a first reaction gas is inducted to etch the silicon sheet so as to form an opening, having undercut morphology, to a first depth; a main etching phase of alternatively carrying out etching and side wall protection is conducted; the main etching phase is finished to form the side wall having basic vertical sidewall morphology.
Description
Technical field
The present invention relates to plasma treatment field, relate in particular to a kind of deep hole silicon etching method to obtain better sidewall pattern.
Background technology
In technical field of manufacturing semiconductors, in MEMS(Micro-Electro-Mechanical Systems, MEMS (micro electro mechanical system)) and the field such as 3D encapsulation technology, conventionally need to carry out deep via etching to materials such as silicon.For example, in crystalline silicon lithographic technique, the degree of depth of dark silicon through hole (Through-Silicon-Via, TSV) reaches hundreds of micron, its depth-to-width ratio even much larger than 10, conventionally adopts deep reaction ion etching method to carry out etching body silicon and forms.Described silicon materials are mainly monocrystalline silicon.Fill conductor material as copper completing after etching in hole that also oriented etching forms or groove, fill method can be to utilize chemical vapor deposition (CVD) or physics vapor phase deposition (PVD) process.Because the copper product of above-mentioned deposition deposits from the top down, so TSV hole opening shape the best that etching forms needs trapezoid-shaped openings, or there is the opening of vertical sidewall.
Existing typical lithographic technique is to utilize the etching-deposition step hocketing to carry out quick etching to silicon, and etching method is again Bosch etching method at the moment.In the time adopting bosch etching method to carry out etching, the hole sidewall of formation is slight arc (bowing).Profile as shown in Figure 1a, the hole that etching forms is all less than interlude diameter in top and bottom.Wherein topmost the enlarged drawing of opening part as shown in Figure 1 b etching material layer structures comprise: mask layer 10(is as photoresist PR), mask layer 10 belows are crystalline silicon material layers 20 to be etched, etching forms hole 200.Such hatch frame is unfavorable for next step electric conducting material deposition, and the less opening sidewalls in top can stop the further deposition of electric conducting material in the hole of below, carries out after electric conducting material filling step possibly at hole, still has cavity in hole.The existence of these cavitys not only can worsen conductive characteristic even can cause need the circuit of conducting disconnect.Cannot eliminate this disadvantageous sidewall pattern by the adjusting of adjustable parameter in traditional B osch etching method.This just causes the hole that adopts traditional B osch etching method to form in following process, to bring problem, finally causes the discarded of whole product, causes very large waste and loss.So industry needs a kind of simple and effective lithographic method to improve deep hole silicon etching method.
Summary of the invention
The object of this invention is to provide the hole pattern that a kind of deep hole silicon etching method forms etching is more suitable for filling in follow-up electric conducting material.Described deep hole silicon etching method is for etch silicon substrate, on described silicon chip, comprise a patterned mask layer, described lithographic method comprises: the first etch stages, form the opening of first degree of depth take described patterned mask layer as mask etching silicon chip, the spacing of described opening both sides sidewall reduces downwards gradually from top, finish the laggard etch stages of becoming owner of in the first etch stages, the described main etching stage comprises the etching and the deposition step that hocket, in etch step, pass into etching gas silicon chip is carried out to etching, in deposition step, passing into fluorocarbon gases protects the opening sidewalls of etching formation, described main etching stage etch silicon substrate is from described first degree of depth to second degree of depth, make the sidewall spacing of described the first depth increase simultaneously.
Wherein said patterned mask layer has the first critical size, there is the second critical size completing described mask layer after the main etching stage, described the second critical size is greater than described the first critical size, and the first critical size is selected from 4-6um, and the second critical size is selected from 7-8um.
The etching gas of the first etch stages comprises SF6, C4F8, O2.Spacing between the open upper end sidewall of described first degree of depth is greater than described the first critical size.
Second degree of depth of wherein said main etching stage etching is greater than 30um.The etching gas that etch step in the main etching stage passes into is selected from one of SF6 and NF3.
The sidewall spacing of described the first degree of depth opening is less than the spacing between the open upper end sidewall of 1.1 times, and wherein first degree of depth is greater than 1um and is less than 6um.
Accompanying drawing explanation
Fig. 1 a is the overall generalized section that in prior art, etching forms dark silicon through hole;
Fig. 1 b is the local enlarged diagram that in prior art, etching forms dark silicon through hole upper end;
Fig. 2 is the local enlarged diagram in dark silicon through hole upper end that utilizes lithographic method provided by the invention to form in etching pilot process;
Fig. 3 is the local enlarged diagram that utilizes lithographic method provided by the invention dark silicon through hole upper end in the time that etching completes;
Fig. 4 is the profile of part, dark silicon through hole upper end while utilizing lithographic method provided by the invention to complete etching.
Embodiment
Below in conjunction with Fig. 2～Fig. 4, by preferred specific embodiment, describe the present invention in detail.
As shown in Figure 2, in etching process, first carry out the pre-correction etching of sidewall pattern with respect to prior art the present invention, form a undercutting pattern (undercut) carrying out first etching before follow-up deep hole silicon etching, this undercutting, with suitable dimension, forms the side direction etching with certain depth to hole both sides at mask layer lower surface.Mask layer 10 has distance B 1 in the side-walls of opening part, and namely mask layer CD is now of a size of D1, and the opening both sides sidewall distance that mask layer is namely close in the upper end of the hole that etching forms is D20, and wherein D20 is greater than D1.The numerical value that concrete D20 is greater than D1 can adjust according to integral processing, and the difference of D20-D1 is at least greater than 1um and offsets to guarantee compensation the pattern skew forming in subsequent etching.Such as the difference of D20-D1 can be to be greater than 1um to be less than 6um, that optimum can be 2-4um.The selection of this degree of depth offsets and is advisable with the degree of depth that can be outstanding with the bowing sidewall pattern phase opening that follow-up main etch stages forms.After the etching that completes undercutting pattern, on silicon chip, form an opening with certain depth, this degree of depth can be adjusted as required etching technics and select, generally want enough large as being greater than 2um, the mask layer extended distance of the opening of formation above the both sides sidewall spacing at upper end in contact mask layer place is greater than.The spacing of opening both sides sidewall reduces from top to bottom gradually, and near first depth H 1 place to bottom has first space D 21.In the time that etching forms undercutting pattern, can adopt a variety of etching technics, be mainly to use SF6 also can adopt the etching gas such as NF3 as etching gas, and other fluorocarbons is if C4F8 and O2 are as auxiliary etch gas.As adopt above-mentioned gas under 50 millitorr air pressure, and pass into the SF6 gas of 1000sccm, the C4F8 gas of 150sccm and the O2 gas of 50sccm, above-mentioned reacting gas is lighted plasma after passing into reaction chamber, continues just can form for 10 seconds the undercutting pattern shown in Fig. 2.Except above-mentioned etching technics, other a lot of etching technics can both be used for forming described undercutting pattern as: (1) air pressure is set as 100mT, pass into the SF6 gas of 500sccm flow and the O2 of 920sccm pass into simultaneously 200sccm C4F8 gas continue 15 seconds; (2) air pressure is 150mt, passes into the SF6 gas of 1500sccm flow, and the C4F8 gas of 800sccm and the O2 of 600sccm continue 15 seconds; (3) maintain 150mT air pressure, the O2 of SF6,800sccm and the C4F8 of 900sccm that pass into 500sccm maintain 15s.
After the undercutting pattern shown in formation Fig. 2, just enter main etching step; adopt traditional dark silicon via etch method etching as downward in Bosch etching method; the etching gas that utilizes alternately waits tropism's etching certain depth downwards; then protecting with the hole sidewall that fluorocarbon forms whole etching; enter subsequently the circulation of next etching-sidewall protection, until etching reaches the needed degree of depth.Wherein etching and deposition step can complete once alternately to reduce the degree of roughness of sidewall in 2 seconds.In fact Fig. 2 Hole 200 sidewalls comprise a large amount of concavo-convex small stripeds that replace that alternately etching forms, all not shown due to the inventive method is not impacted.As shown in Figure 2 in the process take photoresist silicon below mask etching the figure extended distance on photoresist from initial D1, namely critical size D1(critical dimension) start downward etching, because technique needs, need to be increased to gradually the D2 of last etching completion status as shown in Figure 3 in downward etching process split shed distance.While wherein beginning, D1 can be 5um, and while completing to etching, D2 can be 7um, and this just requires in etching process can not be too thick at the polymer deposition layer of the formation on mask layer 10 surfaces, so the gas content of C4F8 can not be very high in etching gas.On mask layer 10 surfaces, polymeric layer also can cause in not thick the polymeric layer of the hole sidewall protection that etching forms also can be very not thick, so the phenomenon that can exist partial sidewall to be etched.In etching, from hole 200 upper openings extension process downwards, the distance of the mask layer opening of top is also being expanded to D2 gradually from D1.So this can cause the hole diameter that the little corresponding etching of mask open forms in the time of the silicon material layer of etching top less, in the time carrying out further etching subsequently, mask open becomes large, and the corresponding hole value footpath forming becomes large.The final little and sidewall pattern that the large this hope of lower openings diameter is seen of upper opening diameter that formed in etching process.After application the inventive method, because oppose side wall pattern has carried out pre-correction, formed the opening of the undercutting pattern shown in Fig. 2, so be to start downward etching at the first depth H 1 place shown in Fig. 2 in main etching step, in the time starting etching, the first depth sidewall spacing remains D21.Along with the carrying out of etching until the whole etching of the second depth complete.Because mask layer critical size in long etching process of top is becoming large, so the main etching stage still there will be the phenomenon of arc (bowing) sidewall, the undercutting pattern forming in described curved wall pattern and first step etching compensates mutually, until can make the sidewall spacing of the first depth reach D22 while completing etching, D22 is greater than aforementioned D21, and the size of the sidewall spacing of D22 and above and below approaches.So opening sidewalls entirety pattern is vertically downward substantially, can not cause the impact that do not work to subsequent deposition step.Because above-mentioned curved wall pattern forms gradually, thus only just can be obvious when etching depth is enough large, and etching depth of the present invention can reach and be greater than 100um, even larger.Certainly when the degree of depth is greater than 30um, just can observe above-mentioned curved wall, also can apply the present invention by the adjusting of etching technics parameter and put the incomplete problem of filling of stopping the follow-up filling stage.
Structural representation while just completing etching with the present invention as shown in Figure 3.Fig. 4 is the material layer profile that practical application the inventive method etching obtains.From Fig. 3 or 4 known: carrying out carrying out traditional etching the first step forms undercutting pattern, both can eliminate to the effect stack of silicon material layer 200 part that prior art etching hole 200 openends extend internally again in invention, so just can prevent from forming in packing material the result of cavity in follow-up electric conducting material filling process.The step forming due to described undercut etch adopts traditional deep hole silicon etching gas, and the time of carrying out very shortly only have about 10 seconds, and relatively existing system hardware do not have extra demand, so adopt the present invention to utilize simple method to realize the correction of oppose side wall pattern under the front topic that does not substantially increase extra cost and time.
The present invention can be applied to capacitive coupling (CCP) type plasma treatment appts or inductance coupling high type (ICP) plasma treatment appts
Although content of the present invention has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.Read after foregoing those skilled in the art, for multiple modification of the present invention and substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (10)
1. deep hole silicon etching method, for an etch silicon substrate, comprises a patterned mask layer on described silicon chip, and described lithographic method comprises
The first etch stages, forms the opening of first degree of depth (H1) take described patterned mask layer as mask etching silicon chip, the spacing of described opening both sides sidewall reduces downwards gradually from top, and has the first side wall spacing (D21) at the first depth,
Finish the laggard etch stages of becoming owner of in the first etch stages; the described main etching stage comprises the etching and the deposition step that hocket; in etch step, pass into etching gas silicon chip is carried out to etching; in deposition step, passing into fluorocarbon gases protects the opening sidewalls of etching formation; the described main etching stage; described opening, from described the first deep etching to second degree of depth, makes the first side wall spacing of described the first depth increase to the second spacing (D22) simultaneously.
2. lithographic method as claimed in claim 1, it is characterized in that, described patterned mask layer has the first critical size in the first etch stages, has the second critical size completing described mask layer after the main etching stage, and described the second critical size is greater than described the first critical size.
3. lithographic method as claimed in claim 1, is characterized in that, the etching gas of described the first etch stages comprises SF6, C4F8, O2.
4. lithographic method as claimed in claim 1, is characterized in that, second degree of depth of described main etching stage etching is greater than 30um.
5. lithographic method as claimed in claim 1, is characterized in that, the etching gas that the etch step in the described main etching stage passes into is selected from one of SF6 and NF3.
6. lithographic method as claimed in claim 2, is characterized in that, the spacing (D20) between the first degree of depth open upper end sidewall that described the first etch stages forms is greater than described the first critical size (D1) more than 1um.
7. lithographic method as claimed in claim 6, is characterized in that, the spacing between the first degree of depth open upper end sidewall that described the first etch stages forms is greater than described the first critical size, and difference is greater than 1um and is less than 6um.
8. lithographic method as claimed in claim 2, is characterized in that described the first critical size is selected from 4-6um, and the second critical size is selected from 7-8um.
9. lithographic method as claimed in claim 1, is characterized in that, the hypomere sidewall spacing of described the first degree of depth opening is less than the spacing between the open upper end sidewall of 1.1 times.
10. lithographic method as claimed in claim 1, is characterized in that, described first degree of depth is greater than 2um.
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| CN201210445649.5A CN103811408B (en) | 2012-11-08 | 2012-11-08 | A kind of deep silicon etching method for forming through hole |
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| CN201210445649.5A CN103811408B (en) | 2012-11-08 | 2012-11-08 | A kind of deep silicon etching method for forming through hole |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448697A (en) * | 2014-07-18 | 2016-03-30 | 中微半导体设备(上海)有限公司 | Etching method for high-aspect-ratio structure and MEMS device manufacturing method |
| CN105720003A (en) * | 2014-12-03 | 2016-06-29 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Deep silicon hole etching method |
| CN108648994A (en) * | 2018-05-15 | 2018-10-12 | 长江存储科技有限责任公司 | Forming method, groove structure and the memory of groove structure |
| CN110937567A (en) * | 2018-09-21 | 2020-03-31 | 国家纳米科学中心 | Silicon-based quadrangular frustum pyramid-shaped micro through hole array, and preparation method and application thereof |
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| US4814041A (en) * | 1986-10-08 | 1989-03-21 | International Business Machines Corporation | Method of forming a via-hole having a desired slope in a photoresist masked composite insulating layer |
| US20100203699A1 (en) * | 2009-02-09 | 2010-08-12 | Samsung Electronics Co., Ltd. | Method of forming semiconductor device |
| CN101962773A (en) * | 2009-07-24 | 2011-02-02 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Deep silicon etching method |
| CN102398887A (en) * | 2010-09-14 | 2012-04-04 | 中微半导体设备(上海)有限公司 | Deep hole silicon etching method |
| CN102543836A (en) * | 2010-12-21 | 2012-07-04 | 无锡华润上华半导体有限公司 | Method for etching through hole |
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2012
- 2012-11-08 CN CN201210445649.5A patent/CN103811408B/en active Active
Patent Citations (5)
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| US4814041A (en) * | 1986-10-08 | 1989-03-21 | International Business Machines Corporation | Method of forming a via-hole having a desired slope in a photoresist masked composite insulating layer |
| US20100203699A1 (en) * | 2009-02-09 | 2010-08-12 | Samsung Electronics Co., Ltd. | Method of forming semiconductor device |
| CN101962773A (en) * | 2009-07-24 | 2011-02-02 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Deep silicon etching method |
| CN102398887A (en) * | 2010-09-14 | 2012-04-04 | 中微半导体设备(上海)有限公司 | Deep hole silicon etching method |
| CN102543836A (en) * | 2010-12-21 | 2012-07-04 | 无锡华润上华半导体有限公司 | Method for etching through hole |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448697A (en) * | 2014-07-18 | 2016-03-30 | 中微半导体设备(上海)有限公司 | Etching method for high-aspect-ratio structure and MEMS device manufacturing method |
| CN105720003A (en) * | 2014-12-03 | 2016-06-29 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Deep silicon hole etching method |
| CN105720003B (en) * | 2014-12-03 | 2019-01-18 | 北京北方华创微电子装备有限公司 | Deep silicon hole lithographic method |
| CN108648994A (en) * | 2018-05-15 | 2018-10-12 | 长江存储科技有限责任公司 | Forming method, groove structure and the memory of groove structure |
| CN110937567A (en) * | 2018-09-21 | 2020-03-31 | 国家纳米科学中心 | Silicon-based quadrangular frustum pyramid-shaped micro through hole array, and preparation method and application thereof |
| CN110937567B (en) * | 2018-09-21 | 2022-12-13 | 国家纳米科学中心 | Silicon-based quadrangular frustum pyramid-shaped micro through hole array, and preparation method and application thereof |
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| CN103811408B (en) | 2016-08-17 |
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