CN103730411A - Through-silicon-via (TSV) etching method - Google Patents
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- 229910004014 SiF4 Inorganic materials 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 3
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
- B81C1/00619—Forming high aspect ratio structures having deep steep walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
- B81C2201/0111—Bulk micromachining
- B81C2201/0112—Bosch process
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Abstract
The invention provides a through-silicon-via (TSV) etching method. A silicon wafer to be processed is arranged in a plasma processing chamber, the surface of the silicon wafer includes a graphical mask layer, the steps of etching and deposition are carried out circularly and alternatively until a through via with a target depth is formed, etching gas is led into a reaction chamber in the step of etching to etch a silicon substrate, openings are formed, and fluorocarbon gas is led in the step of deposition to protect the lateral walls of the openings formed in the step of etching. The TSV etching method is characterized in that the step of gas exhaust is included between the step of etching and the step of deposition, and leading-in of the etching gas or deposition gas is stopped in the step of gas exhaust. By means of the TSV etching method, arc lateral walls of the etched through via are prevented from being generated.
Description
Technical field
The present invention relates to plasma treatment field, relate in particular to a kind of deep hole silicon etching method to obtain better sidewall pattern.
Background technology
In technical field of manufacturing semiconductors, in MEMS(Micro-Electro-Mechanical Systems, MEMS (micro electro mechanical system)) and the field such as 3D encapsulation technology, conventionally need to carry out deep via etching to materials such as silicon.For example, in crystalline silicon lithographic technique, the degree of depth of dark silicon through hole (Through-Silicon-Via, TSV) reaches hundreds of micron, its depth-to-width ratio even much larger than 30, conventionally adopts deep reaction ion etching method to come etching body silicon to form.Described silicon materials are mainly monocrystalline silicon.In the hole that also oriented etching forms after completing etching or groove, fill conductor material as copper, fill method can be to utilize chemical vapor deposition (CVD) or physics vapor phase deposition (PVD) process.Because the copper product of above-mentioned deposition deposits from the top down, so TSV hole opening shape the best that etching forms needs trapezoid-shaped openings, or there is the opening of vertical sidewall.
Existing typical lithographic technique is to utilize the etching-deposition step hocketing to carry out quick etching to silicon, and etching method is again Bosch etching method at the moment.Bosch method as described in US Patent No. 5501893 adopts the method that etching and deposition step hocket to realize the etching fast and vertically downward to single crystal silicon material layer.Etching gas is typically as passing in reaction chamber that SF6 and deposition gases C4F8 replace as shown in Figure 1a, and wherein etching gas also can comprise that other gas is as O2, and deposition gases also can comprise gas fluorocarbons.In Fig. 1 a, in etch step A, only have etching gas to pass into reaction chamber, deposition gases stops passing into reaction chamber, or the flow passing into is little of not impacting etching.After etch step completes, etching gas stops passing into or flow is not reduced to and can affects follow-up deposition step, the flow that simultaneously deposition gases starts to pass into setting enters deposition step, so alternately back and forth carry out etch step and deposition step, until reach etching depth.Wherein the time span of etch step and deposition step can change according to the variation of etching depth, and typical time span can be 1-9 second.When adopting prior art Bosch etching method to carry out etching, the hole sidewall of formation is slight arc (bowing).Profile as shown in Figure 1 b, the hole that etching forms is all less than interlude diameter in top and bottom.Wherein topmost the enlarged drawing of opening part as shown in Figure 1 b etching material layer structures comprise: mask layer 110(is as photoresist PR or SiO2), mask layer 10 belows are crystalline silicon material layers 100 to be etched, etching forms hole 200.Such hatch frame is unfavorable for next step electric conducting material deposition, and the less opening sidewalls in top can stop the further deposition of electric conducting material in the hole of below, carries out after electric conducting material filling step possibly at hole, still has cavity in hole.The existence of these cavitys not only can worsen conductive characteristic and even can cause and need the circuit of conducting to disconnect.By the adjusting of adjustable parameter in traditional B osch etching method, cannot eliminate this disadvantageous sidewall pattern.This,, with regard to causing the hole that adopts traditional B osch etching method to form to bring problem in following process, finally causes the discarded of whole product, causes very large waste and loss.So industry needs a kind of simple and effective lithographic method to improve deep hole silicon etching method, to eliminate the curved wall occurring in Bosch etching method.
Summary of the invention
The object of this invention is to provide a kind of deep hole silicon etching method for etch silicon substrate, on described silicon chip, comprise a patterned mask layer, described lithographic method comprises: the etching that cycle alternation carries out and deposition step, until form the through hole with target depth, in etch step, passing into etching gas carries out etching and forms opening silicon chip to reaction chamber, in deposition step, passing into fluorocarbon gases protects the opening sidewalls of etching formation, it is characterized in that also comprising steps of exhausting between described etch step and deposition step, in steps of exhausting, stop passing into etching gas or deposition gases, or the etching/deposition gases passing into is less than corresponding etching/deposition gases flow 1/3 in corresponding etching/deposition step, described steps of exhausting time span is greater than 0.5 second and is less than 4 seconds.Best steps of exhausting time span can be less than 2 seconds.Wherein etching gas comprises SF6, O2, and deposition step comprises gas C4F8.
The target depth of etching through hole of the present invention is greater than 30um, in the present invention of deep hole silicon etching field, can embody the advantage that etched hole sidewall is more vertical.
Wherein the time span of steps of exhausting increases along with the increase of via depth, to enhance productivity, improves sidewall pattern simultaneously.
Wherein steps of exhausting be arranged on via etch reach target depth 1/3 after etch step and deposition step between, at 1/3 of etching through hole opening part target depth, improve etching efficiency during with interior silicon material layer.
Described in when described via etch reaches first degree of depth, steps of exhausting is only positioned at after steps of exhausting before deposition step, described in when via etch reaches second degree of depth, steps of exhausting is only positioned at after deposition step before etch step, wherein second degree of depth is greater than first degree of depth, etching through hole during corresponding different depth can be chosen in and between etch step-deposition step or between deposition step-etch step, add steps of exhausting, that can more optimize improves sidewall pattern, and each treatment step all adds the embodiment of steps of exhausting in changing relatively, saved the time of unnecessary steps of exhausting.
Accompanying drawing explanation
Fig. 1 a is etching gas and deposition gases gas flow distribution in prior art Bosch etching method;
Fig. 1 b is that prior art Bosch etching method forms dark silicon through hole overall schematic;
Fig. 2 a is for utilizing lithographic method gas flow schematic diagram provided by the invention;
Fig. 2 b forms dark silicon through hole overall schematic when utilizing lithographic method provided by the invention to complete;
Embodiment
Below in conjunction with Fig. 1～Fig. 2, by preferred specific embodiment, describe the present invention in detail.
Through inventor, study discovery; the main cause that can produce the through hole of curved wall while adopting traditional Bosch etching method is: because the application scenario etching through hole degree of depth of TSV is very large; generally be greater than 30um and often can be greater than 100um; so proceed to after certain depth in etching; the through hole that the accessory substance of reaction is difficult to form by etching as SiF4 makes progress and spreads, and also just cannot be taken away by the air extractor of below in reaction chamber.Byproduct of reaction cannot discharge can cause new reacting gas SF6 and C4F8 cannot arrive with the quantity of expection arrival conversion zone.Such as 1/3 o'clock over whole via depth desired depth at etching depth, C4F8 is affected by byproduct of reaction first, and portion gas does not arrive via bottoms and just by air extractor, taken away.Because sidewall protection is not enough, can cause the increase through hole bore along with etching depth can become gradually greatly, although the variation of the cycle inner via hole bore of each etching-deposition is very trickle, in macroscopic view, in the middle of through hole, occur as shown in Figure 1 b the structure of expanding gradually.Along with the further increase of etching depth is such as surpassing 1/2 o'clock of overall depth, the downward diffusion of etching gas SF6 is also affected, and this can cause reducing of etch rate in each etch step, and then causes the bore of through hole to diminish gradually.The final dark silicon through hole that forms camber line sidewall as shown in Figure 1 b.So prevention the most effective solution of appearance of curved wall in Bosch etching method is to discharge the byproduct of reaction gas that causes this problem.
As shown in Figure 2 a, the present invention is directed to the reason that the problems referred to above produce and proposed of the present invention improving one's methods: in traditional etch step A and deposition step B, add a steps of exhausting C.In steps of exhausting, the gas of previous treatment step is such as etching gas is discharged from, and the gas of a rear treatment step is such as deposition gases postpones the time passing into, until steps of exhausting completes simultaneously.After in reaction chamber, remaining etching gas is pumped, the byproduct of reaction in the through hole that etching forms can be quickly discharged reaction chamber as SiF4.After being discharged from, byproduct of reaction can pass into next step the sidewall protective gas such as reacting gas C4F8.When switching back etch step, deposition step there is identical process: deposition gases discharge-byproduct of reaction discharge-etching gas passes into.The gas that deposition step will be discharged to the steps of exhausting C in the transfer process of etch step can be that byproduct of reaction is as a small amount of SiF4, also can comprise the little molecular fluorine carbon compounds such as CF4 that produce after C4F8 is decomposed by energetic plasma, can be also the deposition gases C4F8 remaining in through hole.Differential responses gas alternate cycles supply in Bosch etching method, any byproduct of reaction or the previous step reacting gas remaining in through hole can be discharged from by the inventive method.
The time length of the steps of exhausting of setting of the present invention must be discharged to guarantee the residual reaction gas of most of byproduct of reaction or previous step by long enough, through inventor, studies and finds just can guarantee that these gases are reliably discharged above in 0.5 second.The length of evacuation time can not be oversize, and meeting as oversize in the time causes reacting intracavity gas and is substantially drained, and flows into air pressure supplementary in the situation that and decline rapidly can not get upstream gas, and the plasma in reaction chamber can not maintain stable state, likely can extinguish.Plasma extinguishes in reaction chamber can bring series of problems, the surface that is deposited on substrate 100 or mask layer 101 as deposition gas cognition formation number of polymers becomes pollutant, various parameters in whole reaction chamber need to be readjusted, then rekindle plasma and just can proceed plasma etching.And the oversize meeting of evacuation time causes the relative shortening of effective etch period, such as time of etch step and deposition step is all 2 seconds, within a complete cycle, can experience the circulation of four steps of etch step-exhaust-deposition step-exhaust, if evacuation time is greater than two seconds effective process times (etch step+deposition step) and just only has 4 seconds, only account for half of 8 seconds whole circulation timei.Most of the time is used for carrying out exhaust to improve the sidewall pattern of etching through hole, although sidewall pattern can improve, the degradation of etch rate also can cause to such an extent that do not taste mistake.In the present invention, the time of steps of exhausting can be adjusted according to the variation of gas flow or air pressure in etch step or deposition step, the time span of steps of exhausting is also subject to the impact of etching depth, it is also more of a specified duration that the larger byproduct of reaction gas of the degree of depth is discharged required time, so that the time of steps of exhausting also needs is more long.So the steps of exhausting that comprehensive above-mentioned Consideration inserts between etch step and deposition step in whole etching process is advisable with 0.5-4 second, best steps of exhausting time span is less than 2 seconds.
According to the reason that causes curved wall pattern, different the present invention also can have different embodiment, in the interlude process in via etch flow process, main cause is that deposition gases can not arrive reaction zone, etching gas is excessive, so can only add steps of exhausting in etch step in the transfer process of deposition step, to discharge remaining etching gas and byproduct of reaction; The second half section of via etch flow process etching gas is on the low side, deposition gases is on the high side in contrast, now can only at deposition step, in the transfer process of etch step, add steps of exhausting to discharge remaining deposition gases and byproduct of reaction gas, the final through hole with better sidewall pattern that obtains.Be the schematic diagram of formed through hole after employing the inventive method as shown in Figure 2 b, the sidewall on figure split shed 201 both sides has the pattern that is basically perpendicular to mask layer surface, the carrying out that can be conducive to next step conductor material deposition step, the production efficiency of raising chip, reduces costs.So the present invention can be only in etch step in deposition step transfer process or deposition step in etch step transfer process, add steps of exhausting, also can in two transfer processes, all add.
Because above-mentioned curved wall pattern forms gradually, thus only just can be obvious when etching depth is enough large, and etching depth of the present invention can reach and be greater than 100um, even larger.When the degree of depth is greater than 30um certainly, just can observe above-mentioned curved wall, by the adjusting of etching technics parameter, also can apply the incomplete problem of filling that the present invention prevents the follow-up filling stage.
In steps of exhausting of the present invention, can be stop supplies etching gas and the deposition gases gas as described in above-described embodiment, can be also the amount that significantly reduces supply gas, to promote the discharge of byproduct of reaction gas and residual gas.Such as when changing from etch step to deposition step, add steps of exhausting, the flow of etching gas is reduced to below 1/3 of flow in etch step in steps of exhausting, so not only can discharges residual gas in etching opening air pressure and the plasma stability while also contributing to be switched to next step deposition step.
The present invention can be applied to capacitive coupling (CCP) type plasma treatment appts or inductance coupling high type (ICP) plasma treatment appts
Although content of the present invention has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.Those skilled in the art, read after foregoing, for multiple modification of the present invention with to substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (10)
1. dark silicon etching method for forming through hole, for an etch silicon substrate, comprises a patterned mask layer on described silicon chip, and described lithographic method comprises
The etching that cycle alternation carries out and deposition step, until form the through hole with target depth,
In etch step, pass into etching gas and to reaction chamber, silicon chip carried out etching and forms opening,
In deposition step, pass into fluorocarbon gases the opening sidewalls of etching formation protected,
It is characterized in that between described etch step and deposition step, also comprising steps of exhausting, in steps of exhausting, stop passing into etching gas or deposition gases, described steps of exhausting time span is greater than 0.5 second and is less than 4 seconds.
2. lithographic method as claimed in claim 1, is characterized in that, described steps of exhausting time span is less than 2 seconds.
3. lithographic method as claimed in claim 1, is characterized in that, described etching gas comprises SF6, O2, and the fluorocarbon gases in deposition step comprises gas C4F8.
4. lithographic method as claimed in claim 1, is characterized in that, the via depth of described target depth is greater than 30um.
5. lithographic method as claimed in claim 1, is characterized in that, the time span of described steps of exhausting increases along with the increase of via depth.
6. lithographic method as claimed in claim 1, is characterized in that, described steps of exhausting be arranged on through hole reach target depth 1/3 after etch step and deposition step between.
7. lithographic method as claimed in claim 1, it is characterized in that, described in when described via etch reaches first degree of depth, steps of exhausting is only positioned at after steps of exhausting before deposition step, described in when via etch reaches second degree of depth, steps of exhausting is only positioned at after deposition step before etch step, and wherein second degree of depth is greater than first degree of depth.
8. dark silicon etching method for forming through hole, for an etch silicon substrate, comprises a patterned mask layer on described silicon chip, and described lithographic method comprises:
The etching that cycle alternation carries out and deposition step; until form the through hole with target depth; in etch step, passing into etching gas carries out etching and forms opening silicon chip to reaction chamber; in deposition step, passing into fluorocarbon gases protects the opening sidewalls of etching formation to reaction chamber
It is characterized in that, between described etch step and deposition step, also comprise steps of exhausting, the etching passing in steps of exhausting or the flow of deposition gases are less than 1/3 of etching in etching or deposition step or deposition gases flow, and described steps of exhausting time span is greater than 0.5 second and is less than 4 seconds.
9. lithographic method as claimed in claim 8, is characterized in that, described steps of exhausting time span is less than 2 seconds.
10. lithographic method as claimed in claim 8, is characterized in that, described target depth is greater than 30um.
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Cited By (6)
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| CN104285283A (en) * | 2012-05-07 | 2015-01-14 | 株式会社电装 | Production method for semiconductor substrate |
| CN105565257A (en) * | 2014-10-13 | 2016-05-11 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Etching method for inclined hole |
| CN105679700A (en) * | 2014-11-21 | 2016-06-15 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Silicon deep hole etching method |
| CN105720003A (en) * | 2014-12-03 | 2016-06-29 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Deep silicon hole etching method |
| CN106548933A (en) * | 2015-09-23 | 2017-03-29 | 北京北方微电子基地设备工艺研究中心有限责任公司 | A kind of etching technics |
| CN108747598A (en) * | 2018-04-26 | 2018-11-06 | 华中光电技术研究所（中国船舶重工集团有限公司第七七研究所） | Ultra-smooth glass lens multipole ion polishing method |
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| US6261962B1 (en) * | 1996-08-01 | 2001-07-17 | Surface Technology Systems Limited | Method of surface treatment of semiconductor substrates |
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| CN104285283A (en) * | 2012-05-07 | 2015-01-14 | 株式会社电装 | Production method for semiconductor substrate |
| CN104285283B (en) * | 2012-05-07 | 2018-01-26 | 株式会社电装 | The manufacture method of semiconductor substrate |
| CN105565257A (en) * | 2014-10-13 | 2016-05-11 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Etching method for inclined hole |
| CN105565257B (en) * | 2014-10-13 | 2017-10-13 | 北京北方华创微电子装备有限公司 | Inclined hole lithographic method |
| CN105679700A (en) * | 2014-11-21 | 2016-06-15 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Silicon deep hole etching method |
| CN105720003A (en) * | 2014-12-03 | 2016-06-29 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Deep silicon hole etching method |
| CN105720003B (en) * | 2014-12-03 | 2019-01-18 | 北京北方华创微电子装备有限公司 | Deep silicon hole lithographic method |
| CN106548933A (en) * | 2015-09-23 | 2017-03-29 | 北京北方微电子基地设备工艺研究中心有限责任公司 | A kind of etching technics |
| CN108747598A (en) * | 2018-04-26 | 2018-11-06 | 华中光电技术研究所（中国船舶重工集团有限公司第七七研究所） | Ultra-smooth glass lens multipole ion polishing method |
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