CN103730411B - Through-silicon-via (TSV) etching method - Google Patents
Through-silicon-via (TSV) etching method Download PDFInfo
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- CN103730411B CN103730411B CN201310574583.4A CN201310574583A CN103730411B CN 103730411 B CN103730411 B CN 103730411B CN 201310574583 A CN201310574583 A CN 201310574583A CN 103730411 B CN103730411 B CN 103730411B
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- 238000005530 etching Methods 0.000 title claims abstract description 83
- 238000000034 method Methods 0.000 title claims abstract description 56
- 230000008021 deposition Effects 0.000 claims abstract description 56
- 238000006243 chemical reaction Methods 0.000 claims abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000007789 gas Substances 0.000 claims description 62
- 238000012545 processing Methods 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 description 48
- 239000006227 byproduct Substances 0.000 description 14
- 230000008569 process Effects 0.000 description 14
- 230000009466 transformation Effects 0.000 description 6
- 239000012495 reaction gas Substances 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000002210 silicon-based material Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 206010051986 Pneumatosis Diseases 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000003851 corona treatment Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 208000002925 dental caries Diseases 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 150000003384 small molecules Chemical class 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
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Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
- B81C1/00619—Forming high aspect ratio structures having deep steep walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
- B81C2201/0111—Bulk micromachining
- B81C2201/0112—Bosch process
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- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Plasma & Fusion (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The invention provides a through-silicon-via (TSV) etching method. A silicon wafer to be processed is arranged in a plasma processing chamber, the surface of the silicon wafer includes a graphical mask layer, the steps of etching and deposition are carried out circularly and alternatively until a through via with a target depth is formed, etching gas is led into a reaction chamber in the step of etching to etch a silicon substrate, openings are formed, and fluorocarbon gas is led in the step of deposition to protect the lateral walls of the openings formed in the step of etching. The TSV etching method is characterized in that the step of gas exhaust is included between the step of etching and the step of deposition, and leading-in of the etching gas or deposition gas is stopped in the step of gas exhaust. By means of the TSV etching method, arc lateral walls of the etched through via are prevented from being generated.
Description
Technical field
The present invention relates to corona treatment field, more particularly, to a kind of deep hole silicon etching method is to obtain more preferably side wall
Pattern.
Background technology
In technical field of manufacturing semiconductors, in mems(micro-electro-mechanical systems, micro-electro-mechanical systems
System) and the field such as 3d encapsulation technology, it usually needs deep via etching is carried out to materials such as silicon.For example, in crystalline silicon lithographic technique
In, the depth of deep silicon hole (through-silicon-via, tsv) reaches hundreds of micron, its depth-to-width ratio and is even much larger than 30,
Generally to etch body silicon using deep reaction ion etching method to be formed.Described silicon materials are mainly monocrystal silicon.Complete to etch
Conductor material such as copper is filled afterwards, fill method can be to utilize chemical vapor deposition in the hole of also oriented etching formation or groove
Or physical vapor deposition (pvd) process (cvd).Copper product due to above-mentioned deposition deposits from the top down, so etching
The tsv hole opening shape being formed most preferably needs trapezoid-shaped openings, or has the opening of vertical sidewall.
Existing typical lithographic technique is using etching-deposition step alternately, silicon quickly to be etched, this
Lithographic method is bosch etching method again.Bosch method as described by United States Patent (USP) us5501893 is using etching and deposition steps
Rapid method alternately is realized to the quick of single crystal silicon material layer and etching vertically downward.Etching gas allusion quotation as shown in Figure 1a
Alternately being passed through in reaction chamber as sf6 and deposition gases c4f8 of type, wherein etching gas can also include other gases such as o2,
Deposition gases can also include gas fluorocarbons.Only have etching gas to be passed through reaction chamber in Fig. 1 a in etch step a, sink
Pneumatosis body stops being passed through reaction chamber, or the flow that is passed through little to etching will not being impacted.Carve after the completion of etch step
Erosion gas stops being passed through or flow is reduced to and does not interfere with follow-up deposition step, and deposition gases start to be passed through setting simultaneously
Flow enters deposition step, so alternately back and forth performs etching step and deposition step, until reaching etching depth.Wherein etch
The time span of step and deposition step can change according to the change of etching depth, and typical time span can be 1-9
Second.When being etched using prior art bosch etching method, the hole sidewalls of formation are in slight arc (bowing).As
Profile shown in Fig. 1 b, the hole that etching is formed is all less than interlude diameter in top and bottom.Wherein the top opening
Etachable material Rotating fields include the enlarged drawing at place as shown in Figure 1 b: mask layer 110(such as photoresist pr or sio2), mask layer 10
Lower section is crystalline silicon material layer 100 to be etched, and etching forms hole 200.Such hatch frame is unfavorable for leading of next step
Electric material deposits, and the less opening sidewalls in top can stop the further precipitation of conductive material in the hole of lower section it is likely that can be
After hole carries out conductive material filling step, in hole, yet suffer from cavity.The presence of these cavitys not only can deteriorate conductive spy
Property even can cause to need the circuit of conducting to disconnect.This cannot be eliminated by the regulation of adjustable parameter in traditional bosch etching method
One unfavorable sidewall profile.The hole that this results in using traditional bosch etching method is formed brings problem in following process,
Lead to the discarded of whole product eventually, cause very big waste and loss.So industry needs a kind of simple and effective lithographic method
Improve deep hole silicon etching method, to eliminate the curved wall occurring in bosch etching method.
Content of the invention
It is an object of the invention to provide a kind of deep hole silicon etching method is used for etching silicon chip, described silicon chip includes one
Patterned mask layer, described lithographic method includes: etching and deposition step that cycle alternation is carried out, has target until being formed
The through hole of depth, is passed through etching gas in etch step and to reaction chamber, silicon chip is performed etching and form opening, in deposition
It is passed through the opening sidewalls that fluorocarbon gases are formed to etching in step and protected it is characterised in that in described etch step
Also include steps of exhausting and deposition step between, stop being passed through etching gas or deposition gases in steps of exhausting, or be passed through
Etching/deposition gases be less than in corresponding etching/deposition step accordingly etching/deposition gases flow 1/3, during described steps of exhausting
Between length be more than 0.5 second and be less than 4 seconds.Optimal steps of exhausting time span can be less than 2 seconds.Wherein etching gas include
Sf6, o2, deposition step includes gas c4f8.
The target depth of etching through hole of the present invention is more than 30um, and in deep hole silicon etching field, the present invention can embody etching
The more vertical advantage of hole side wall.
The time span of wherein steps of exhausting increases with the increase of via depth, with improve production efficiency, changes simultaneously
Kind sidewall profile.
Wherein steps of exhausting is arranged on via etch and reaches etch step and deposition step after the 1/3 of target depth
Between, improve etching efficiency during silicon material layer within 1/3 of target depth at etching through hole opening.
Described via etch reaches before described steps of exhausting during the first depth is only positioned at deposition step after steps of exhausting, leads to
Hole etching reaches before described steps of exhausting during the second depth is only positioned at etch step after deposition step, and the wherein second depth is more than
First depth, etching through hole during corresponding different depth can select between etch step-deposition step or deposition step-
Add steps of exhausting between etch step, be capable of the improvement sidewall profile of more optimization, and during each process step is changed relatively
All add the embodiment of steps of exhausting, save the time of unnecessary steps of exhausting.
Brief description
Fig. 1 a is etching gas and deposition gases gas flow distribution in prior art bosch etching method；
Fig. 1 b forms deep silicon hole overall schematic for prior art bosch etching method；
Fig. 2 a is the lithographic method gas flow schematic diagram being provided using the present invention；
Fig. 2 b forms deep silicon hole overall schematic when being and completing using the lithographic method that the present invention provides；
Specific embodiment
Below in conjunction with Fig. 1～Fig. 2, by preferred specific embodiment, describe the present invention in detail.
Study through inventor and find, can produce during using traditional bosch etching method curved wall through hole mainly former
Because being: because the application scenario etching through hole depth of tsv is very big, generally higher than 30um is often more than 100um, so carving
After erosion proceeds to certain depth, the by-product such as sif4 of reaction is difficult to diffuse up by etching the through hole being formed, and also just cannot
Taken away by the air extractor below reaction intracavity.Byproduct of reaction cannot be discharged and can be led to new reacting gas sf6 and c4f8 no
Method is with expected quantity to arrival conversion zone.Such as when etching depth exceedes the 1/3 of whole via depth desired depth,
C4f8 is affected by byproduct of reaction first, and portion gas do not reach via bottoms and just taken away by air extractor.Because side wall is protected
Protect deficiency can cause become larger with the increase through hole bore of etching depth although leading in the cycle of each etching-deposition
The change of bore open is very trickle, but the structure gradually expanded as shown in Figure 1 b in the middle of macroscopically through hole.With etching
Depth increase further such as more than overall depth 1/2 when, the downward diffusion of etching gas sf6 is also affected, and this can make
Become the reduction of etch rate in each etch step, the bore in turn resulting in through hole tapers into.Ultimately form as shown in Figure 1 b
Camber line side wall deep silicon hole.So prevention maximally effective solution of appearance of curved wall in bosch etching method is
Discharge the byproduct of reaction gas causing this problem.
As shown in Figure 2 a, the improved method that the present invention proposes the present invention for the problems referred to above Producing reason: in tradition
Etch step a and deposition step b in add steps of exhausting c.The gas ratio of previous process step in steps of exhausting
As etching gas are discharged, the gas of the rear process step time that such as deposition gases delay is passed through simultaneously, until aerofluxuss
Step completes.After the remaining etching gas of reaction intracavity are pumped, the byproduct of reaction such as sif4 in through hole that etching is formed
Reaction chamber can be quickly discharged.The wall protection of the side such as reacting gas c4f8 of next step can be passed through after byproduct of reaction is discharged
Gas.There is when deposition step switches back into etch step identical process: deposition gases discharge-byproduct of reaction discharges-
Etching gas are passed through.The wanted expellant gas of steps of exhausting c in the transformation process of etch step for the deposition step can be anti-
Answer by-product such as a small amount of sif4 it is also possible to include the small molecule fluorine carbonization such as cf4 of generation after c4f8 is decomposed by energetic plasma
Compound or residual deposition gases c4f8 in through-holes.In bosch etching method, differential responses gas alternate cycles supply
Answer, any byproduct of reaction or the previous step reacting gas remaining in through hole can be arranged by the inventive method
Go out.
The present invention setting steps of exhausting time length must long enough with ensure most of byproduct of reaction or on
The residual reaction gas of one step is discharged, and finds more than 0.5 second it is ensured that these gases are reliably discharged through inventor's research.
The length of evacuation time nor oversize, as oversize in the time can lead to react intracavity gas be substantially drained, cannot get upstream
Gas flows into air pressure in the case of supplementing and declines rapidly, and the plasma of reaction intracavity can not maintain steady statue it is possible to meeting
Extinguish.Plasma can bring series of problems in reaction intracavity extinguishing, and such as deposition gas are known from experience formation number of polymers and are deposited on
The surface of substrate 100 or mask layer 101 becomes pollutant, and the various parameters of whole reaction intracavity need to readjust, then weigh
Newly light plasma and just can proceed plasma etching.And the oversize relative contracting that can cause effective etch period of evacuation time
Short, the time of such as etch step and deposition step is all 2 seconds, can experience within a complete cycle etch step-aerofluxuss-
The circulation of four steps of deposition step-aerofluxuss, if evacuation time is more than two seconds effectively process time (etch step+
Deposition step) just only 4 seconds, only account for the whole circulation time half of 8 seconds.Most of the time is used for being exhausted to improve etching
The sidewall profile of through hole is although the degradation that sidewall profile can obtain improving still etch rate will also result in not taste
Lose.In the present invention, the time of steps of exhausting can adjust according to the change of gas flow or air pressure in etch step or deposition step
Whole, the time span of steps of exhausting is also affected by etching depth, and depth bigger byproduct of reaction gas discharges required time
More long, thus the time of steps of exhausting be also required to more long.So summary Consideration etches step in whole etching process
The steps of exhausting of rapid insertion and deposition step between was advisable with the 0.5-4 second, and optimal steps of exhausting time span is less than 2 seconds.
Can also there are different embodiments according to the present invention different the reason causing curved wall pattern, such as in via etch
During the interlude of flow process, main cause is that deposition gases can not reach reaction zone, etching gas excessive it is possible to only
Add steps of exhausting in etch step in the transformation process of deposition step, to discharge etching gas and the reaction by-product of remnants
Thing；Second half section etching gas in via etch flow process are on the low side and deposition gases are on the high side in contrast, now can only exist
Deposition step adds steps of exhausting to discharge deposition gases and the byproduct of reaction gas of remnants in the transformation process of etch step
Body, final acquisition has the through hole of more preferably sidewall profile.As shown in Figure 2 b by using the through hole being formed after the inventive method
Schematic diagram, the side wall in figure opening 201 both sides has the pattern being basically perpendicular to mask layer surface, can be conducive to next step
The carrying out of conductor material deposition steps, improves the production efficiency of chip, reduces cost.So the present invention can be only in etch step
To in deposition step transformation process or deposition step adds steps of exhausting it is also possible at two in etch step transformation process
All add in transformation process.
Because above-mentioned curved wall pattern gradually forms, so just can compare only when etching depth is sufficiently large
More apparent, etching depth of the present invention can reach more than 100um, even more greatly.Certainly depth just can observe when being more than 30um
Above-mentioned curved wall, can also apply the present invention to prevent the filling of subsequent filling stage not complete by the regulation of etch process parameters
Full problem.
In steps of exhausting of the present invention, can be stopping supply etching gas and the deposition gases as described in above-described embodiment
Gas or the amount significantly reducing supply gas, to promote the discharge of byproduct of reaction gas and residual gas.Such as exist
When etch step is changed to deposition step, add steps of exhausting, be reduced to carve by the flow of etching gas in steps of exhausting
Less than the 1/3 of flow in erosion step, so not only can discharge the residual gas in etching opening and additionally aid and be switched to next
Air pressure during step deposition step and plasma stability.
Present invention could apply to Capacitance Coupled (ccp) type plasma treatment appts or inductive type (icp) etc. from
Sub-processing unit
Although present disclosure has been made to be discussed in detail by above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read the above, for the present invention's
Multiple modifications and substitutions all will be apparent from.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (5)
1. a kind of deep silicon hole lithographic method is used for etching silicon chip, and described silicon chip includes a patterned mask layer, institute
State lithographic method to include
Etching and deposition step that cycle alternation is carried out, until forming the through hole with target depth,
It is passed through etching gas to reaction chamber, silicon chip to be performed etching and form opening in etch step,
It is passed through the opening sidewalls that fluorocarbon gases are formed to etching and protected it is characterised in that in institute in deposition step
State and also include steps of exhausting between etch step and deposition step, stop being passed through etching gas or deposition gas in steps of exhausting
Body, described steps of exhausting time span is more than 0.5 second and is less than 4 seconds,
Described via etch reaches before described steps of exhausting during the first depth is only positioned at deposition step after etch step, and described
One depth is more than the 1/3 of target depth, and via etch reaches after during the second depth, described steps of exhausting is only positioned at deposition step
Before etch step, the wherein second depth is more than the first depth, and the second depth is more than the 1/2 of described through hole target depth.
2. lithographic method as claimed in claim 1 is it is characterised in that described steps of exhausting time span is less than 2 seconds.
3. lithographic method as claimed in claim 1 is it is characterised in that described etching gas include sf6, o2, in deposition step
Fluorocarbon gases include gas c4f8.
4. lithographic method as claimed in claim 1 is it is characterised in that the via depth of described target depth is more than 30um.
5. lithographic method as claimed in claim 1 is it is characterised in that the time span of described steps of exhausting is with via depth
Increase and increase.
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| CN201310574583.4A CN103730411B (en) | 2013-11-15 | 2013-11-15 | Through-silicon-via (TSV) etching method |
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| JP5713043B2 (en) * | 2012-05-07 | 2015-05-07 | 株式会社デンソー | Manufacturing method of semiconductor substrate |
| CN105565257B (en) * | 2014-10-13 | 2017-10-13 | 北京北方华创微电子装备有限公司 | Inclined hole lithographic method |
| CN105679700B (en) * | 2014-11-21 | 2019-08-23 | 北京北方华创微电子装备有限公司 | Silicon deep hole lithographic method |
| CN105720003B (en) * | 2014-12-03 | 2019-01-18 | 北京北方华创微电子装备有限公司 | Deep silicon hole lithographic method |
| CN106548933B (en) * | 2015-09-23 | 2020-07-17 | 北京北方华创微电子装备有限公司 | Etching process |
| CN108747598B (en) * | 2018-04-26 | 2020-04-21 | 华中光电技术研究所（中国船舶重工集团有限公司第七一七研究所） | Multistage ion polishing method for ultra-smooth glass lens |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6261962B1 (en) * | 1996-08-01 | 2001-07-17 | Surface Technology Systems Limited | Method of surface treatment of semiconductor substrates |
| CN1675750A (en) * | 2002-08-16 | 2005-09-28 | 优利讯美国有限公司 | Sidewall smoothing in high aspect ratio/deep etching using a discrete gas switching method |
| CN101962773A (en) * | 2009-07-24 | 2011-02-02 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Deep silicon etching method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6261962B1 (en) * | 1996-08-01 | 2001-07-17 | Surface Technology Systems Limited | Method of surface treatment of semiconductor substrates |
| CN1675750A (en) * | 2002-08-16 | 2005-09-28 | 优利讯美国有限公司 | Sidewall smoothing in high aspect ratio/deep etching using a discrete gas switching method |
| CN101962773A (en) * | 2009-07-24 | 2011-02-02 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Deep silicon etching method |
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