CN105448697A - Etching method for high-aspect-ratio structure and MEMS device manufacturing method - Google Patents
Etching method for high-aspect-ratio structure and MEMS device manufacturing method Download PDFInfo
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- CN105448697A CN105448697A CN201410345037.8A CN201410345037A CN105448697A CN 105448697 A CN105448697 A CN 105448697A CN 201410345037 A CN201410345037 A CN 201410345037A CN 105448697 A CN105448697 A CN 105448697A
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Abstract
The invention discloses an etching method for a high-aspect-ratio structure. The etching method comprises main etch, transition etch and over etch, wherein the main etch process is carried out to etch a semiconductor substrate until reaching the place above a target depth, and forming a first etch hole; the transition etch process is carried out to etch the semiconductor substrate continuously until reaching the target depth, and forming a second etch hole, the critical dimension of which is smaller than that of the first etch hole; and the over etch process is used for etching the side wall of the second etch hole and finally forming the target-depth high-aspect-ratio structure. The bottom portion of the high-aspect-ratio structure can be protected from being etched transversely, thereby preventing the generation of transverse notch in the etching process, and improving the performance of the device.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing process technology field, particularly relate to a kind of lithographic method of high aspect ratio structure and the manufacture method of corresponding MEMS.
Background technology
Deep reaction ion etching technology (Deepreactiveionetching, DRIE) is a kind of etching technics based on plasma technique, is mainly used in processing the high aspect ratio microstructures with vertical sidewall, has the advantages that up rightness is good.Greatly expand working ability and the scope of application of bulk silicon technological in this technology more than ten years in the past, applied very extensive in MEMS process technology and emerging 3D interconnection technique.But add man-hour in the MEMS high aspect ratio microstructures processing based on SOI technology and the 3D interconnection high aspect ratio structure based on SOI technology, DRIE technique but also exists some and is considered to etch rate and the disadvantageous effect of structure outline, as lateral etching (Notching) effect.
The conventional RIE technique being applied to MEMS process technology and 3D interconnection technique realizes the etching of high-aspect-ratio based on the principle of Bosch technique, primarily of two step compositions: the first step, main etching (MainEtch), be used for forming the body shape of high aspect ratio structure, carved fast at this step major part silicon and formed deep trouth to the greatest extent, the body normal degree of major effect high aspect ratio structure; Second step, over etching (OverEtch), this step with remove in main etch step do not carve most silicon remain.
In order to the requirement of the perpendicularity and roughness that improve the sidewall of through hole, existing RIE etches high aspect ratio structure and usually adopts Bosch technique.US Patent No. 5501893 pairs of Bosch techniques record road: the method that Bosch technique is utilization deposition, etching hockets carries out deep hole etching.Its detailed process is: provide Semiconductor substrate, described Semiconductor substrate is formed with the photoresist mask layer with opening; Carry out etch step: in etching cavity, pass into etching gas (such as: SF
6), etching gas is dissociated into plasma, etches described Semiconductor substrate, forms etched hole; Carry out deposition step: in etching cavity, pass into deposition gases (such as: CF
4, C
4f
8), deposition gases is dissociated into plasma, and form polymer at the sidewall of etched hole, described polymer protects the sidewall of established etched hole to be etched into when next etch step, thus ensures the anisotropy of whole Bosch etching process; Repeat above-mentioned etch step and deposition step, high speed alternate cycles, until form high aspect ratio structure in the semiconductor substrate.
But because electronics has wider angular distribution than ion, sidewall and mask will more than covering ion to covering of electronics, and therefore, finally the ion arrived bottom hole will more than electronics.At the end of main etching (when etching the buried silicon oxide layer arriving SOI substrate), because silica is insulator, ionic charge accumulates in trench bottom, cause the difference of channel bottom electromotive force, the repulsion of Accumulating charge and the bombardment sidewall that alters course can be subject to when subsequent ion bombardment bottom land, cause sidewall bottom by sapping.Produce lateral recesses (Notching) as shown in Figure 1.
Therefore, how to become based on the elimination Notching effect in the MEMS of SOI technology and the RIE etching of 3D interconnection the problem that industry needs solution badly.
In order to eliminate etching lateral recesses; Chinese patent ZL200310122904.3 discloses a kind of method of two step over etchings; first step high pressure over etching; this high pressure easily makes to produce high molecular polymer in plasma; make on grid sidewall and bottom formation passivation protection layer; second step is general conventional over etching, and it is slightly low that its pressure compares the first step, does not carve most silicon remain with removing.But the etch period of this two steps over etching is difficult to grasp, if the first step over etching time is longer, the passivation protection layer of sidewall is thicker, and pattern more tilts, and transverse concave groove occurs that possibility is less; If second step over etching etch period is longer, grid are more vertical, but the possibility that transverse concave groove occurs is larger.Therefore, the method for this patent is difficult to both ensure do not have transverse concave groove, makes sidewall profile vertical as far as possible again simultaneously.
Chinese patent application CN103400800A discloses a kind of Bosch lithographic method, its etch step is, pass into etching gas, applying source radio frequency power source to reaction chamber to maintain the plasma concentration in reaction chamber, the first bias power source that simultaneously applies, to pedestal, forms etched hole along opening etched portions substrate; Its deposition step is, passes into deposition gases, and the second bias power source that applies is to pedestal, and at sidewall surfaces and the mask layer surface deposition formation polymer of etched hole, the frequency in the second bias power source is greater than the frequency in the first bias power source.But the lithographic method of this patent application needs constantly to carry out alternately adjustment to the frequency in etching and deposition step bias power source, adds technology difficulty and cost, is also unfavorable for the stability of technique.
Summary of the invention
The object of the invention is to make up above-mentioned the deficiencies in the prior art, a kind of high depth-width-ratio structure etching method is provided, by increasing by a step transition etching technics between main etching technique and over etching technique, avoiding the generation of lateral recesses in etching process.
For achieving the above object, the invention provides a kind of lithographic method of high aspect ratio structure, it comprises the following steps:
Step S01, provides semi-conductive substrate;
Step S02, perform main etching technique, etch described Semiconductor substrate to stop to during the top position of target depth to form the first etched hole, this main etching technique comprises etch step and the deposition step of alternate cycles, and described first etched hole limits the body shape of high aspect ratio structure;
Step S03, perform transition etching technics, continue the described Semiconductor substrate of etching to described target depth to form the second etched hole that critical size is less than the first etched hole, this transition etching technics comprises etch step and the deposition step of alternate cycles, and wherein etching/the deposition rate of etch step and deposition step is than the etching/deposition rate ratio being less than etch step and deposition step in described main etching technique; And
Step S04, performs over etching technique, etches the sidewall of described second etched hole to form the high aspect ratio structure reaching described target depth in described Semiconductor substrate.
Further, in step S02, described main etching technique etches the At The Height stopping of above described Semiconductor substrate to described target depth 2-3 μm.
Further, the etching depth of described main etching technique is controlled by endpoint Detection or process time in step S02.
Further, the etching depth of described transition etching technics is controlled in step S03 by etching terminal detection technique or process time.
Further, step S01 comprises and forms patterned mask layer on the semiconductor substrate; Described main etching technique, transition etching technics and over etching technique all with described patterned mask layer for etch mask performs etching technics.
Further, the etching/deposition rate of described main etching technique is than being 1:1 ~ 2:1, and the etching/deposition rate ratio of described transition etching technics is less than or equal to 1:1.
Further, when carrying out described main etching technique, transition etching technics and over etching technique, the gas passing into treatment chamber comprises etching gas and deposition gases, and described etching gas is SF
6, described deposition gases is C
4f
8.
Further, the pressure for the treatment of chamber described in described main etching technique, transition etching technics and over etching technique, temperature, gas flow rate are all identical with radio frequency source power; Wherein the flow velocity of etching gas is 100 ~ 2000sccm, the flow velocity of deposition gases is 100 ~ 2000sccm, the pressure limit for the treatment of chamber is 40 ~ 120 millitorrs, and the power of source radio frequency source is 1500 ~ 3000 watts, and the power of biased radio frequency source exports in a pulsed fashion and is greater than 300 watts.
The present invention also proposes a kind of manufacture method of MEMS based on the lithographic method of above-mentioned high aspect ratio structure, comprise the following steps: provide a base substrate, this base substrate deposits oxide layer; There is provided semi-conductive substrate and by described base substrate and described Semiconductor substrate bonding; Perform main etching technique, etch described Semiconductor substrate to stop to during top position bottom it to form the first etched hole, this main etching technique comprises etch step and the deposition step of alternate cycles, and described first etched hole limits the body shape of high aspect ratio structure; Perform transition etching technics, continue the described Semiconductor substrate of etching until expose described oxide layer surface to form the second etched hole that critical size is less than described first etched hole, this transition etching technics comprises etch step and the deposition step of alternate cycles, and wherein etching/the deposition rate of etch step and deposition step is than the etching/deposition rate ratio being less than etch step and deposition step in described main etching technique; And perform over etching technique, etch the sidewall of described second etched hole to form the high aspect ratio structure running through described Semiconductor substrate.
The present invention also proposes the manufacture method of another kind of MEMS based on above-mentioned high depth-width-ratio structure etching method, comprise the following steps: provide a base substrate, this base substrate is formed an oxide layer; MEMS cavity is formed in described base substrate and oxide layer; There is provided semi-conductive substrate and by described base substrate and described Semiconductor substrate bonding; Perform main etching technique, etch described Semiconductor substrate to stop to during top position bottom it to form the first etched hole, this main etching technique comprises etch step and the deposition step of alternate cycles, and described first etched hole limits the body shape of high aspect ratio structure; Perform transition etching technics, continue the described Semiconductor substrate of etching to bottom it to be formed and described MEMS cavity connects and critical size are less than the second etched hole of described first etched hole, this transition etching technics comprises etch step and the deposition step of alternate cycles, and wherein etching/the deposition rate of etch step and deposition step is than the etching/deposition rate ratio being less than etch step and deposition step in described main etching technique; And perform over etching technique, the sidewall etching described second etched hole with formed run through described Semiconductor substrate and with the high aspect ratio structure of described MEMS cavity connects.
The lithographic method of high aspect ratio structure provided by the invention; by between conventional main etching technique and over etching technique; increase the step of a step transition etching technics; wherein; main etching technique stops when high aspect ratio structure being etched to target depth (as lower floor's etching stop layer) top position; carry out etching subsequently/deposition rate is than less transition etching technics; to protect bottom high aspect ratio structure not because of over etching technique by lateral etching; thus avoid producing lateral recesses bottom high aspect ratio structure, can device performance be significantly improved.
Accompanying drawing explanation
For can clearer understanding objects, features and advantages of the present invention, below with reference to accompanying drawing, preferred embodiment of the present invention be described in detail, wherein:
Fig. 1 is the schematic diagram of the bottom notch of the high aspect ratio structure adopting existing Bosch technique to be formed;
Fig. 2 is the schematic flow sheet of the lithographic method of high aspect ratio structure of the present invention;
Fig. 3 a to 3d is the schematic cross-section of each step of lithographic method of high aspect ratio structure of the present invention;
Fig. 4 a to 4d is the schematic cross-section of the lithographic method making MEMS of one embodiment of the invention application high aspect ratio structure;
Fig. 5 a to 5c is the schematic cross-section of the lithographic method making MEMS of another embodiment of the present invention application high aspect ratio structure.
Embodiment
Fig. 2 is the schematic flow sheet of high depth-width-ratio structure etching method of the present invention, Fig. 3 a ~ 3d is the cutaway view of each step of lithographic method of high aspect ratio structure, incorporated by reference to reference Fig. 2 and Fig. 3 a ~ 3d, the lithographic method of high aspect ratio structure is completed by deep reaction ion etching (RIE) technique, and it specifically comprises the following steps:
Step S01, please refer to Fig. 3 a, provides Semiconductor substrate 10.
In this step, also comprise and form mask layer 11 on a semiconductor substrate and graphically, in mask layer, form the window 11a exposing semiconductor substrate surface.Wherein, the material of mask layer can be selected from the sandwich construction of silica, silicon nitride or its composition, and metal hardmask material also can be adopted as titanium nitride etc., and the present invention is not limited.The graphical chemical wet etching by routine of mask layer realizes, and therefore not to repeat here.
Step S02, please refer to Fig. 3 b, performs main etching (MainEtch) technique, and its etch semiconductor substrates stops to during the top position of target depth, forms the first etched hole.
In this step, main etching technique is Bosch (Bosch) etching, comprises etch step and the deposition step of alternate cycles.Its detailed process is: etch step using plasma dry etching carries out, and passes into etching gas, as SF in treatment chamber
6, etching gas is ionized as plasma, is not etched by the expose portion that mask layer covers Semiconductor substrate, forms etched hole; In etching cavity, deposition gases is passed into when carrying out deposition step; as C4F8; deposition gases is ionized as plasma; polymer is formed at the sidewall of etched hole; this polymer protects the sidewall of established etched hole to be etched into when next etch step, thus ensures the anisotropy of whole Bosch etching technics.Repeat above-mentioned etch step and deposition step, until form the first etched hole 12 in the semiconductor substrate, as shown in Figure 3 b.It should be noted that, first etched hole 12 defines the shape of the final high aspect ratio structure formed, but its degree of depth is less than the target depth of high aspect ratio structure, namely when being etched to the position of certain altitude above the distance objective degree of depth, main etching technique stops, and treats that transition etching technics and over etching technique are removed to leave a part of semiconductive substrate thickness.Preferably, main etching technique is that the At The Height of above etch semiconductor substrates to target depth 2-3 μm stops, and controls by endpoint Detection or process time the etching depth deciding main etching technique.
During main etching technique, etching/deposition rate is than being 1:1 to 2:1, and make the speed of etching very fast like this, the pattern therefore etching the first etched hole of formation is higher.
Step S03, please refer to Fig. 3 c, performs transition etching (TransitionEtch) technique, continues etch semiconductor substrates to target depth, form the second etched hole that critical size is less than the first etched hole.
In this step, transition etching technics is similarly Bosch technique, comprises etch step and the deposition step of alternate cycles, and mask layer is still as the mask of transition etching technics.Wherein, etch step using plasma dry etching, etching gas still selects SF
6, in deposition step, deposition gases still selects CF
4etch step and deposition step alternate cycles, it should be noted that the etching/deposition rate of etch step and deposition step in this step than the etching being less than etch step and deposition step in main etching technique/deposition rate ratio, preferably both etching/deposition rate ratios are less than or equal to 1:1.Transition etching technics is along the first etched hole etch semiconductor substrates and bottom the first etched hole 12, form the second etched hole 13 that critical size (criticaldimension) is less than the critical size (that is to say the critical size of high aspect ratio structure) of the first etched hole, as shown in Figure 3 c.Wherein control by endpoint Detection or process time the etching depth deciding transition etching technics.First etched hole 12 and the second etched hole 13 form a step nibs.In general, bottom the second etched hole 13 side-walls have part semiconductor substrate materials remain.Because etching/deposition rate in this step reduces than the main etching technique compared to step S01, therefore overall etch rate slows down, and the polymer that deposition step generates is formed in the sidewall of the second etched hole more, the bottom transverse depression that follow-up over etching technique causes can be offset.
Step S03, please refer to Fig. 3 d, performs over etching (OverEtch) technique, etches the sidewall of the second etched hole to form the high aspect ratio structure of target depth in the semiconductor substrate.
In this step, still using mask layer as etch mask, and still employing comprises the etch step of alternate cycles and the Bosch technique of deposition step.Wherein, etch step using plasma dry etching, etching gas still selects SF
6, in deposition step, deposition gases still selects CF
4, etch step and deposition step alternate cycles.Etching/the deposition rate of etch step and deposition step is than the etching/deposition rate ratio being greater than etch step and deposition step in transition etching technics in this step, etching/the deposition rate that such as can adopt with main etching technique is than identical, the duration of over etching technique is according to process requirements and etching/deposition rate ratio setting, can be identical with the over etching process time of prior art, generally occupy the more than at least 20% of whole high aspect ratio structure etch period.Transition etching technics etches the sidewall of the second etched hole 12, also comprises semiconductor substrate materials residual bottom the second etched hole.Critical size due to the second etched hole is less than the first etched hole, over etching technique just can remove the stage portion of the protrusion of step nibs to the lateral etching of the second etched hole lateral wall polymer, and the final high aspect ratio structure 14 reaching target depth that formed after making over etching technique, and can not transverse concave groove be produced bottom high aspect ratio structure, ensure that the integrality of high aspect ratio structure sidewall thus.
Carrying out in these three steps of main etching technique, transition etching technics and over etching technique, the pressure for the treatment of chamber, temperature, the technological parameter such as gas flow rate and radio frequency source power all can be set as identical, wherein the pressure limit for the treatment of chamber is 40 ~ 120 millitorrs, is preferably 70 millitorrs; The power of source radio frequency source is 1500 ~ 3000 watts, is preferably 1800 watts; The power of biased radio frequency source exports in a pulsed fashion and power is greater than 300 watts, and pulse duty factor is about 10%.Etching gas SF
6flow velocity be 100 ~ 2000sccm, deposition gases C
4f
8flow velocity be 100 ~ 2000sccm, be preferably 1000sccm.
The lithographic method of high aspect ratio structure of the present invention can be applicable to the isolated groove of MEMS and the preparation of fixed electrode, also can be applied to the preparation of the silicon through hole TSV of 3D interconnection.Next will in conjunction with specific embodiments the application MEMS isolated groove of high depth-width-ratio structure etching method of the present invention and the making of fixed electrode be described in detail.
embodiment 1
In the present embodiment, apply the isolated groove of above-mentioned high depth-width-ratio structure etching method formation based on the MEMS of SOI technology.
First, please refer to Fig. 4 a, provide the first Semiconductor substrate 100, this first Semiconductor substrate, as base substrate, it also forms layer of oxide layer 101.
Then, please refer to Fig. 4 b, the second Semiconductor substrate 200 is provided and itself and the first Semiconductor substrate 100 is had the side bonding of oxide layer.Bonding technology is melting bonding or is called Si-Si bonding, the method of Si-Si bonding comprise planarization first Semiconductor substrate and the second Semiconductor substrate surface, carry out cleaning and remove surface contaminant, by staggered relatively for the first and second Semiconductor substrate, apply certain pressure in high temperature environments and make both combine.Concrete technology method is well known to those skilled in the art, and therefore not to repeat here.The first Semiconductor substrate after bonding, oxide layer and the second Semiconductor substrate form soi structure substrate, and respectively as top silicon layer, insulating barrier and bottom silicon layer.
Then, please refer to Fig. 4 c, high aspect ratio structure 201 is etched in the second Semiconductor substrate 200, comprise aforesaid main etching processing step, transition etching process and over etching processing step, the concrete steps of each etching technics and technological parameter with describe substantially identical above, be not described in detail in this.It should be noted that in the present embodiment, namely the target depth of high aspect ratio structure is equal to the thickness of the second Semiconductor substrate till being the oxide layer 101 arriving SOI substrate.Concrete, stop when main etching processing step stops at the top position of (i.e. oxide layer 101 upper surface) bottom the second Semiconductor substrate 200, form the first etched hole limiting high aspect ratio structure body shape.Transition etching process along the first etched hole continue etching second Semiconductor substrate 200 to its bottom, stop at oxide layer and oxide layer 101 upper surface of expose portion, form the second etched hole that critical size is less.Oxide layer 101 herein as etching stop layer, and through the second semiconductor substrate materials of transition etching technics rear oxidation layer surface still residual fraction.Over etching processing step then etches the sidewall (comprising the second semiconductor substrate materials of oxide layer 101 remained on surface) of the second etched hole, finally etches the high aspect ratio structure running through the second Semiconductor substrate and consistent appearance.As shown in figure 4d, bottom high aspect ratio structure, sidewall has smooth pattern, can eliminate in prior art the generation of notching phenomenon when applying DRIE etching soi wafer.
Finally, in this high aspect ratio structure, fill spacer medium and form the isolation structure of the MEMS based on SOI technology.
embodiment 2
The present embodiment applies the fixed electrode of lithographic method formation based on the MEMS of SOI technology of high aspect ratio structure of the present invention.The present embodiment can combine with embodiment 1 or independently implement.
First, please refer to Fig. 5 a, provide the first Semiconductor substrate 100, this first Semiconductor substrate, as base substrate, it also forms layer of oxide layer 101.
Then, in the first Semiconductor substrate 100 and oxide layer 101, form groove 102, this groove is used as the MEMS cavity (cavity) of MEMS.
Then, please refer to Fig. 5 b, provide the second Semiconductor substrate 200 and by itself and the first Semiconductor substrate 100 tool reeded side bonding.Bonding technology is melting bonding or claims Si-Si bonding.The first Semiconductor substrate after bonding, oxide layer and the second Semiconductor substrate form the substrate of soi structure, and respectively as the top silicon layer of soi structure substrate, insulating barrier and bottom silicon layer.
Then, please refer to Fig. 5 c, in the second Semiconductor substrate 200, the position relative with MEMS cavity etches high aspect ratio structure 201, it comprises aforesaid main etching processing step, transition etching process and over etching processing step, the concrete steps of each etching technics and technological parameter with describe substantially identical above, be not described in detail in this.It should be noted that the target depth of high aspect ratio structure in the present embodiment is for till arrival MEMS cavity, i.e. the thickness of equivalent second Semiconductor substrate.Concrete, stop when main etching processing step is etched to the top position bottom the second Semiconductor substrate 200, form the first etched hole limiting high aspect ratio structure body shape.Transition etching process continues etching second Semiconductor substrate 200 to the second Semiconductor substrate bottom along the first etched hole is to be formed with MEMS cavity connects and critical size second etched hole less than the first etched hole.Over etching processing step then etches the sidewall of the second etched hole, and final formation runs through high aspect ratio structure, this high aspect ratio structure and the MEMS cavity connects of the second Semiconductor substrate and consistent appearance.Thus, the second semi-conducting material being formed with high aspect ratio structure can serve as the fixed electrode of the MEMS based on SOI technology.
In sum, the lithographic method of high aspect ratio structure provided by the invention, by between the main etching and over etching of routine, increase by a step transition etch step, wherein, stop when making main etching technique high aspect ratio structure is etched to target depth top position, carry out etching subsequently/deposition rate is than less transition etching technics, the lateral etching avoiding follow-up over etching technique to cause produces inside depression bottom high aspect ratio structure, improves device performance thus.
Although the present invention discloses as above with preferred embodiment; right described many embodiments are citing for convenience of explanation only; and be not used to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion with described in claims.
Claims (10)
1. a lithographic method for high aspect ratio structure, is characterized in that, it comprises the following steps:
Step S01, provides semi-conductive substrate;
Step S02, perform main etching technique, etch described Semiconductor substrate to stop to during the top position of target depth to form the first etched hole, this main etching technique comprises etch step and the deposition step of alternate cycles, and described first etched hole limits the body shape of high aspect ratio structure;
Step S03, perform transition etching technics, continue the described Semiconductor substrate of etching to described target depth to form the second etched hole that critical size is less than the first etched hole, this transition etching technics comprises etch step and the deposition step of alternate cycles, and wherein etching/the deposition rate of etch step and deposition step is than the etching/deposition rate ratio being less than etch step and deposition step in described main etching technique; And
Step S04, performs over etching technique, etches the sidewall of described second etched hole to form the high aspect ratio structure reaching described target depth in described Semiconductor substrate.
2. the lithographic method of high aspect ratio structure according to claim 1, is characterized in that, in step S02, described main etching technique etches the At The Height stopping of above described Semiconductor substrate to described target depth 2-3 μm.
3. the lithographic method of high aspect ratio structure according to claim 2, is characterized in that, is controlled the etching depth of described main etching technique in step S02 by endpoint Detection or process time.
4. the lithographic method of high aspect ratio structure according to claim 1, is characterized in that, is controlled the etching depth of described transition etching technics in step S03 by etching terminal detection technique or process time.
5. the lithographic method of high aspect ratio structure according to claim 1, is characterized in that, step S01 comprises and forms patterned mask layer on the semiconductor substrate; Described main etching technique, transition etching technics and over etching technique all with described patterned mask layer for etch mask performs etching technics.
6. the lithographic method of high aspect ratio structure according to claim 1, is characterized in that, the etching/deposition rate of described main etching technique is than being 1:1 ~ 2:1, and the etching/deposition rate ratio of described transition etching technics is less than or equal to 1:1.
7. the lithographic method of high aspect ratio structure according to claim 1, it is characterized in that, when carrying out described main etching technique, transition etching technics and over etching technique, the gas passing into treatment chamber comprises etching gas and deposition gases, and described etching gas is SF
6, described deposition gases is C
4f
8.
8. the lithographic method of high aspect ratio structure according to claim 7, is characterized in that, the pressure of described main etching technique, transition etching technics and treatment chamber described in over etching technique, temperature, gas flow rate are all identical with radio frequency source power; Wherein the flow velocity of etching gas is 100 ~ 2000sccm, the flow velocity of deposition gases is 100 ~ 2000sccm, the pressure limit for the treatment of chamber is 40 ~ 120 millitorrs, and the power of source radio frequency source is 1500 ~ 3000 watts, and the power of biased radio frequency source exports in a pulsed fashion and is greater than 300 watts.
9. a manufacture method for MEMS, is characterized in that, comprises the following steps:
One base substrate is provided, this base substrate deposits oxide layer;
There is provided semi-conductive substrate and by described base substrate and described Semiconductor substrate bonding;
Perform main etching technique, etch described Semiconductor substrate to stop to during top position bottom it to form the first etched hole, this main etching technique comprises etch step and the deposition step of alternate cycles, and described first etched hole limits the body shape of high aspect ratio structure;
Perform transition etching technics, continue the described Semiconductor substrate of etching until expose described oxide layer surface to form the second etched hole that critical size is less than described first etched hole, this transition etching technics comprises etch step and the deposition step of alternate cycles, and wherein etching/the deposition rate of etch step and deposition step is than the etching/deposition rate ratio being less than etch step and deposition step in described main etching technique; And
Perform over etching technique, etch the sidewall of described second etched hole to form the high aspect ratio structure running through described Semiconductor substrate.
10. a manufacture method for MEMS, is characterized in that, comprises the following steps:
One base substrate is provided, this base substrate is formed an oxide layer;
MEMS cavity is formed in described base substrate and oxide layer;
There is provided semi-conductive substrate and by described base substrate and described Semiconductor substrate bonding;
Perform main etching technique, etch described Semiconductor substrate to stop to during top position bottom it to form the first etched hole, this main etching technique comprises etch step and the deposition step of alternate cycles, and described first etched hole limits the body shape of high aspect ratio structure;
Perform transition etching technics, continue the described Semiconductor substrate of etching to bottom it to be formed and described MEMS cavity connects and critical size are less than the second etched hole of described first etched hole, this transition etching technics comprises etch step and the deposition step of alternate cycles, and wherein etching/the deposition rate of etch step and deposition step is than the etching/deposition rate ratio being less than etch step and deposition step in described main etching technique; And
Perform over etching technique, the sidewall etching described second etched hole with formed run through described Semiconductor substrate and with the high aspect ratio structure of described MEMS cavity connects.
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| CN111252730A (en) * | 2020-01-22 | 2020-06-09 | 成都工业学院 | Preparation method of asymmetric semiconductor structure |
| CN113200511A (en) * | 2021-04-06 | 2021-08-03 | 杭州士兰集昕微电子有限公司 | Manufacturing method of back cavity of micro-electromechanical sensor |
| CN113745101A (en) * | 2020-05-29 | 2021-12-03 | 江苏鲁汶仪器有限公司 | Method and machine table for etching high-aspect-ratio device |
| CN114300413A (en) * | 2021-12-02 | 2022-04-08 | 北京北方华创微电子装备有限公司 | Processing method of semiconductor packaging structure and semiconductor packaging structure |
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| TWI313040B (en) * | 2003-02-20 | 2009-08-01 | Taiwan Semiconductor Mfg | Etching method for forming deep trench. |
| TWI255502B (en) * | 2005-01-19 | 2006-05-21 | Promos Technologies Inc | Method for preparing structure with high aspect ratio |
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| CN101652841A (en) * | 2007-04-11 | 2010-02-17 | 株式会社爱发科 | Dry etching method |
| CN103262207A (en) * | 2010-06-22 | 2013-08-21 | Vtt技术研究中心 | Multi-layer substrate structure and manufacturing method for the same |
| CN103594361A (en) * | 2012-08-13 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor structure |
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| CN110890277A (en) * | 2018-09-07 | 2020-03-17 | 无锡华润上华科技有限公司 | Preparation method of groove type metal oxide semiconductor Schottky barrier transistor |
| CN110890277B (en) * | 2018-09-07 | 2022-05-10 | 无锡华润上华科技有限公司 | Preparation method of groove type metal oxide semiconductor Schottky barrier transistor |
| CN111252730A (en) * | 2020-01-22 | 2020-06-09 | 成都工业学院 | Preparation method of asymmetric semiconductor structure |
| CN113745101A (en) * | 2020-05-29 | 2021-12-03 | 江苏鲁汶仪器有限公司 | Method and machine table for etching high-aspect-ratio device |
| CN113200511A (en) * | 2021-04-06 | 2021-08-03 | 杭州士兰集昕微电子有限公司 | Manufacturing method of back cavity of micro-electromechanical sensor |
| CN113200511B (en) * | 2021-04-06 | 2024-08-16 | 杭州士兰集昕微电子有限公司 | Method for manufacturing back cavity of micro-electromechanical sensor |
| CN114300413A (en) * | 2021-12-02 | 2022-04-08 | 北京北方华创微电子装备有限公司 | Processing method of semiconductor packaging structure and semiconductor packaging structure |
Also Published As
| Publication number | Publication date |
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| TW201604993A (en) | 2016-02-01 |
| TWI560807B (en) | 2016-12-01 |
| CN105448697B (en) | 2018-05-01 |
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