TW531833B - Manufacturing method for shallow trench isolation with high aspect ratio - Google Patents

Abstract

The present invention provides a manufacturing method for shallow trench isolation with high aspect ratio, which repetitively conducts twice the method of high density plasma chemical vapor deposition oxide/spin-on glass layer/thermal annealing/wet etching, so as to improve the void problems in the shallow trench isolation caused by difficult deposition of shallow trench with high aspect ratio.

Description

531833 V. Description of the invention (1) Field of the invention The present invention relates to the manufacturing technology of integrated circuits (ICs), in particular to a method for forming a shallow trench isolation (STI) 'Suitable for filling insulating trenches and other insulating materials into shallow trenches with high aspect ratios to form shallow trench isolations that are void-free. Description of related technologies

The manufacturing method of shallow trench spacers is generally to selectively etch the semiconductor substrate to form shallow trenches, and then use chemical vapor deposition (CVD) for the insulating material, such as atmospheric pressure chemical vapor deposition ( atmospheric pressure chemical vapor deposition (APCVD) or sub-atmospheric pressure chemical vapor deposition (SACVD) or high density plasma chemical vapor deposition (HDP-CVD) Materials such as silicon dioxide are filled into the shallow trenches, and then chemical mechanical polishing (CMP) is used to planarize the above dioxide dioxide materials, leaving shallow trench spacers.

However, with the development of integrated circuit technology, the size of shallow trench spacers, which are used as isolation regions between active components, has been reduced to 0 · n # m or 0 · 1 1 // 'shallow trenches below m The aspect ratio (ie depth / width) is even as high as 4 or more. 'Even if a high-density plasma chemical vapor deposition method with better trench filling capability is used, it is still unavoidable to generate holes (v. )or

0548-7289TWF; 90050; Jessica.ptd Page 4 531833 V. Description of the invention (2) is the seam (sam), the above hole — & VI-, the conductive second surface of the semiconductor substrate may cause subsequent deposition in Ke, This leads to an improper short circuit between the components. The summary and purpose of the invention is in view of this. The purpose of the invention is to provide a shallow trench spacer with a high aspect ratio (aspect rati0). In addition to the holes in the shallow trench spacer, the interfering substances derived from the holes are improved. ί ΐ i i ', the present invention provides a shallow trench with a high aspect ratio, which is suitable for forming a semiconductor substrate with an etched hard mask] 丄 The above manufacturing method includes the following steps: (a) using the above etched hard The mask ^ is used to shield the dome, and the semiconductor substrate described above is formed into a shallow trench; (w high-density electrical chemical vapor deposition is used to open the shallow trench: the first oxide layer at the bottom; (C) using The spin coating method is used to comprehensively apply a glass layer on the surface of the above-mentioned first oxide layer to serve as the first silver engraving buffer: '(d) apply the seat to the engraving step to remove the first layer above the hard cover. A glass] and a first oxide layer to form a bottom in the shallow trench, and a high-density electrical chemical vapor deposition method is used to form a second oxide layer on the top: a recess; (f) using Spin coating method comprehensive coating — ί 二 (= 于 Λ 述, second oxidation The surface "" is used as a second contact buffer (g) the target squatter etch step to remove the above-mentioned hardened layer on the hard mask; (h) the use of a high-density electrochemical polymerized gas = product method to form a second gasified layer ; ⑴Use chemical mechanical polishing method to flat

^ 1833 V. Description of the Invention— ^ 7-~ — Tu Yue 4 ~ the third oxide layer described above; and (j) removing the etching hard mask. In addition, in the method for manufacturing the shallow trench spacer with high aspect ratio as described above, the carved hard mask layer is made of a pad oxidized reed stone material with a thickness of 80 ~ 150 angstroms at the bottom (50 ~ 1〇 〇〇Angle) composition. In other words, in the method for manufacturing the above-mentioned shallow trench spacer with high aspect ratio, step V (3) is performed by a reactive ion etching method. In addition, in the above method of manufacturing the shallow trench spacer with a high aspect ratio, the depth / width m ruler / approximately less than 0 · η ", or even the shallow trench of the aforementioned shallow trench is the first of step (b). The thickness of the oxide layer filled in the above-mentioned 'repeated grooves is about 400 to 50 0 angstroms. Medium =', the method of manufacturing the above-mentioned shallow trench spacers with the high aspect ratio, the first glass substrate and the ^ = substrate, respectively. It includes a tempering step to densify the upper glass layer and the above-mentioned second glass layer. + T ί 1 The liquid of the manufacturing method of the shallow trench spacer with a high aspect ratio is performed, and the gas solution or the buffer oxidation is engraved. ^ Asian, among which the etching selection ratio of the first (two) 的 © / 筮. Layers is about 4 to 5. ', a) glass layer / younger-(two) in oxidation, when ^ 述 describes the shallow aspect ratio The second and third oxygen-cut layers of the method for making trench spacers are the two oxygen-cut layers. A brief description of the drawings Figures 1 to 8 are cross-sectional views of the process of a trench spacer according to the present invention. . &Quot; Steam is also deeper than X shallow groove

531833

Explanation of symbols 100 ~, conductor base; 丨 〇2 ~ pad oxide layer; 104 ~ silicon nitride material; HM ~ etch hard cover curtain sound 106 ~ shallow trench with high aspect ratio; Zhuo Shield 108, 114, 120 to high-density plasma oxide layer; 116 to spin-coated glass layer; B to the bottom of the shallow trench; 11 2, 11 8 to the concave recess at the bottom; STI to the shallow trench spacer.

Embodiment ": A cross-sectional view of a shallow trench spacer with a high aspect ratio as shown in Figs. 1 to 8 is used below to illustrate a preferred embodiment of the present invention. First, please refer to Fig. 1, in A single-crystal silicon semiconductor substrate 100 has a pad oxide layer 102 having a thickness of about ⑽ ⑽ by a thermal oxidation method, and then a low pressure chemical vapor dep. siti〇n;

LfCVD) ^ Under a ring containing dichlorosilane (SiH2Cl2) and ammonia (n%), a layer of nitride nitride having a thickness of, for example, 5000-1000 Angstroms is formed, and The photoresist is coated, exposed, developed, and baked to form a photoresist pattern on the surface of the nitride layer (not shown), and then use the photoresist pattern as a mask to etch the silicon nitride. Layer and pad oxide layer until the surface of the semiconductor substrate 100 is exposed, at this time, an etched hard mask curtain made of silicon nitride material 104 and pad oxide layer 102 is left. Then ’using the etched hard mask HM as a shield, and using

531833 V. Description of the invention (5) Reactive ion etching method is used to etch the above-mentioned semiconductor substrate not covered by the hard mask HM to form a size less than about 0 · 1 1 // m (1 1 00 Angstroms) and a depth of 4 5 The shallow trench 1 0 6 of 0 0 angstrom, that is, the depth-to-width ratio of the shallow trench 1 0 6 is greater than 4. Next, referring to FIG. 2, using high density plasma-chemi cal vapor deposition (HDP-CVD), for example, tetra-ethyl-ortho- silicate; TEOS) and ozone 'to form the oxide layer 10 filled in the bottom B of the shallow trench 106, and the depth of the filling is about 400 ~ 500 Angstroms.

Then, 'refer to FIG. 3', a spin-on-glass (SOG) 110 is completely coated on the oxide layer 108 by using a spin coating method (s ρ 丨 nc 〇ating), Taking it as a first etching buffered layer, since the spin-coating glass layer 110 has a good trench filling ability, it can fill the uneven surface of the oxide layer 08. Next, a tempering step (annealing KlO ~ 25 minutes) is performed by a thermal process (250 ~ 400 ° C) to increase the density of the spin-coated glass layer 11〇.

Secondly, please refer to FIG. 4, using a dilute HF solution or a buffered oxide etching solution (BOE) as an etchant, and then perform a wet etching step to remove the above the hard mask HM. The glass layer 110 and the oxide layer 106 are spin-coated to form a tapered recess 112 at the bottom of the shallow trench 106. At this time, the etching selection ratio of the spin-coated glass layer n0 to the oxide layer 106 is approximately 1200 Å. Between 4 and 5. Next, please refer to Figure 5 and use the high-density plasma chemical gas again.

531833

ί 目 ί = α (ΗΙ) Ρ CVD) 'in the presence of, for example, tetraethyl oxalate (te0s) and: milk' to form an oxide layer 114 filling the above-mentioned recess 112, and filling The depth is about 400 ~ 500 Angstroms. Then, referring to FIG. 6, the spin coating method is once again used to comprehensively coat the surface of the spin-on-glass layer (S0G) 116 on the oxide layer 114 as the first etching buffer layer ( etching buffered layer), because the glass layer 116 is spin-coated to fill the uneven surface of the oxide layer 114 described above. Next, the heat treatment plant (annealing) (25 to 400 ° C) (10 to 25 *) is performed to increase the density of the spin-coated glass layer 116. Secondly, please refer to FIG. 7, and use the dilute HF solution or buffered oxide etching solution (BOE) as the etching JW] (etchant), and then perform the engraving step. The spin-coated glass layer 116 and the oxide layer 114 above the hard mask HM are removed to form a concave recess at the bottom of the surface of the oxide layer 114 at this time. The spin-coated glass layer 6 and the oxide layer 114 at this time The etching selection ratio is between about 4 ~ 5. Then, the second step is to form an oxide layer 1 2 0 filled with the above-mentioned recesses 8 by using a high-density plasma chemical vapor deposition method. Finally, please refer to FIG. 8, and use chemical mechanical polishing (CMP) to planarize the oxide layer 12 until the surface of the hard mask HM is exited. Used as a polishing stop layer. Next, the silicon nitride material 104 is sequentially removed by using an acid solution, and then the hafnium oxide layer 102 'is washed with a dilute hydrofluoric acid solution to expose the surface of the semiconductor substrate 100, and is left.

0548-7289TWF; 90050; Jessica.ptd page 9 531833 V. Description of the invention (7) Shallow trench spacer STI composed of high-density plasma-oxide layer. The embodiment of the present invention repeats the method of “high-density plasma chemical vapor deposition oxide layer / spin-coated glass layer / thermal tempering / wet etching” to change the ice width ratio and the shallow trench is not easy to be deposited. The problem of the holes in the shallow trench spacers, however, when the shallow trench aspect ratio is required, ^-"high-density plasma chemical vapor deposition oxide layer / spin-on glass / etched ". Limitation: 5 ^ 1 month has been disclosed as above with better examples, but it is not used as a god, without departing from the essence of the present invention. Applicants who attach the patent = the scope of protection of the present invention

0548-7289TWF; 90050; Jessica.ptd 10th stomach

Claims (1)

531833 VI. Application Patent Scope 1. A method for manufacturing a shallow trench spacer with a high aspect ratio, which is suitable for forming a semiconductor substrate with an etched hard mask. The above manufacturing method includes the following steps: (a) using the above etched hard mask Is a shield, and the semiconductor substrate is etched to form a shallow trench, (b) a high-density plasma chemical vapor deposition method is used to form a first oxide layer filling the bottom of the shallow trench; The coating method comprehensively applies a first glass layer on the surface of the first oxide layer as the first buffer layer; (d) performing a wet etching step to remove the first glass layer above the hard mask. And a first oxide layer to form a recess with a tapered bottom in the shallow trench; (e) using a high-density plasma chemical vapor deposition method to form a second oxide layer filling the recess; (f ) Comprehensively coating a second glass layer on the surface of the second oxide layer by using a spin coating method as a second etching buffer layer; (g) performing a wet etching step to remove the first layer above the hard mask. Two glass layers and the second An oxide layer; (h) using a high-density plasma chemical vapor deposition method to form a third oxide layer; (i) using a chemical mechanical polishing method to planarize the third oxide layer; and (j) removing the money and hard The curtain. 2. Shallow trench spacer with high aspect ratio as described in item 1 of patent application 0548-7289TWF; 90050; Jessica.ptd Page 11 VI. Scope of patent application ^ ~ ___ ____ · _ Method of making an object oxide layer 其中 where the above-mentioned etching hard cover curtain layer is composed of a pad 3 at the bottom. Shen :: Material composition. The producer of the object is separated by a shallow trench with a high aspect ratio as described in item 1 of the profit removal range. 4 'where step (a) is completed by reactive ion etching method 'Where the size of the shallow trench is less than 0 · 11 # m. Production of free objects. Shallow trenches with high aspect ratio as described in item 1 of the profit range. 6. As mentioned above, the shallow trench has an aspect ratio greater than 4. The producer of the object, and the shallow trench with the aspect ratio of 咼 described in the item 5 of the range, such as: 、, spoon is 400 ~ 500 angstroms. The method of separating the object from the shallow trench with a high aspect ratio as described in the first item of the two patents' method, wherein the steps ⑹ and ⑴, respectively, further include — ΓΓ: densification of the above-mentioned Glass layer. Isolation ":: Li, the shallow trench with a high aspect ratio as described in item 1 ^ ^ ^ ^ ^ / ', the above wet I engraving step is the use of diluted hydrofluoric acid shallow trench FΪ' Wherein the first oxide layer of step (b) is filled with the above-mentioned W conductivity of about 400 ~ H ... six τ the above-mentioned wet etching ... bath 9 or & — Declaring the method of making shallow trenches with a high aspect ratio as described in item 8 of the patent scope, wherein the above-mentioned first glass layer / first oxide layer etch selection ratio is about 4 to 5. 1．If applied The manufacturing method of the shallow trench sample P with high aspect ratio as described in item 8 of the patent scope, wherein the etching selection ratio of the second glass layer / second oxide layer is about 4 to 5. Page 12 0548-7289TWF; 90050 Jessica.ptd 531833 6. The scope of patent application η. For example, the scope of patent application '' S ': the method for making objects in the shallow trench layer of the first aspect ratio in the above is a silicon dioxide layer. Oxidation, 12. As described in the method of making patents on the scope of patent application, the method for making silicon ions, which includes the following steps: The method of removing the silver-engraved hard military curtain; removing the silicon nitride material with a phosphoric acid solution, and removing the pad oxide layer with dilute hydrofluoric acid. 1 3 · High ion content as described in item 2 of the scope of patent application The manufacturing method, wherein the above silicon nitride material is strict = between shallow grooves between 50 0 and 1 000 angstroms. The degree of ingenuity and the degree is approximately 14. As described in item 2 of the scope of patent application, The manufacturing method, wherein the sound groove of the above-mentioned pad oxide layer is separated between 80 and 150 angstroms. 0548-7289TWF; 90050; Jessica.ptd p. 13