CN103035511B - Make the method for the zero layer photo-etching mark of the high tension apparatus of without hindrance barrier - Google Patents
Make the method for the zero layer photo-etching mark of the high tension apparatus of without hindrance barrier Download PDFInfo
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Abstract
The invention discloses a kind of method making the zero layer photo-etching mark of the high tension apparatus of without hindrance barrier, comprise the following steps: the first step, etch zero layer photo-etching mark groove; Second step, deposit one deck dielectric layer, and remove zero layer photo-etching mark groove with the dielectric layer of exterior domain; 3rd step, etches deep trench; 4th step, on a silicon substrate selective growth one deck epitaxial loayer; 5th step, removes the transoid epitaxial material on a silicon substrate of deposit in epitaxial process; 6th step, etches away the dielectric layer in zero layer photo-etching mark groove by the method for wet etching, leaves zero layer photo-etching mark figure.The present invention can form the photo-etching mark of easily identification on the high tension apparatus of without hindrance barrier, facilitates the aligning of subsequent film, can ensure the smooth and easy of technological process, improves the yield of product.
Description
Technical field
The present invention relates to a kind of semiconductor technology method, be specifically related to a kind of method making the zero layer photo-etching mark of the high pressure resistant device of without hindrance barrier.
Background technology
Now semiconductor power application in there is a kind of novel semiconductor device, this semiconductor device can either improve puncture voltage can reduce again conducting state under resistance.It has the PN post layer be alternately arranged, and plays the effect of the super junction (super junction) as drift layer.
The method of etching and filling deep trench in super junction MOS transistor manufacture process, grow one deck n-type epitaxial loayer (monocrystalline silicon) on n+ type silicon substrate, then one or more layers oxide-film of deposit or nitride film on this epitaxial loayer, etch deep trench again, and carry out selective epitaxial with p-type monocrystalline silicon and fill this deep trench, finally use cmp (CMP) technique to carry out surface planarisation.Now this deep groove structure is as p-type semiconductor post, and the both sides of this deep groove structure, as n-type semiconductor post, namely obtain the p-type and n-type semiconductor post that are longitudinally alternately arranged.
In said method in monocrystalline silicon selective epitaxial process, need to improve fillibility and the etching gas introduced can cause the lateral etching of the monocrystalline substrate top oxide layer exposed of deep trench both sides and produce undercut, silicon substrate now in otch exposes, subsequently again can fill by silicon epitaxy.Because this part epitaxial loayer is present in oxide-film lower surface, and silicon substrate forms one, and horizontal direction extends along the part of groove dorsad, is difficult to remove in planarization process.Remove technique at subsequent oxidation film, if the epitaxial loayer be filled in inside this part otch is not removed, silicon ridge will be formed in the both sides of groove, affect some electric property of device.
If carry out photoetching and the etching of deep trench by the method on barrier layer, cannot guarantee that silicon ridge can be removed, the assembly of one or more layers oxide layer or nitration case therefore cannot be used to be used as the barrier layer etched.
Zero layer photo-etching mark is generally adopt first to expose, develop, and then produce through the method for over etching, its surfacial pattern region must keep certain offset (step height), and this mark normally could work on mask aligner.And high pressure resistant device is owing to being directly carry out deep plough groove etched on a silicon substrate and form figure, and then fill deep trench by epitaxy technology, due to the existence of barrier without hindrance in zero layer cursor graphic, can cause while filling deep trench, epitaxial loayer also can be filled in the figure of zero layer photo-etching mark, and deep trench filler and silicon substrate are all monocrystalline, in follow-up cmp flow process, owing to causing offset too little without high selectivity, this photo-etching mark is beyond recognition, cause in follow-up technique, using this zero layer figure, for the aligning of subsequent film brings difficulty, affect the smooth and easy of technological process, and then the yield of product can be affected.
As shown in Figure 1, zero layer photo-etching mark fill by epitaxial loayer (EPI), be beyond recognition.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of method making the zero layer photo-etching mark of the high tension apparatus of without hindrance barrier, and it can form the zero layer photo-etching mark of easily identification.
For solving the problems of the technologies described above, the technical solution that the present invention makes the method for the zero layer photo-etching mark of the high tension apparatus of without hindrance barrier is:
Comprise the following steps:
The first step, forms one deck photoresistance on a silicon substrate, and carries out exposure imaging on a silicon substrate; Then zero layer photo-etching mark groove is etched on a silicon substrate; The degree of depth of zero layer photo-etching mark groove is 0.1 ~ 10 micron, and width is 1 ~ 10 micron, and length is 1 ~ 10 micron; The pattern of groove is vertical or tilts;
Wherein zero layer photo-etching mark groove is preferably dimensioned to be: the degree of depth 0.5 ~ 5 micron, width 1 ~ 6 micron, length 1 ~ 10 micron.
Second step, removes the photoresistance on silicon substrate; Then deposit a layer thickness is on a silicon substrate the dielectric layer of 0.1 ~ 10 micron; Zero layer photo-etching mark groove is removed with the dielectric layer of exterior domain afterwards by cmp; Described dielectric layer is oxide-film or nitride film;
Its dielectric layer by reduce pressure or aumospheric pressure cvd method generate; Dielectric layer fills up zero layer photo-etching mark groove, or covers the Partial Height of zero layer photo-etching mark groove, does not namely fill up zero layer photo-etching mark groove.
The thickness of its dielectric layer is preferably 0.1 ~ 1 micron.
The lapping liquid that cmp uses is for comprising silicon dioxide and containing akaline liquid stabilizer hydroxy.
3rd step, forms one deck photoresistance on a silicon substrate, etches deep trench by the method for dry etching; The degree of depth of deep trench is 10 ~ 100 microns, and width is 1 ~ 10 micron; Then the photoresistance on silicon substrate is removed;
Wherein deep trench is preferably dimensioned to be: the degree of depth 30 ~ 100 microns, width 1 ~ 5 micron.
4th step, on a silicon substrate selective growth one deck epitaxial loayer, make epitaxial loayer deep trench be filled up; The deposition thickness of epitaxial loayer is 0.5 ~ 5 micron;
The deposition thickness of its epitaxial layers is preferably 0.5 ~ 2.5 micron.
The method of selective growth epitaxial loayer adopts rpcvd method, and uses etching property gas chlorination hydrogen to carry out selective growth at silicon chip surface.
5th step, removes the transoid epitaxial material on a silicon substrate of deposit in epitaxial process by the mode of cmp;
6th step, etches away the dielectric layer in zero layer photo-etching mark groove by the method for wet etching, leaves zero layer photo-etching mark figure.
In wet etching process, for oxide film dielectric layer, the etching liquid used is buffered hydrofluoric acid, and the concentration of buffered hydrofluoric acid liquid is 0.01 ~ 20%, and etch amount is 0.1 ~ 1 micron; For nitride film dielectric layer, the etching liquid used is phosphoric acid solution, and the temperature of solution is 150 ~ 200 DEG C, and the concentration of solution is 20 ~ 80%, and etch amount is 0.1 ~ 1 micron.
The technique effect that the present invention can reach is:
The present invention first forms the groove of zero layer photo-etching mark, and this groove can be pattern that is vertical or that tilt; Rear deposit one deck dielectric layer, this dielectric layer can use oxide-film or nitride film; Remove completely with the dielectric layer of cmp by all the other regions except the dielectric layer in cursor subsequently; And then carry out the flow process of the etching of follow-up deep trench, selective epitaxial precipitation and cmp; Finally the dielectric layer in cursor is removed, leave cursor graphic.
The present invention can form the photo-etching mark of easily identification on the high tension apparatus of without hindrance barrier, facilitates the aligning of subsequent film, can ensure the smooth and easy of technological process, improves the yield of product.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the schematic diagram of the zero layer photo-etching mark adopting prior art to be formed;
Fig. 2 to Figure 12 is concrete technology step schematic diagram;
Figure 13 is the schematic diagram of the zero layer photo-etching mark that method that the present invention makes the zero layer photo-etching mark of the high tension apparatus of without hindrance barrier is formed.
Description of reference numerals in figure:
1 is silicon substrate, and 2 is photoresistance (PR),
3 is dielectric layer, and 4 is selective epitaxial precipitation layer.
Embodiment
The present invention makes the method for the zero layer photo-etching mark of the high tension apparatus of without hindrance barrier, comprises the following steps:
The first step, silicon substrate 1 as shown in Figure 2 forms one deck photoresistance 2, and carry out exposure imaging on silicon substrate 1, as shown in Figure 3; Then on silicon substrate 1, zero layer photo-etching mark groove is etched, as shown in Figure 4; The degree of depth of zero layer photo-etching mark groove is 0.1 ~ 10 micron, and width is 1 ~ 10 micron, and length is 1 ~ 10 micron; The pattern of groove is vertical or tilts all can;
Zero layer photo-etching mark groove is preferably dimensioned to be: the degree of depth 0.5 ~ 5 micron, width 1 ~ 6 micron, length 1 ~ 10 micron;
Second step, removes the photoresistance 2 on silicon substrate 1, as shown in Figure 5; Then deposit one deck dielectric layer 3 on silicon substrate 1, as shown in Figure 6; The thickness of dielectric layer 3 is 0.1 ~ 10 micron, dielectric layer 3 can by reduce pressure or aumospheric pressure cvd method generate; Dielectric layer can be oxide-film or nitride film; This dielectric layer can fill up zero layer photo-etching mark groove, also can not fill up zero layer photo-etching mark groove;
The thickness of dielectric layer 3 is preferably 0.1 ~ 1 micron,
Zero layer photo-etching mark groove is removed with the dielectric layer 3 of exterior domain afterwards, as shown in Figure 7 by cmp;
The lapping liquid that cmp uses is for comprising silicon dioxide and containing akaline liquid stabilizer hydroxy, residual without dielectric layer 3 to ensure the region except zero layer photo-etching mark groove;
3rd step, as shown in Figure 8, silicon substrate 1 forms one deck photoresistance 2, etches deep trench by the method for dry etching; The degree of depth of deep trench is 10 ~ 100 microns, and width is 1 ~ 10 micron;
Deep trench is preferably dimensioned to be: the degree of depth 30 ~ 100 microns, width 1 ~ 5 micron;
Then the photoresistance 2 on silicon substrate 1 is removed, as shown in Figure 9;
4th step, selective growth one deck epitaxial loayer 4 on silicon substrate 1, makes epitaxial loayer 4 deep trench be filled up, as shown in Figure 10; The deposition thickness of this epitaxial loayer 4 is 0.5 ~ 5 micron;
The deposition thickness of epitaxial loayer 4 is preferably 0.5 ~ 2.5 micron;
The method of selective growth epitaxial loayer 4 adopts rpcvd method, and uses etching property gas chlorination hydrogen to carry out selective growth at silicon chip surface, to prevent from sealing too early in deep trench in growth course, has avoided hole to produce;
5th step, removes the transoid epitaxial material be deposited in epitaxial process on silicon substrate 1 by the mode of cmp, by its planarization, forms the PN post layer be alternately arranged, as shown in figure 11;
The lapping liquid used in chemical mechanical planarization process has the lapping liquid of high selectivity for monocrystalline silicon relative medium layer 3, to guarantee that the transoid epitaxial loayer on silicon substrate 1 top is removed clean, dielectric layer 3 free of losses meanwhile in zero layer photo-etching mark groove; The method of fixing milling time can be used;
6th step, etches away the dielectric layer 3 in zero layer photo-etching mark groove by the method for wet etching, leaves zero layer photo-etching mark figure, as shown in figure 12;
The liquid used in wet etching process is the liquid relative to oxide film dielectric layer with high selectivity, and described etching liquid comprises dilute hydrofluoric acid, buffered hydrofluoric acid etc. have etching property liquid to oxide-film;
The concentration of buffered hydrofluoric acid liquid is 0.01 ~ 20%, and etch amount is 0.1 ~ 1 micron;
Or hot phosphoric acid solution etc. has the solution of high selectivity relative to nitride film dielectric layer, its solution concentration is 20 ~ 80%, and etch amount is 0.1 ~ 1 micron.
Zero layer photo-etching mark figure as shown in figure 13 for adopting the present invention to be formed, can use.
Claims (10)
1. make a method for the zero layer photo-etching mark of the high tension apparatus of without hindrance barrier, it is characterized in that, comprise the following steps:
The first step, forms one deck photoresistance on a silicon substrate, and carries out exposure imaging on a silicon substrate; Then zero layer photo-etching mark groove is etched on a silicon substrate; The degree of depth of zero layer photo-etching mark groove is 0.1 ~ 10 micron, and width is 1 ~ 10 micron, and length is 1 ~ 10 micron; The pattern of groove is vertical or tilts;
Second step, removes the photoresistance on silicon substrate; Then deposit a layer thickness is on a silicon substrate the dielectric layer of 0.1 ~ 10 micron; Zero layer photo-etching mark groove is removed with the dielectric layer of exterior domain afterwards by cmp; Described dielectric layer is oxide-film or nitride film;
3rd step, forms one deck photoresistance on a silicon substrate, etches deep trench by the method for dry etching; The degree of depth of deep trench is 10 ~ 100 microns, and width is 1 ~ 10 micron; Then the photoresistance on silicon substrate is removed;
4th step, on a silicon substrate selective growth one deck epitaxial loayer, make epitaxial loayer deep trench be filled up; The deposition thickness of epitaxial loayer is 0.5 ~ 5 micron;
5th step, removes the transoid epitaxial material on a silicon substrate of deposit in epitaxial process by the mode of cmp;
6th step, etches away the dielectric layer in zero layer photo-etching mark groove by the method for wet etching, leaves zero layer photo-etching mark figure.
2. the method for the zero layer photo-etching mark of the high tension apparatus of the without hindrance barrier of making according to claim 1, is characterized in that, in the described first step, zero layer photo-etching mark groove is of a size of: the degree of depth 0.5 ~ 5 micron, width 1 ~ 6 micron, length 1 ~ 10 micron.
3. the method for the zero layer photo-etching mark of the high tension apparatus of the without hindrance barrier of making according to claim 1, is characterized in that, the dielectric layer in described second step by reduce pressure or aumospheric pressure cvd method generate.
4. the method for the zero layer photo-etching mark of the high tension apparatus of the without hindrance barrier of making according to claim 1, is characterized in that, the dielectric layer in described second step fills up zero layer photo-etching mark groove, or covers the Partial Height of zero layer photo-etching mark groove.
5. the method for the zero layer photo-etching mark of the high tension apparatus of the without hindrance barrier of making according to claim 1, is characterized in that, the thickness of the dielectric layer in described second step is 0.1 ~ 1 micron.
6. the method for the zero layer photo-etching mark of the high tension apparatus of the without hindrance barrier of making according to claim 1, is characterized in that, the lapping liquid that described second step cmp uses is for comprising silicon dioxide and containing akaline liquid stabilizer hydroxy.
7. the method for the zero layer photo-etching mark of the high tension apparatus of the without hindrance barrier of making according to claim 1, is characterized in that, in described 3rd step, deep trench is of a size of: the degree of depth 30 ~ 100 microns, width 1 ~ 5 micron.
8. the method for the zero layer photo-etching mark of the high tension apparatus of the without hindrance barrier of making according to claim 1, is characterized in that, the deposition thickness of described 4th step epitaxial layers is 0.5 ~ 2.5 micron.
9. the method for the zero layer photo-etching mark of the high tension apparatus of the without hindrance barrier of making according to claim 1, it is characterized in that, in described 4th step, the method for selective growth epitaxial loayer adopts rpcvd method, and uses etching property gas chlorination hydrogen to carry out selective growth at silicon chip surface.
10. the method for the zero layer photo-etching mark of the high tension apparatus of the without hindrance barrier of making according to claim 1, it is characterized in that, in the wet etching process of described 6th step, for oxide film dielectric layer, the etching liquid used is buffered hydrofluoric acid, the concentration of buffered hydrofluoric acid liquid is 0.01 ~ 20%, and etch amount is 0.1 ~ 1 micron; For nitride film dielectric layer, the etching liquid used is phosphoric acid solution, and the temperature of solution is 150 ~ 200 DEG C, and the concentration of solution is 20 ~ 80%, and etch amount is 0.1 ~ 1 micron.
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| CN104752323B (en) * | 2013-12-27 | 2018-03-20 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof |
| CN104952849B (en) * | 2014-03-31 | 2019-01-08 | 中芯国际集成电路制造(上海)有限公司 | The production method of align structures and through silicon via for through silicon via production |
| CN104409348B (en) * | 2014-11-10 | 2017-08-08 | 成都士兰半导体制造有限公司 | The preparation method of trench device |
| CN104882436B (en) * | 2015-03-31 | 2018-02-06 | 上海华虹宏力半导体制造有限公司 | Twice in epitaxy technique photoetching alignment mark preparation method |
| CN105789181B (en) * | 2016-01-29 | 2018-08-21 | 上海华虹宏力半导体制造有限公司 | A kind of reverse phase photoetching alignment mark and its production method |
| CN108063121A (en) * | 2016-11-08 | 2018-05-22 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method, electronic device |
| CN108127582B (en) * | 2017-12-13 | 2019-12-31 | 湖北鼎汇微电子材料有限公司 | Mold for preparing polishing layer and preparation method |
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| CN112563246B (en) * | 2020-12-18 | 2022-06-24 | 河源市众拓光电科技有限公司 | Photoetching overlay mark and preparation method thereof |
| CN112992773B (en) * | 2021-02-04 | 2022-09-20 | 华虹半导体(无锡)有限公司 | Alignment mark forming method for deep trench isolation and semiconductor device structure |
| CN113675174A (en) * | 2021-08-17 | 2021-11-19 | 青岛佳恩半导体科技有限公司 | Preparation method for improving Mark point morphology of power device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7338909B2 (en) * | 2004-06-18 | 2008-03-04 | Taiwan Semiconductor Manufacturing Co. Ltd. | Micro-etching method to replicate alignment marks for semiconductor wafer photolithography |
| CN101447452A (en) * | 2007-11-27 | 2009-06-03 | Oki半导体株式会社 | Method for manufacturing semiconductor device |
| CN101446768A (en) * | 2007-11-27 | 2009-06-03 | 中芯国际集成电路制造(上海)有限公司 | Zero layer alignment maker and preparation method |
-
2011
- 2011-10-09 CN CN201110301468.0A patent/CN103035511B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7338909B2 (en) * | 2004-06-18 | 2008-03-04 | Taiwan Semiconductor Manufacturing Co. Ltd. | Micro-etching method to replicate alignment marks for semiconductor wafer photolithography |
| CN101447452A (en) * | 2007-11-27 | 2009-06-03 | Oki半导体株式会社 | Method for manufacturing semiconductor device |
| CN101446768A (en) * | 2007-11-27 | 2009-06-03 | 中芯国际集成电路制造(上海)有限公司 | Zero layer alignment maker and preparation method |
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