CN104752323A - Semiconductor device and preparation method thereof - Google Patents
Semiconductor device and preparation method thereof Download PDFInfo
- Publication number
- CN104752323A CN104752323A CN201310743149.4A CN201310743149A CN104752323A CN 104752323 A CN104752323 A CN 104752323A CN 201310743149 A CN201310743149 A CN 201310743149A CN 104752323 A CN104752323 A CN 104752323A
- Authority
- CN
- China
- Prior art keywords
- layer
- hole
- interlayer dielectric
- silicon
- photo
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Manufacturing & Machinery (AREA)
Abstract
The invention relates to a semiconductor device and a preparation method thereof. The method comprises the steps of providing a semiconductor substrate, and forming an interlayer dielectric layer on the semiconductor substrate, wherein the interlayer dielectric layer is internally provided with a contact hole and a photoetching mark hole, and the photoetching mark hole is provided with a gap; depositing a sacrificial material layer so as to completely fill the gap; forming a protection layer on the interlayer dielectric layer and the sacrificial material layer; forming a silicon through hole in the semiconductor substrate and the interlayer dielectric layer; removing the protection layer so as to expose the sacrificial material layer; and removing the sacrificial material layer so as to expose the gap. According to the invention, a-C is used to act as the protection layer of CT in the silicon through hole preparation (TSV VIA middle) process, and compared with SIN, the a-C has a better step coverage ability and can be completely removed, thereby not affecting follow-up photoetching (M1photo) alignment for a first metal layer, and effectively solving a problem of OVL measurement.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of semiconductor device and preparation method thereof.
Background technology
At consumer electronics field, multifunctional equipment is more and more subject to liking of consumer, compared to the simple equipment of function, multifunctional equipment manufacturing process will be more complicated, such as need the chip of integrated multiple difference in functionality in circuit version, thus there is 3D integrated circuit (integrated circuit, IC) technology, 3D integrated circuit (integrated circuit, IC) a kind of system-level integrated morphology is defined as, multiple chip is stacking in vertical plane direction, thus saving space, multiple pin can be drawn as required in the marginal portion of each chip, utilize these pins as required, by need be connected to each other chip interconnected by metal wire, but still there is a lot of deficiency in aforesaid way, such as stacked chips quantity is more, and the annexation more complicated between chip, so will need to utilize many metal line, final wire laying mode is more chaotic, and volume can be caused to increase.
Therefore, at present at described 3D integrated circuit (integrated circuit, IC) silicon through hole (Through Silicon Via is mostly adopted in technology, TSV), silicon through hole is a kind of perpendicular interconnection penetrating Silicon Wafer or chip, TSV can storehouse multi-plate chip, (processing procedure can be divided into again first boring and rear boring two kinds to get out duck eye at chip, Via Fist, Via Last), enter metal from underfill, Silicon Wafer is holed (via) with etching or laser mode, then with electric conducting material as the materials such as copper, polysilicon, tungsten fill up.Thus it is interconnected to realize between different silicon chip.
3D IC is by the processor wafer of former naked brilliant size, programmable logic lock (FPGA) wafer, memory chip, RF chip (RF) or optoelectronic wafers, directly superimposed after thinning, and connects through TSV boring.At the three-dimensional composite technology of 3D IC, under the assistance of the key technology/encapsulation spare parts such as silicon through hole (TSV), intermediate plate (Interposer), in limited areal, carry out the superposition of maximum wafer and integrate, reduce SoC chip area/encapsulation volume further and promote wafer and link up efficiency.
At present; in the process of the combination of two wafers; namely after completing FEOL; before BEOL, be generally after formation contact hole (Contact) technique, embed a kind of technology of TSV through hole; so in TSV through hole technical process; the protection of CT level is particularly important, by deposition SiN as the protective layer of contact hole (CT), then carries out TSV technique.
Particularly as illustrated by figs. 1 a-1f, first with reference to Fig. 1 a, Semiconductor substrate 101 is provided, described Semiconductor substrate 101 completes the various components and parts in front end of line, then interlevel dielectric deposition 102 on the semiconductor substrate, contact hole (contact) level is formed in described interlayer dielectric layer, wherein in contact hole (contact) level, contact hole mainly contains two kinds of patterns (pattern), wherein a class is contact hole 103 pattern, as the contact hole of interconnection, usually there is less size (being 0.24 in 0.18 processing procedure), another is as photo-etching mark pattern (photo mark) 104, usually there is larger size (being generally greater than 1um), CT hole as photo-etching mark is middle when filling metal can leave larger space 10.TSV technique is performed after the described contact hole of formation, with reference to Fig. 1 b, on described interlayer dielectric layer 102, on described contact hole 103 pattern, protective layer 105 is formed in photo-etching mark pattern (photo mark) 104, at present in semiconductor processing, usual use CVD deposits SiN as protective layer, method and cost are all comparatively ripe simple, also the protective layer of CT and the stop-layer of TSVCMP is usually used as in Cu-Cu combined process (TSV VIA middle) in wafer combines, but because (stepcoverage) ability filled by the poor step that has of described SiN, good filling cannot be formed in photo-etching mark pattern (photo mark) region, still there is larger space, interlayer dielectric layer 102 described in patterning forms silicon through hole groove, and as illustrated in figure 1 c, wherein said protective layer 105 forms good protection to described CT region, then depositing silicon through hole separator 106(TSV isolation), described silicon through hole separator 106 has good step and fills (step coverage) ability, therefore, space in described photo-etching mark bore region (CT photo mark) is completely filled, as shown in Figure 1 d, then filled conductive material in described silicon through hole groove, and be planarized to described protective layer 105, form the structure of silicon through hole, as shown in Fig. 1 e-1f, finally remove described protective layer 105, but silicon through hole absciss layer 106(oxide in photo-etching mark bore region (CT photo mark) after removing) residually still cannot to be removed, make follow-up the first metal layer photoetching (M1photo) processing procedure contraposition CT become difficulty, and be unfavorable for the measurement of aiming at (OVL).
Usually CVD is used to deposit SIN as protective layer in the prior art, method and cost are all comparatively ripe simple, also the protective layer of CT and the stop-layer of TSV planarization is usually used as in TSV VIA middle technique, but owing to there is great CD difference as the CT pattern of photo-etching mark (photo mark) with as the aperture of contact hole of interconnection in CT level, cause in the CT pattern of photo-etching mark (photo mark), to produce comparatively multimedium in TSV process to remain, this is as the inevitable problems faced of protective layer at TSV VIA Middle technique SIN, temporary transient without good scheme solution.
In addition; use SIN can be with as the protective layer of CT in TSV technical process and serve technological problems; follow-up M1 lithographic process photoetching (photo) cannot contraposition and aligning (OVL) cannot be measured, and how solving this problem, is the larger challenge that current TSV technique faces.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
The present invention, in order to overcome current existing problems, provides a kind of preparation method of semiconductor device, comprising:
There is provided Semiconductor substrate, be formed with interlayer dielectric layer on the semiconductor substrate, be formed with contact hole and photo-etching mark hole in described interlayer dielectric layer, described photo-etching mark hole has space;
Sacrificial material layer, to fill described space completely;
Described interlayer dielectric layer and described sacrificial material layer form protective layer;
Silicon through hole is formed in described Semiconductor substrate and described interlayer dielectric layer;
Remove described protective layer, to expose described sacrificial material layer;
Remove described sacrificial material layer, to expose described space.
As preferably, described sacrificial material layer selects amorphous carbon.
As preferably, the method for filling described space is:
In described interlayer dielectric layer and described space, deposit described sacrificial material layer, to cover described interlayer dielectric layer, and fill described space;
Perform planarisation step, to remove the described sacrificial material layer on described interlayer dielectric layer surface.
As preferably, the method forming described silicon through hole is:
Described protective layer is formed the mask layer of patterning;
With described mask layer for protective layer, described interlayer dielectric layer and described Semiconductor substrate described in mask etch, to form silicon through hole groove;
Remove described mask layer;
Separator is formed in described silicon through hole groove;
Select silicon through hole groove described in filled with conductive material;
Perform planarisation step, described electric conducting material is planarized to described protective layer, to form described silicon through hole.
As preferably, the method for filling described silicon through hole groove is:
Described separator forms diffusion impervious layer;
Described diffusion impervious layer is formed the Seed Layer of metal;
Select electrochemistry electric plating method plated metal to fill described silicon through hole groove.
As preferably, ashing method is selected to remove described sacrificial material layer.
As preferably, SiN layer selected by described protective layer;
Described interlayer dielectric layer selects oxide skin(coating).
As preferably, the method forming described contact hole and described photo-etching mark hole is:
Interlayer dielectric layer described in patterning, to form contact hole groove and photo-etching mark hole groove;
Deposits conductive material, to fill described contact hole groove completely, forms contact hole, is partially filled described photo-etching mark hole groove simultaneously, the sidewall of described photo-etching mark hole groove forms electric conducting material, to form the photo-etching mark hole that center has space.
Present invention also offers the semiconductor device that a kind of above-mentioned method prepares, described in described semiconductor device, the center in photo-etching mark hole has space.
The present invention proposes the protective layer using a-C as CT in silicon through hole preparation (TSV VIA middle) technique, a-C is as the good protective layer of one and sacrifice layer, the method that CVD can be used to deposit covers the surface of wafer, and compare SIN there is better Step Coverage ability, can to photo-etching mark hole 204(CT photo mark) cavity in region forms good filling, make silicon through hole medium (TSV isolation) that photo-etching mark hole 204(CT photo mark cannot be deposited on) region, so CT surface silicon through hole medium (TSV isolation) can be completely removed, thus do not affect the contraposition of follow-up the first metal layer photoetching (M1photo), efficiently solve OVL and measure problem.
In addition, a-C compares SIN, in CMP process and between silicon through hole medium (oxide), have higher Selection radio, can form better protection to CT.
In addition, a-C can remove by ashing (Asher) mode, and a-C compares SIN and more easily removes, clean and it is not easy to produce residue.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
The preparation process schematic diagram that Fig. 1 a-1g is the TSV of semiconductor device described in prior art;
Fig. 2 a-2h is the preparation process schematic diagram of the TSV of semiconductor device described in an embodiment of the present invention;
Fig. 3 is preparation technology's flow chart of the present invention one TSV of semiconductor device described in execution mode particularly.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed description is proposed, so that the preparation method of semiconductor device of the present invention to be described.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should give it is noted that term used here is only to describe specific embodiment, and be not intended to restricted root according to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative be also intended to comprise plural form.In addition, it is to be further understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.Should be understood that, providing these embodiments to be of the present inventionly disclose thorough and complete to make, and the design of these exemplary embodiments fully being conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region, and use the element that identical Reference numeral represents identical, thus will omit description of them.
The present invention, in order to solve Problems existing in current semiconductor device preparation process, provides a kind of new preparation method, is further described below in conjunction with accompanying drawing 2a-2h to described method.
First, perform step 201, Semiconductor substrate 201 is provided, in described Semiconductor substrate 201, is formed with various components and parts.
Particularly, with reference to Fig. 2 a, in this step, described Semiconductor substrate 201 can at least one in following mentioned material: stacked SiGe (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.Other active areas or active device can be formed with in described substrate, not repeat them here.
Perform step 202, described Semiconductor substrate 201 forms interlayer dielectric layer 202, in described interlayer dielectric layer 202, is formed with contact hole 203 and photo-etching mark hole 204, in described photo-etching mark hole 204, there is space.
Particularly, as shown in Figure 2 a, first in described Semiconductor substrate 201, interlayer dielectric layer 202 is formed, then patterning interlayer dielectric layer 202 to form contact hole opening and photo-etching mark hole opening in described interlayer dielectric layer 202, then filled conductive material in described contact hole opening, form described contact hole 203, be partially filled described photo-etching mark hole 204 simultaneously, after being partially filled described photo-etching mark hole 204, the sidewall in described photo-etching mark hole 204 forms conductive material layer, but still there is larger space in described photo-etching mark hole 204.
Perform step 203, sacrificial material layer 205 on described interlayer dielectric layer 202, to fill the space in described photo-etching mark hole 204.
Particularly; as shown in Figure 2 b; sacrificial material layer 205; to fill the space in described photo-etching mark hole 204 completely; described expendable material preferably has good step covering power (step coverage) in this step; to guarantee the space of filling described photo-etching mark hole 204 completely, using the protective layer as described photo-etching mark hole 204.
As preferably; described sacrificial material layer 205 selects amorphous carbon (a-C) in this step; described amorphous carbon (a-C) is as photo-etching mark hole 204(CT photo mark) locality protection material; final meeting is thoroughly got rid of; a-C compares SIN and more easily removes, and does not have the problem of residual (residue)
In addition, amorphous carbon (a-C) has good Step Coverage ability (step coverage), can effectively be filled in the space in photo-etching mark hole 204, and in follow-up process in removal, efficiently solves OVL and measure problem.In addition, a-C compares SIN, in CMP process and between silicon through hole medium (oxide), have higher Selection radio, can form better protection to CT; And a-C can remove by ashing (Asher) mode, clean and it is not easy to produce residue.
In of the present invention one particularly execution mode, described amorphous carbon (a-C) is formed by the method for CVD, and described reacting gas is hydrocarbon source (hydrocarbon source), can comprise gas phase hydrocarbon compound and (be preferably propylene; And/or comprise the steam of liquid-phase hydrocarbon compounds and the admixture of gas of carrier gas C3H6).Reaction temperature is maintained between about 100 DEG C of-Yue 450 DEG C, and be preferably between about 300 DEG C of-Yue 450 DEG C, to reduce the absorption coefficient of the film of generation, just can deposit a-C:H layer from process gas.This process comprises further and chamber pressure to be maintained between about 2 holder (Torr)-8 holders.The flow velocity in hydrocarbon source is about between 5000sccm between about 200sccm-, the flow velocity of carrier gas is between about 300sccm ~ about between 600sccm.
Perform step 205, sacrificial material layer 205 described in planarization to described interlayer dielectric layer 202, to remove the described sacrificial material layer 205 on described interlayer dielectric layer 202 surface.
Particularly, as shown in Figure 2 b, flattening method conventional in field of semiconductor manufacture can be used in this step to realize the planarization on surface.The limiting examples of this flattening method comprises mechanical planarization method and chemico-mechanical polishing flattening method.Chemico-mechanical polishing flattening method is more conventional.
After planarisation steps, remove the sacrificial material layer 205 be positioned on described interlayer dielectric layer 202 surface, retain the sacrificial material layer 205 in described gap.
Perform step 206, described interlayer dielectric layer 202 and described sacrificial material layer 205 form protective layer 206.
Particularly; as shown in Figure 2 c; described protective layer 206 can select the hard mask layer of metal or oxide in this step; of the present invention one particularly protective layer 206 described in execution mode select SiN; but be not limited to SiN; the thickness of described SiN can be thinner, such as, between 5-100 dust, as long as can play a protective role.
One in low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG) that the deposition process of described protective layer 206 can select chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method etc. to be formed.Preferred chemical vapor deposition (CVD) method in the present invention.
Perform step 207, protective layer 206, interlayer dielectric layer 202 and described Semiconductor substrate 201 described in patterning, to form silicon through hole groove 20 in described interlayer dielectric layer 202 and Semiconductor substrate 201.
Particularly; as shown in Figure 2 d; described protective layer 206, interlayer dielectric layer 202 and described Semiconductor substrate 201; to form the shape of described silicon through hole groove 20; protective layer 206 described in wet etching in this step; to form the shape of described silicon through hole groove 20, particularly, wherein comprise HF, H with the hydrofluoric acid DHF(diluted
2o
2and H
2o) described oxide hardmask layer is etched.Wherein, the concentration of described DHF does not strictly limit, in the present invention preferred HF:H
2o
2: H
2o=0.1-1.5:1:5.
Then be mask etch interlayer dielectric layer 202 and described Semiconductor substrate 201 with described protective layer 206, to form described silicon through hole groove 20 in described interlayer dielectric layer 202 and Semiconductor substrate 201.Described engraving method can select dry etching or wet etching, is not limited to a certain method.
The number of described silicon through hole groove 20 and the degree of depth are not limited to a certain number range in this step, and in this embodiment, the number of described silicon through hole groove 20 is one, its degree of depth is less than the thickness of described Semiconductor substrate 201, can arrange as required, not repeat them here.
Perform step 208, in described protective layer 206 and described silicon through hole groove 20, form separator 208.
Particularly, as shown in Figure 2 e, in of the present invention one particularly execution mode, described separator 203 is SiO
2layer, its thickness is 8-50 dust, but is not limited to this thickness.
Described protective layer 206 can be formed by chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method etc.Preferred ald (ALD) method in the present invention.
Perform step 209, in described silicon through hole groove 20, form diffusion impervious layer 206.
Particularly, as shown in Figure 2 e, time in critical size (critical dimension) going reduction to deep sub-micron range of device, need to use the RC delay time that multiple layer metal connecting line construction reduces because dead resistance and parasitic capacitance cause, form diffusion impervious layer (barrier) (not shown) in the present invention over the substrate, as preferably, the formation method on described barrier layer 206 can for mainly to select physical vaporous deposition and chemical vapour deposition technique, particularly, evaporation can be selected, electron beam evaporation, plasma spray deposition and sputtering, preferably plasma spray deposition and sputtering method form described barrier layer in the present invention.The thickness on described barrier layer is not limited in a certain numerical value or scope, can adjust as required.
As preferably, described diffusion impervious layer 206 material can one or more for being selected from TaN, Ta, TiN, Ti.
Perform step 210, filled conductive material 207 in described silicon through hole groove 20, to form through-silicon via structure.
Particularly, as shown in Figure 2 e, select metal material 207, such as select metallic copper to fill filled conductive material 207 in described silicon through hole groove 20, described silicon through hole groove 20 filled conductive material 207 can be filled by the method for physical vapor deposition (PVD) method or Cu electroplating (ECP) in the present invention.
As preferably, then in the first Seed Layer of plated metal copper on described diffusion impervious layer, the deposition process of described Seed Layer can select chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method etc.
Then select the method for Cu electroplating (ECP) to form described metallic copper, as preferably, can also use additive when electroplating, described additive is smooth dose (LEVELER), accelerator (ACCELERATORE) and inhibitor (SUPPRESSOR).
As preferably, forming the step that can also comprise annealing after described metallic copper is formed further, annealing can carry out 2-4 hour at 80-160 DEG C, to impel copper crystallization again, crystal grain of growing up, reduces resistance and improves stability.
Perform step 210, carry out chemico-mechanical polishing (CMP) technique, electric conducting material 207 described in planarization is to described protective layer 206.
As shown in figure 2f, flattening method conventional in field of semiconductor manufacture can be used in this step to realize the planarization on surface.The limiting examples of this flattening method comprises mechanical planarization method and chemico-mechanical polishing flattening method.Chemico-mechanical polishing flattening method is more conventional.
Perform step 211, remove described protective layer 206, to expose described sacrificial material layer 205.
Particularly, as shown in Figure 2 g, described protective layer 206 is removed in this step; to expose described sacrificial material layer 205 and contact hole 203; as preferably, select dry etching to remove described sacrificial material layer 205 in this step, can CF be selected in described dry etching in this step
4, CHF
3add N in addition
2, CO
2, O
2in one as etching atmosphere, wherein gas flow is CF
410-200sccm, CHF
310-200sccm, N
2or CO
2or O
210-400sccm, described etching pressure is 30-150mTorr, and etching period is 5-120s, is preferably 5-60s, is more preferably 5-30s.
Perform step 212, remove described sacrificial material layer 205.
Particularly, with reference to Fig. 2 h, select ashing method to remove described sacrificial material layer 205 in this step, in an embodiment of the present invention, select O
2or containing O
2atmosphere ashing process is carried out to described device, described ashing treatment temperature at 800-1500 DEG C, be preferably 1100-1200 DEG C, the processing time is 2-30min.
A-C can remove by ashing (Asher) mode, and a-C compares SIN and more easily removes, clean and it is not easy to produce residue.
Described method can further include at described through-silicon via structure high formation metal interconnect structure, described metal interconnect structure is formed metal pad and selects Damascus technics to form described metal interconnect structure in this step.In of the present invention one particularly execution mode, first on described the first metal layer, deposit the first erosion stop-layer, the first dielectric layer, etching stopping layer, dielectric layer, hard mask layer, oxide hardmask layer and metal hard mask successively; Etch described metal hard mask layer and the described compound hard mask layer of part, form opening, then deposit anti-reflective coatings and photoresist layer, and etching forms via openings; Remove described reflectance coating and photoresist layer; With described metal hard mask layer for dielectric layer described in mask etch, form multiple contact hole groove and through hole simultaneously; Etch described etching stopping layer, in described interlevel dielectric material layer, another dielectric layer described, form the metal interconnect structure inlayed to expose; Adopt electric conducting material (Cu) to fill described groove and through hole, and planarization is to form electrical connection.
The present invention proposes the protective layer using a-C as CT in silicon through hole preparation (TSV VIA middle) technique, a-C is as the good protective layer of one and sacrifice layer, the method that CVD can be used to deposit covers the surface of wafer, and compare SIN there is better Step Coverage ability, can to photo-etching mark hole 204(CT photo mark) cavity in region forms good filling, make silicon through hole medium (TSV isolation) that photo-etching mark hole 204(CT photo mark cannot be deposited on) region, so CT surface silicon through hole medium (TSV isolation) can be completely removed, thus do not affect the contraposition of follow-up the first metal layer photoetching (M1photo), efficiently solve OVL and measure problem.
In addition, a-C compares SIN, in CMP process and between silicon through hole medium (oxide), have higher Selection radio, can form better protection to CT.
And a-C can remove by ashing (Asher) mode, and a-C compares SIN and more easily removes, clean and it is not easy to produce residue.
Fig. 3 is preparation technology's flow chart of the present invention one semiconductor device described in execution mode particularly, specifically comprises the following steps:
Step 201 provides Semiconductor substrate, is formed with interlayer dielectric layer on the semiconductor substrate, is formed with contact hole and photo-etching mark hole in described interlayer dielectric layer, and described photo-etching mark hole has space;
Step 202 sacrificial material layer, to fill described space completely;
Step 203 forms protective layer on described interlayer dielectric layer and described sacrificial material layer;
Step 204 forms silicon through hole in described Semiconductor substrate and described interlayer dielectric layer;
Step 205 removes described protective layer, to expose described sacrificial material layer;
Step 206 removes described sacrificial material layer, to expose described space.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (9)
1. a preparation method for semiconductor device, comprising:
There is provided Semiconductor substrate, be formed with interlayer dielectric layer on the semiconductor substrate, be formed with contact hole and photo-etching mark hole in described interlayer dielectric layer, described photo-etching mark hole has space;
Sacrificial material layer, to fill described space completely;
Described interlayer dielectric layer and described sacrificial material layer form protective layer;
Silicon through hole is formed in described Semiconductor substrate and described interlayer dielectric layer;
Remove described protective layer, to expose described sacrificial material layer;
Remove described sacrificial material layer, to expose described space.
2. method according to claim 1, is characterized in that, described sacrificial material layer selects amorphous carbon.
3. method according to claim 1, is characterized in that, the method for filling described space is:
In described interlayer dielectric layer and described space, deposit described sacrificial material layer, to cover described interlayer dielectric layer, and fill described space;
Perform planarisation step, to remove the described sacrificial material layer on described interlayer dielectric layer surface.
4. method according to claim 1, is characterized in that, the method forming described silicon through hole is:
Described protective layer is formed the mask layer of patterning;
With described mask layer for protective layer, described interlayer dielectric layer and described Semiconductor substrate described in mask etch, to form silicon through hole groove;
Remove described mask layer;
Separator is formed in described silicon through hole groove;
Select silicon through hole groove described in filled with conductive material;
Perform planarisation step, described electric conducting material is planarized to described protective layer, to form described silicon through hole.
5. method according to claim 4, is characterized in that, the method for filling described silicon through hole groove is:
Described separator forms diffusion impervious layer;
Described diffusion impervious layer is formed the Seed Layer of metal;
Select electrochemistry electric plating method plated metal to fill described silicon through hole groove.
6. method according to claim 1 and 2, is characterized in that, selects ashing method to remove described sacrificial material layer.
7. method according to claim 1, is characterized in that, SiN layer selected by described protective layer;
Described interlayer dielectric layer selects oxide skin(coating).
8. method according to claim 1, is characterized in that, the method forming described contact hole and described photo-etching mark hole is:
Interlayer dielectric layer described in patterning, to form contact hole groove and photo-etching mark hole groove;
Deposits conductive material, to fill described contact hole groove completely, forms contact hole, is partially filled described photo-etching mark hole groove simultaneously, the sidewall of described photo-etching mark hole groove forms electric conducting material, to form the photo-etching mark hole that center has space.
9. the semiconductor device that the method that one of claim 1 to 8 is described prepares, described in described semiconductor device, the center in photo-etching mark hole has space.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310743149.4A CN104752323B (en) | 2013-12-27 | 2013-12-27 | A kind of semiconductor devices and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310743149.4A CN104752323B (en) | 2013-12-27 | 2013-12-27 | A kind of semiconductor devices and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104752323A true CN104752323A (en) | 2015-07-01 |
| CN104752323B CN104752323B (en) | 2018-03-20 |
Family
ID=53591806
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310743149.4A Active CN104752323B (en) | 2013-12-27 | 2013-12-27 | A kind of semiconductor devices and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104752323B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108511388A (en) * | 2017-02-27 | 2018-09-07 | Imec 非营利协会 | Make the patterned method of destination layer |
| CN108667437A (en) * | 2018-04-19 | 2018-10-16 | 中芯集成电路（宁波）有限公司 | A kind of thin film bulk acoustic wave resonator and its manufacturing method and electronic device |
| CN113745297A (en) * | 2021-08-31 | 2021-12-03 | 深圳市华星光电半导体显示技术有限公司 | OLED display panel, pixel repairing method and mobile terminal |
| CN114582721A (en) * | 2022-05-05 | 2022-06-03 | 湖北江城芯片中试服务有限公司 | Method for manufacturing semiconductor device |
| CN115922258A (en) * | 2023-02-07 | 2023-04-07 | 河南工学院 | Casting and milling integrated forming manufacturing method for terahertz metal coating hollow rectangular waveguide cavity |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW393725B (en) * | 1998-10-22 | 2000-06-11 | United Microelectronics Corp | Reproduction method of the alignment mark in the shallow trench isolation process |
| CN1292469A (en) * | 1999-10-08 | 2001-04-25 | 沈锝桓 | Flow control valve of feedback regulation pressure-difference hydraulic machine |
| US6528386B1 (en) * | 2001-12-20 | 2003-03-04 | Texas Instruments Incorporated | Protection of tungsten alignment mark for FeRAM processing |
| US20040198017A1 (en) * | 2003-01-28 | 2004-10-07 | Taiwan Semiconductor Manufacturing Company | Method to solve alignment mark blinded issues and technology for application of semiconductor etching at a tiny area |
| CN1820359A (en) * | 2003-06-24 | 2006-08-16 | 国际商业机器公司 | Planar magnetic tunnel junction substrate having recessed alignment marks |
| CN1292469C (en) * | 2001-07-19 | 2006-12-27 | 三洋电机株式会社 | Semiconductor device and its manufacture |
| CN101140903A (en) * | 2006-09-06 | 2008-03-12 | 海力士半导体有限公司 | Method of manufacturing a semiconductor device |
| KR100816248B1 (en) * | 2006-08-29 | 2008-03-21 | 동부일렉트로닉스 주식회사 | the semiconductor device and the manufacturing method thereof |
| JP2008135671A (en) * | 2006-11-29 | 2008-06-12 | Elpida Memory Inc | Method of manufacturing semiconductor device |
| CN102612748A (en) * | 2009-07-15 | 2012-07-25 | 桑迪士克3D公司 | Method of making damascene diodes using sacrificial material |
| CN103035511A (en) * | 2011-10-09 | 2013-04-10 | 上海华虹Nec电子有限公司 | Method for producing zero layer photoetching marking of high-voltage device without barrier layers |
| US20130119543A1 (en) * | 2011-11-16 | 2013-05-16 | Globalfoundries Singapore Pte. Ltd. | Through silicon via for stacked wafer connections |
| CN103367234A (en) * | 2012-03-29 | 2013-10-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure forming method |
| CN103378033A (en) * | 2012-04-27 | 2013-10-30 | 台湾积体电路制造股份有限公司 | Through-substrate vias and methods for forming the same |
-
2013
- 2013-12-27 CN CN201310743149.4A patent/CN104752323B/en active Active
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW393725B (en) * | 1998-10-22 | 2000-06-11 | United Microelectronics Corp | Reproduction method of the alignment mark in the shallow trench isolation process |
| CN1292469A (en) * | 1999-10-08 | 2001-04-25 | 沈锝桓 | Flow control valve of feedback regulation pressure-difference hydraulic machine |
| CN1292469C (en) * | 2001-07-19 | 2006-12-27 | 三洋电机株式会社 | Semiconductor device and its manufacture |
| US6528386B1 (en) * | 2001-12-20 | 2003-03-04 | Texas Instruments Incorporated | Protection of tungsten alignment mark for FeRAM processing |
| US20040198017A1 (en) * | 2003-01-28 | 2004-10-07 | Taiwan Semiconductor Manufacturing Company | Method to solve alignment mark blinded issues and technology for application of semiconductor etching at a tiny area |
| CN1820359A (en) * | 2003-06-24 | 2006-08-16 | 国际商业机器公司 | Planar magnetic tunnel junction substrate having recessed alignment marks |
| KR100816248B1 (en) * | 2006-08-29 | 2008-03-21 | 동부일렉트로닉스 주식회사 | the semiconductor device and the manufacturing method thereof |
| CN101140903A (en) * | 2006-09-06 | 2008-03-12 | 海力士半导体有限公司 | Method of manufacturing a semiconductor device |
| JP2008135671A (en) * | 2006-11-29 | 2008-06-12 | Elpida Memory Inc | Method of manufacturing semiconductor device |
| CN102612748A (en) * | 2009-07-15 | 2012-07-25 | 桑迪士克3D公司 | Method of making damascene diodes using sacrificial material |
| CN103035511A (en) * | 2011-10-09 | 2013-04-10 | 上海华虹Nec电子有限公司 | Method for producing zero layer photoetching marking of high-voltage device without barrier layers |
| US20130119543A1 (en) * | 2011-11-16 | 2013-05-16 | Globalfoundries Singapore Pte. Ltd. | Through silicon via for stacked wafer connections |
| CN103367234A (en) * | 2012-03-29 | 2013-10-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure forming method |
| CN103378033A (en) * | 2012-04-27 | 2013-10-30 | 台湾积体电路制造股份有限公司 | Through-substrate vias and methods for forming the same |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108511388A (en) * | 2017-02-27 | 2018-09-07 | Imec 非营利协会 | Make the patterned method of destination layer |
| CN108667437A (en) * | 2018-04-19 | 2018-10-16 | 中芯集成电路（宁波）有限公司 | A kind of thin film bulk acoustic wave resonator and its manufacturing method and electronic device |
| CN108667437B (en) * | 2018-04-19 | 2022-04-26 | 中芯集成电路（宁波）有限公司 | Film bulk acoustic resonator, manufacturing method thereof and electronic device |
| CN113745297A (en) * | 2021-08-31 | 2021-12-03 | 深圳市华星光电半导体显示技术有限公司 | OLED display panel, pixel repairing method and mobile terminal |
| CN114582721A (en) * | 2022-05-05 | 2022-06-03 | 湖北江城芯片中试服务有限公司 | Method for manufacturing semiconductor device |
| CN114582721B (en) * | 2022-05-05 | 2022-08-02 | 湖北江城芯片中试服务有限公司 | Method for manufacturing semiconductor device |
| WO2023213085A1 (en) * | 2022-05-05 | 2023-11-09 | 湖北江城芯片中试服务有限公司 | Method for manufacturing semiconductor device |
| CN115922258A (en) * | 2023-02-07 | 2023-04-07 | 河南工学院 | Casting and milling integrated forming manufacturing method for terahertz metal coating hollow rectangular waveguide cavity |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104752323B (en) | 2018-03-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11854962B2 (en) | Via structure and methods thereof | |
| TWI818663B (en) | Metal-insulator-metal capacitor structure and method for forming the same | |
| US9087878B2 (en) | Device with through-silicon via (TSV) and method of forming the same | |
| JP5562087B2 (en) | Via structure and via etching process to form it | |
| US10937694B2 (en) | Chamferless via structures | |
| US20220208749A1 (en) | Semiconductor devices and methods of manufacture thereof | |
| CN101847597B (en) | Integrated circuit structure | |
| US20160133828A1 (en) | Embedded magnetoresistive random access memory (mram) integration with top contacts | |
| US20150028476A1 (en) | Devices, systems, and methods related to forming through-substrate vias with sacrificial plugs | |
| CN104752323A (en) | Semiconductor device and preparation method thereof | |
| US20190221473A1 (en) | Skip via structures | |
| CN104752324A (en) | Preparation method of semiconductor device | |
| CN104425356A (en) | Preparation method of semiconductor device | |
| CN102237295B (en) | Semiconductor structure manufacturing method | |
| CN104752322A (en) | Semiconductor device and manufacturing method thereof | |
| US11114338B2 (en) | Fully aligned via in ground rule region | |
| CN104900543A (en) | Semiconductor device and preparation method thereof | |
| US9831124B1 (en) | Interconnect structures | |
| EP2826061A1 (en) | Semiconductor constructions and methods of planarizing across a plurality of electrically conductive posts | |
| CN107978515A (en) | A kind of semiconductor devices and its manufacture method | |
| Tenailleau et al. | TSV development, characterization and modeling for 2.5-D interposer applications | |
| CN106558533B (en) | Method for forming conductive plug structure | |
| US11594420B1 (en) | Semiconductor structure and manufacturing method thereof | |
| CN103579088B (en) | A kind of preparation method of semiconductor device silicon through hole |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |