WO2023213085A1

WO2023213085A1 - Method for manufacturing semiconductor device

Info

Publication number: WO2023213085A1
Application number: PCT/CN2022/140985
Authority: WO
Inventors: 汪松; 王逸群; 程曲; 刘天建
Original assignee: 湖北江城芯片中试服务有限公司
Priority date: 2022-05-05
Filing date: 2022-12-22
Publication date: 2023-11-09
Also published as: CN114582721A; CN114582721B

Abstract

Disclosed in the embodiments of the present disclosure is a method for manufacturing a semiconductor device, comprising: forming first blind holes in a first wafer; forming first filling structures in the first blind holes; forming a first mask structure covering the first wafer and the first filling structures, the first mask structure comprising mask openings; etching the first wafer according to the mask openings so as to form second blind holes in the first wafer, the depth of the second blind holes being different from that of the first blind holes, and the positions of the second blind holes being different from the positions of the first blind holes; and after forming the second blind holes, removing the first mask structure and the first filling structures.

Description

Semiconductor device manufacturing method

Cross-references to related applications

This application is filed based on the Chinese patent application with application number 202210479744.0, the filing date is May 5, 2022, and the invention name is "Method for Manufacturing Semiconductor Devices", and claims the priority of the Chinese patent application. All the Chinese patent applications The contents are incorporated herein by reference into this application.

Technical field

Embodiments of the present disclosure relate to, but are not limited to, the field of semiconductor manufacturing, and in particular, to a method of manufacturing a semiconductor device.

Background technique

During the manufacturing process of semiconductor devices, hole structures (including through holes and/or blind holes) can be formed in the wafer through a hole etching process.

The hole etching process currently only etches a hole structure of one depth on the wafer surface. If it involves etching hole structures of two depths or more than two depths, for example, when etching to form a second hole structure, the hole structure that has been formed will The depth and sidewall morphology of the first hole structure (which has a different depth than the second hole structure) are difficult to control, resulting in poor stability of the hole engraving process.

Contents of the invention

An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including:

forming a first blind via in the first wafer;

forming a first filling structure in the first blind hole;

Forming a first mask structure covering the first wafer and the first filling structure; wherein the first mask structure includes a mask opening;

The first wafer is etched according to the mask opening to form a second blind hole in the first wafer; wherein the depth of the second blind hole is different from the depth of the first blind hole. ;The position of the second blind hole is different from the position of the first blind hole;

After forming the second blind hole, the first mask structure and the first filling structure are removed.

In some embodiments, the first filling structure includes: a first bonding glue layer; the first mask structure includes: a second wafer; wherein the second wafer includes the mask opening;

Forming a first filling structure in the first blind hole includes:

Coating the first bonding glue layer into the first blind hole;

The forming a first mask structure covering the first wafer and the first filling structure includes:

Align and bond the first wafer and the second wafer; wherein the first bonding glue layer is located between the first wafer and the second wafer.

In some embodiments, the first wafer includes: a first area and a second area; wherein the first blind hole is located in the first area; the manufacturing method further includes:

While filling the first blind hole with the first bonding glue layer, the first bonding glue layer covering the second area is formed.

In some embodiments, the second wafer includes: a third region and a fourth region; wherein the mask opening is located in the fourth region;

Before aligning and bonding the first wafer and the second wafer, the manufacturing method further includes:

Forming a second bonding glue layer covering the third region;

The bonding of the first wafer and the second wafer includes:

The first bonding glue layer and the second bonding glue layer are bonded, so that the first wafer and the second wafer are bonded.

In some embodiments, removing the first mask structure and the first filling structure after forming the second blind hole includes:

Perform a debonding process on the first wafer and the second wafer to expose the first bonding glue layer;

Remove the first bonding glue layer.

In some embodiments, the first wafer includes: a first area and a second area; wherein the first blind hole is located in the first area;

Forming a first filling structure in the first blind hole includes:

Depositing a filling material into the first blind hole; wherein the filling material covers the second area;

The filling material located on the first wafer is removed to form the first filling structure; wherein a top surface of the first filling structure is substantially flush with a top surface of the first wafer.

In some embodiments, forming a first filling structure in the first blind hole includes:

Form the first filling structure covering the sidewall of the first blind hole and the bottom of the first blind hole, and form a first sub-blind hole based on the topography of the first blind hole;

The first mask structure is formed to cover the first wafer and the first sub-blind hole; wherein the first mask structure is substantially flush with a surface relatively far away from the first wafer.

In some embodiments, forming a first mask structure covering the first wafer and the first filling structure includes:

bonding the first wafer and the second wafer; wherein the first filling structure is located between the first wafer and the second wafer;

The mask opening is formed through the second wafer; wherein the mask opening exposes the first wafer.

In some embodiments, after bonding the first wafer and the second wafer, and before etching the second wafer, the manufacturing method further includes:

Thinning a side of the second wafer relatively away from the first wafer.

In some embodiments, after forming the second blind hole and before removing the first mask structure and the first filling structure, the manufacturing method further includes:

forming a second filling structure in the second blind hole;

forming a second mask structure covering the first mask structure and the second filling structure;

Form a third blind hole that penetrates the second mask structure and the first mask structure and has a bottom located in the first wafer; wherein the depth of the third blind hole is the same as that of the second blind hole. The depth of the third blind hole is different from the depth of the first blind hole; the position of the third blind hole is different from the position of the second blind hole, and the position of the third blind hole is different. It is different from the position of the first blind hole.

In the embodiment of the present disclosure, by first forming a first filling structure in the first blind hole, and then forming a first mask structure covering the first wafer and the first filling structure, and then according to the mask in the first mask structure By etching the first wafer with the opening, a second blind hole having a different depth from the first blind hole can be formed in the first wafer. In the process of forming the second blind hole, since the first filling structure is formed in the first blind hole and the first mask structure covers the first filling structure, the first mask structure and the first filling structure can be better protected. The sidewalls and bottom of the first blind hole reduce the probability that the formed first blind hole is exposed to the etching environment, which is beneficial to ensuring a better shape of the sidewall of the first blind hole and reducing the risk of the first blind hole being exposed to the etching environment. The probability of the hole being further etched makes the actual depth of the first blind hole closer to the design depth, which is beneficial to improving the process stability of through-silicon via engraving.

Furthermore, if it is necessary to form the first blind hole and the second blind hole in different first wafers, the first mask structure including the mask opening can be reused, that is, the first mask structure can be reused. In this way, the demand for the first mask structure in subsequent processing can be reduced, and the manufacturing cost of the semiconductor device can be reduced.

Description of the drawings

In order to more clearly explain the specific embodiments of the present disclosure or the technical solutions in the prior art, the drawings that need to be used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description The drawings illustrate some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 is a flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

Figure 2 is a schematic diagram 1 of a semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 3 is a schematic diagram 2 of a semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 4 is a schematic diagram 3 of a semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 5 is a schematic diagram 4 of a semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 6 is a schematic diagram 5 of a semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 7 is a schematic diagram 6 of a semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 8 is a schematic diagram 7 of a semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 9a is a schematic diagram 8 of a semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 9b is a schematic diagram 9 of a semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 9c is a schematic diagram 10 of a semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 10 is a schematic diagram 11 of a semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 11 is a schematic diagram 12 of a semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 12 is a schematic diagram of a semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 13 is a schematic diagram of a semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 14 is a schematic diagram of a semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 15 is a schematic diagram of a semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 16 is a schematic diagram of a semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 17 is a schematic diagram 1 of another semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 18a is a schematic diagram 2 of another semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 18b is a schematic diagram 3 of another semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 19 is a schematic diagram 4 of another semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 20 is a schematic diagram 5 of another semiconductor device manufacturing process according to an embodiment of the present disclosure;

Figure 21 is a schematic diagram 6 of another semiconductor device manufacturing process according to an embodiment of the present disclosure;

FIG. 22 is a schematic diagram 7 of another semiconductor device manufacturing process according to an embodiment of the present disclosure.

Detailed ways

The following examples are provided to better understand the present disclosure. They are not limited to the best implementation modes and do not limit the content and protection scope of the present disclosure. Anyone who is inspired by the present disclosure or interprets the present disclosure Any product that is identical or similar to the present disclosure by combining it with other features of the prior art falls within the protection scope of the present disclosure.

In the description of the present disclosure, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "inner", "outer", etc. are based on the orientation or positional relationship shown in the drawings, and are only for the purpose of The disclosure is facilitated and simplified, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be construed as a limitation on the disclosure. In addition, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance.

With the development of semiconductor technology, the characteristic size of integrated circuits continues to shrink, and the density of device interconnections continues to increase. Traditional two-dimensional packaging can no longer meet the needs of the industry. Therefore, the adapter board packaging method based on through silicon via (TSV) vertical interconnection has its key technical advantages of short-distance interconnection, high-density integration and low cost. , gradually leading the development of packaging technology.

Two different depths of through-silicon vias can be formed in the wafer by performing two drilling processes. After performing the first hole etching process and before performing the second hole etching process, a photoresist layer covering the wafer, the sidewalls and the bottom of the first through silicon via is formed. By performing an exposure and development process, a patterned photoresist layer is formed, and a second hole-engraving process is performed according to the pattern in the photoresist layer to form a second through-silicon via in the wafer.

Here, the first through silicon via and the second through silicon via can be used as light-transmitting structures, that is, allowing light to pass through. Alternatively, the first through silicon via and the second through silicon via can be filled with conductive material to form a conductive interconnection structure, and the interconnection structure is used to realize electrical connection between two functional structures.

However, the sidewalls of the first through silicon hole formed after performing the first hole etching process are almost perpendicular to the bottom of the first through silicon hole, and the photoresist covering the sidewalls of the first through silicon hole may fall off. When performing the second hole-engraving process, the photoresist on the sidewall of the first through-silicon hole falls off, and the sidewall of the first through-silicon hole is exposed to the etching environment, causing damage to the sidewall of the first through-silicon hole.

In the related art, a bump is first formed at a preset position of the second through-silicon via, and after the first hole-engraving process is performed, the bump is removed to expose the wafer, and the wafer with the bump exposed is The second hole engraving process. In this way, there is no need to apply a photoresist layer, which prevents the photoresist covering the sidewall of the first through silicon hole from falling off.

However, in the above-mentioned solution of removing the bumps and then performing the second hole-engraving process, when the first through-silicon hole reaches the designed depth after the first hole-engraving process is performed, during the second hole-engraving process, due to The first through silicon via is not protected, and the first through silicon via is exposed to the etching environment, causing the actual depth of the first through silicon via to increase (that is, greater than the design depth of the first through silicon via), reducing the cost of through silicon via etching. Hole process stability.

Moreover, when the first through silicon hole is used as a light-transmitting structure, other structures located below the first through silicon hole may be damaged because the first through silicon hole is further etched. When the conductive material is filled into the first through silicon hole, since the actual depth of the first through silicon hole increases, the actual depth of the interconnection structure filling the first through silicon hole increases, affecting signal transmission. For example, signal delay occurs, etc.

Furthermore, if it is necessary to form more than two through silicon holes with different depths in the wafer, the actual depth of the first through silicon hole will further increase, and the actual depth of the second through silicon hole will increase, resulting in a through silicon hole engraving process. Stability is further reduced.

When the first through silicon hole does not reach the designed depth after performing the first hole etching process, the first through silicon hole can be further etched to the designed depth during the second hole etching process. . However, this solution requires first forming a first through silicon hole with a deep depth, and then forming a second through silicon hole with a shallow depth. That is, the production of the through silicon hole needs to be performed in a process from deep to shallow, resulting in a through silicon hole manufacturing process. The flexibility is low, and the deep first through silicon hole requires two drilling processes, resulting in poor continuity of the sidewalls of the first through silicon hole.

Moreover, when the first through-silicon via is used as a light-transmitting structure, the poor continuity of the sidewalls of the first through-silicon via may increase the probability of light refraction, affecting the transmission of light. When the conductive material is filled into the first through silicon hole, due to poor continuity of the sidewalls of the first through silicon hole, subsequent filling of the conductive material may be affected.

In view of this, embodiments of the present disclosure provide a method for manufacturing a semiconductor device.

Figure 1 is a flow chart of a manufacturing method of a semiconductor device according to an embodiment of the present disclosure. The manufacturing method at least includes the following steps:

S100: Form the first blind hole in the first wafer;

S200: Form a first filling structure in the first blind hole;

S300: Form a first mask structure covering the first wafer and the first filling structure; wherein the first mask structure includes a mask opening;

S400: Etch the first wafer according to the mask opening to form a second blind hole in the first wafer; wherein the depth of the second blind hole is different from the depth of the first blind hole; the position of the second blind hole is different from the depth of the first blind hole. The location of the first blind hole is different;

S500: After forming the second blind hole, remove the first mask structure and the first filling structure.

Moreover, since the probability of the first blind hole being further etched is reduced, it is helpful to reduce the probability that other structures located under the first through silicon hole are damaged, which can better protect other structures located under the first through silicon hole. structure.

In addition, since the etching of the second blind hole and the etching of the first blind hole are performed independently, it is beneficial to ensure better continuity of the side walls of the second blind hole and the first blind hole.

2 to 22 are schematic diagrams of a manufacturing process of a semiconductor device according to embodiments of the present disclosure. The present disclosure will be described in further detail below with reference to FIGS. 1, 2 to 22.

First, referring to FIGS. 2 to 8 , step S100 is performed: forming a first blind hole 104 in the first wafer 101 .

In some embodiments, before performing step S100, the above production method further includes:

providing a first wafer 101;

Sequentially forming a first mask material layer 102' and a first photoresist material layer 103' covering the first wafer 101;

forming a first photolithography pattern 1031 in the first photoresist material layer 103';

Etch the first mask material layer 102' according to the first photolithography pattern 1031 to form a mask pattern 1021 in the first mask material layer 102';

The above step S100 includes:

The first wafer 101 is etched according to the mask pattern 1021 to form a first blind hole 104 in the first wafer 101 .

Exemplarily, the first mask material layer 102' is deposited on the first wafer 101 through a thin film deposition process. The thin film deposition process includes but is not limited to chemical vapor deposition (CVD) process and plasma enhanced chemical vapor deposition (PECVD). process, atomic layer deposition (ALD) process, or a combination thereof.

Exemplarily, the first photoresist material layer 103' is coated on the first mask material layer 102' through a glue coating process. Glue coating processes include, but are not limited to, spin coating processes, spray coating processes, roller coating processes, dip coating processes, printing processes or combinations thereof.

Exemplarily, through an exposure and development process, the first photoresist layer 103 including the first photolithography pattern 1031 is formed, and the bottom of the first photolithography pattern 1031 exposes the first mask material layer 102'. The first photolithography pattern 1031 is used to define the position of the first blind hole 104 .

Exemplarily, through an etching process, the first mask material layer 102' is etched downward along the z-axis direction to form the mask layer 102 including the mask pattern 1021, and the bottom of the mask pattern 1021 exposes the first wafer 101 , continue to etch the first wafer 101 downward along the z-axis direction to form a first blind hole 104 in the first wafer 101, and the bottom of the first blind hole 104 is located in the first wafer 101. The etching process includes, but is not limited to, dry etching, wet etching or combinations thereof. The mask layer 102 is used to protect the mask pattern 1021 during etching to form the first blind hole 104 and reduce the probability of the mask pattern 1021 being deformed.

The constituent materials of the first wafer 101 include: elemental semiconductor materials (such as silicon, germanium), group III-V compound semiconductor materials, group II-VI compound semiconductor materials, organic semiconductor materials or other semiconductor materials known in the art. In this embodiment, the first wafer 101 is a silicon wafer.

The composition material of the first mask material layer 102' includes: any one of silicon oxide, silicon nitride, polysilicon, amorphous carbon, spin-coated carbon or any combination thereof.

The constituent materials of the first photoresist material layer 103' include photosensitive resin or radiation-sensitive materials.

The first blind hole 104 may be a hole structure located in the first wafer 101 , or may be a groove structure located in the first wafer 101 . The projection of the first blind hole 104 on the horizontal plane includes a circle, an ellipse, a square or a rectangle, etc. Here, the horizontal plane may be a plane perpendicular to the z-axis.

Then, step S200 is performed: forming a first filling structure in the first blind hole 104 .

In some embodiments, the first filling structure includes: a first bonding glue layer;

The above step S200 includes: applying a first bonding glue layer into the first blind hole 104 .

For example, the first bonding glue layer 105' can be coated into the first blind hole 104 through a glue coating process. Glue coating processes include, but are not limited to, spin coating processes, spray coating processes, roller coating processes, dip coating processes, printing processes or combinations thereof.

In one example, referring to Figure 9a, the first bonding glue layer 105' includes a gap 1051, that is, the first bonding glue layer 105' in Figure 9a is a hollow structure. In another example, referring to Figure 9b, the first bonding glue layer 105' completely fills the first blind hole 104, that is, the first bonding glue layer 105' in Figure 9b is a solid structure.

In one example, the top surface of the first bonding glue layer 105′ is substantially flush with the top surface of the first wafer 101. Here, substantially flush includes that the top surface of the first bonding adhesive layer 105' is completely flush with the top surface of the first wafer 101, or the top surface of the first bonding adhesive layer 105' is completely flush with the top surface of the first wafer 101. The distance between the top surfaces is very small and can be ignored.

It should be pointed out that during the process of coating the first bonding glue layer 105' into the first blind hole 104, due to the influence or limitation of actual process conditions, a gap 1051 as shown in Figure 9a may appear. By setting the top surface of the first bonding adhesive layer 105' to be substantially flush with the top surface of the first wafer 101, the flatness of the first wafer 101 during processing can be ensured, providing a relatively flat surface for subsequent semiconductor processes. s surface.

Moreover, by ensuring that the top surface of the first bonding glue layer 105' is substantially flush with the top surface of the first wafer 101, it is helpful to improve the subsequent alignment accuracy and bonding between the first wafer and the second wafer. accuracy, thereby improving the process stability of subsequent production of the second blind hole.

The first bonding glue layer 105' includes a temporary bonding (Temporary Bonding, TB) glue, which is used to temporarily bond the first wafer and the second wafer or to connect the first wafer and the second wafer in the subsequent process. Circle debonding. The material of the temporary bonding glue includes polymer materials that dissolve after laser irradiation or polymer materials that dissolve after heating. For example, thermoplastic resin, etc.

In the embodiment of the present disclosure, by coating the first bonding glue layer into the first blind hole, the first bonding glue layer can protect the side walls and bottom of the first blind hole and can also be used in subsequent processes. The first wafer and the second wafer are bonded, and the bonded second wafer can further protect the first bonding glue layer located in the first blind hole, so that the subsequent etching of the second blind hole is independent of the first blind hole. Performing the process with one blind hole will help reduce the probability of the first blind hole being further etched and improve the stability of the through silicon via etching process.

In some embodiments, referring to FIG. 8 , the first wafer 101 includes: a first area 101a and a second area 101b; wherein the first blind hole 104 is located in the first area 101a; the above manufacturing method also includes:

While the first bonding glue layer 105 is filled into the first blind hole 104, the first bonding glue layer 105 covering the second area 101b is formed.

For example, the first area 101a may be an area in the first wafer 101 used to form the first blind hole 104, and the second area 101b may be an area in the first wafer 101 except the first area 101a. When the first bonding glue layer is coated into the first blind hole 104, part of the first bonding glue layer is coated on the second area 101b, thereby forming the first bonding glue layer 105 as shown in FIG. 9c.

In some embodiments, the surface of the first bonding adhesive layer 105 relatively far away from the first wafer 101 satisfies the preset flatness condition. Here, satisfying the preset flat condition includes: the surface of the first bonding glue layer 105 relatively far away from the first wafer 101 is parallel to the horizontal plane, or the surface of the first bonding glue layer 105 relatively far away from the first wafer 101 is parallel to the horizontal plane. The flatness tolerance range includes -20nm to 20nm.

In the embodiment of the present disclosure, while filling the first blind hole with the first bonding glue layer, the first bonding glue layer covering the second area is formed, which is beneficial to increasing the coating area of the first wafer surface with the first bonding glue. area of the bonding layer, thereby increasing the adhesion strength between the first wafer and the second wafer that are subsequently bonded, and ensuring the firm bonding between the first wafer and the second wafer through bonding glue. property, reducing the probability of offset or early debonding due to excessively low adhesion strength between the first wafer and the second wafer, which is conducive to ensuring the normal progress of the subsequent production of the second blind hole.

Next, step S300 is performed: forming a first mask structure covering the first wafer 101 and the first filling structure; wherein the first mask structure includes a mask opening 1061 . The following will take the example shown in FIG. 9c as an example for description, but the present disclosure is not limited thereto.

In some embodiments, as shown in Figure 13, the first mask structure includes: a second wafer 106; wherein the second wafer 106 includes a mask opening 1061;

The above step S300 includes: aligning and bonding the first wafer 101 and the second wafer 106; wherein the first bonding glue layer 105 is located between the first wafer 101 and the second wafer 106.

The constituent materials of the second wafer 106 include: elemental semiconductor materials (such as silicon, germanium), group III-V compound semiconductor materials, group II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art.

It can be understood that in this embodiment, the second wafer 106 is a wafer including a mask opening 1061, and the mask opening 1061 is used to define the position of the second blind hole formed subsequently. The second wafer 106 is used to protect the mask opening 1061 during etching to form the second blind hole and reduce the probability of the mask opening 1061 being deformed. In other examples, the second wafer 106 may be a complete wafer, which will be described in detail below and will not be described again here.

In some embodiments, as shown in FIG. 13 , the second wafer 106 includes: a third area and a fourth area; wherein the mask opening 1061 is located in the fourth area;

Before aligning and bonding the first wafer 101 and the second wafer 106, the above manufacturing method also includes:

Forming a second bonding glue layer covering the third region;

The above-mentioned bonding of the first wafer 101 and the second wafer 106 includes:

The first bonding glue layer 105 and the second bonding glue layer are bonded, so that the first wafer 101 and the second wafer 106 are bonded.

For example, the fourth region may be a region in the second wafer 106 for forming the mask opening 1061, and the third region may be a region in the second wafer 106 except the fourth region. Using the above glue coating process, a second bonding adhesive layer is coated on the third area of the second wafer 106, and the second wafer 106 is inverted so that the surface of the third area coated with the second bonding adhesive layer faces the third area. A wafer 101 is then bonded with the first bonding adhesive layer 105 and the second bonding adhesive layer.

It can be understood that after the first wafer 101 and the second wafer 106 are bonded, the first bonding glue layer 105 is located between the first wafer 101 and the second wafer 106, and the second bonding glue layer ( (not shown in the figure) is located between the first bonding glue layer 105 and the second wafer 106 .

The second bonding glue layer includes temporary bonding glue, which is used to temporarily bond the first wafer and the second wafer or to debond the first wafer and the second wafer in subsequent processes. Temporary bonding glue is made of polymer materials that dissolve after laser irradiation, such as thermoplastic resins. In this embodiment, the second bonding glue layer is the same as the first bonding glue layer. In other embodiments, the second bonding glue layer is different from the first bonding glue layer.

Compared with only coating the first bonding adhesive layer on the first wafer, in the embodiment of the present disclosure, the second bonding adhesive layer is also coated on the third area of the second wafer, which is beneficial to increase the subsequent The adhesion strength between the bonded first wafer and the second wafer further ensures the firmness of the bonding between the first wafer and the second wafer through the bonding glue and reduces the risk of the first wafer being bonded. The probability of offset or premature debonding due to excessively low adhesion strength to the second wafer is conducive to further ensuring the normal progress of the subsequent production of the second blind hole.

In some embodiments, as shown in Figure 10 and Figure 13, the above step S300 includes:

Bonding the first wafer 101 and the second wafer 106"; wherein the first filling structure is located between the first wafer 101 and the second wafer 106";

A mask opening 1061 is formed through the second wafer 106 ″; wherein the mask opening 1061 exposes the first wafer 101 .

Exemplarily, a second photoresist material layer covering the second wafer 106″ is formed, and a second photoresist including a second photoresist pattern 1071 is formed by performing an exposure and development process on the second photoresist material layer. Layer 107. Here, the composition material of the second photoresist layer 107 may be the same as the composition material of the first photoresist layer 103, which will not be described again.

Illustratively, through an etching process, the second wafer 106" is etched downward along the z-axis direction to form the second wafer 106 including the mask opening 1061. In an example, the first bonding glue layer 105 only Located in the first blind hole, the bottom of the mask opening 1061 exposes the first wafer 101. In another example, the first bonding glue layer 105 is also located on the second area, and the bottom of the mask opening 1061 exposes the first bond Bond the adhesive layer 105 and remove the first bonding adhesive layer 105 exposed at the bottom of the mask opening 1061 to expose the first wafer 101 .

Different from the second wafer 106 in Figure 13, in this example, the second wafer 106" is a complete wafer. Here, the complete wafer means that it has not been processed by photolithography, etching, deposition, etc. Processed wafers, or wafers without mask openings or circuit patterns.

In actual applications, it is usually necessary to process the first wafers of a certain batch to form at least a first blind hole and a second blind hole in each first wafer of the batch. For example, when making the first blind hole in the first first wafer, the second wafer 106″ is used to process the first first wafer to form the second wafer 106 including the mask opening 1061 (such as As shown in Figure 13), when making the second blind hole in the second first wafer, the second wafer 106 can be reused without using another complete second wafer 106". In this way, the number of The demand for the second wafer 106″ reduces the manufacturing cost of the semiconductor device.

In some embodiments, as shown in conjunction with Figures 10 and 11, after bonding the first wafer 101 and the second wafer 106" and before etching the second wafer 106", the above manufacturing method further includes:

Thinning the side of the second wafer 106" relatively away from the first wafer 101.

For example, a thinning process can be performed on the side of the second wafer 106" relatively far away from the first wafer 101 to form the thinned second wafer 106' as shown in Figure 11, and then the thinning process is performed. The second photoresist material layer is coated on the second wafer 106'. Here, the thinning process includes planarization process or etching process.

It can be understood that the second wafer 106 is used as a hard mask layer for making the second blind hole 108. By performing a thinning process on the second wafer 106", the thickness of the second wafer 106" can be reduced. The final second wafer 106 has a thickness that meets the process requirements for use as a hard mask layer.

It should be emphasized that in actual applications, when the thickness of the provided second wafer 106″ has met the process requirements for use as a hard mask layer, thinning processing may not be performed, and the disclosure is not limited here.

Next, as shown in FIG. 13 and FIG. 14 , step S400 is performed: etching the first wafer 101 according to the mask opening 1061 to form a second blind hole 108 in the first wafer 101 ; wherein, the second blind hole The depth of 108 is different from the depth of the first blind hole 104; the position of the second blind hole 108 is different from the position of the first blind hole 104.

Exemplarily, through an etching process, the first wafer 101 is etched downward along the z-axis direction to form a second blind hole 108 in the first wafer 101. The bottom of the second blind hole 108 is located on the first wafer. Within 101. The etching process includes, but is not limited to, dry etching, wet etching or combinations thereof.

The second blind hole 108 may be a hole structure located in the first wafer 101 , or may be a groove structure located in the first wafer 101 . The projection of the second blind hole 108 on the horizontal plane includes a circle, an ellipse, a square or a rectangle, etc. Here, the horizontal plane may be a plane perpendicular to the z-axis.

The difference between the depth of the second blind hole 108 and the depth of the first blind hole 104 includes: the depth of the second blind hole 108 is greater than the depth of the first blind hole 104 , or the depth of the second blind hole 108 is smaller than the depth of the first blind hole 104 . depth.

It can be understood that since the first filling structure is formed in the first blind hole and the second wafer covers the first blind hole formed with the first filling structure, during the process of etching to form the second blind hole, it can be reduced. The probability that the first blind hole is exposed to the etching environment is small, that is, the probability that the first blind hole is further etched is reduced. Therefore, the manufacturing method provided by the embodiment of the present disclosure is beneficial to ensure that the sidewall morphology of the formed first blind hole is better, and does not increase the depth of the formed first blind hole.

In addition, since the etching of the first blind hole and the etching of the second blind hole are performed independently, the fabrication of the through silicon via does not need to be performed in a process from deep to shallow. For example, when the depth of the first blind hole is h ₁ and the second blind hole is The depth h ₂ of the blind hole satisfies: h ₁ <h ₂ . The first blind hole with a shallow depth can be formed first, and then the second blind hole with a deep depth can be formed. For another example, when the depth h ₁ of the first blind hole and the depth h ₂ of the second blind hole satisfy: h ₁ > h ₂ , the first blind hole with a deep depth can be formed first, and then the second blind hole with a shallow depth can be formed. This will help improve the flexibility of the through silicon via manufacturing process. Moreover, both the first blind hole and the second blind hole are formed through one etching, which is beneficial to ensuring the continuity of the side wall of the first blind hole and the continuity of the side wall of the second blind hole, that is, the side wall of the first blind hole. The wall and the sidewall of the second blind hole are relatively flat.

Finally, as shown in FIGS. 14 to 16 , step S500 is performed: after forming the second blind hole 108 , remove the first mask structure and the first filling structure.

In some embodiments, after forming the second blind hole 108, the above step S500 includes:

Perform a debonding process on the first wafer 101 and the second wafer 106 to expose the first bonding glue layer 105;

The first bonding glue layer 105 is removed.

Exemplarily, after the second blind hole 108 is formed, the first bonding glue layer 105 is irradiated with a laser or the first bonding glue layer 105 is heated, so that the first bonding glue layer 105 is dissolved, thereby making the first wafer 101 and the second wafer 106 are separated, that is, the first wafer 101 and the second wafer 106 are debonded. After the first wafer 101 and the second wafer 106 are debonded, the first bonding glue layer 105 is removed, thereby forming a structure as shown in Figure 16.

In an example, referring to FIG. 16 , the depth h ₂ of the second blind hole 108 is greater than the depth h ₁ of the first blind hole 104 . In other examples, the depth h ₂ of the second blind hole 108 may be smaller than the depth h ₁ of the first blind hole 104 , which is not limited by the present disclosure.

In the embodiment of the present disclosure, since the first wafer and the second wafer are bonded physically (i.e., temporary bonding glue), after the first blind hole and the second blind hole are independently formed, the debonding method is used. The first wafer and the second wafer can be separated without causing damage to the first wafer and the second wafer. On the one hand, the integrity of the first wafer is ensured, and on the other hand, the debonded second wafer It can be reused during the processing of other first wafers in the same batch, which improves the utilization rate of the second wafer and reduces the manufacturing cost of semiconductor devices.

In some embodiments, as shown in Figure 8 and Figure 17, the above step S200 includes:

Depositing filling material into the first blind hole 104; wherein the filling material covers the second area 101b;

The filling material located on the first wafer 101 is removed to form the first filling structure 205 ; wherein the top surface of the first filling structure 205 is substantially flush with the top surface of the first wafer 101 .

For example, the filling material may be deposited into the first blind hole 104 through a thin film deposition process. During the process of depositing the filling material into the first blind hole 104, part of the filling material covers the second area 101b, and the filling material located on the first wafer 101 is removed by performing a planarization process, thereby forming a structure as shown in Figure 17 The first filling structure 205 is shown.

In an example, the first filling structure 205 includes gaps, that is, the first filling structure 205 is a hollow structure. In another example, the first filling structure 205 completely fills the first blind hole 104 , that is, the first filling structure 205 is a solid structure.

In one example, the top surface of the first filling structure 205 is substantially flush with the top surface of the first wafer 101 . Here, substantially flush includes that the top surface of the first filling structure 205 is completely flush with the top surface of the first wafer 101 , or the distance between the top surface of the first filling structure 205 and the top surface of the first wafer 101 Very small and can be ignored.

It should be noted that during the process of depositing the filling material into the first blind hole 104, voids may appear in the first filling structure 205 due to the influence or limitation of actual process conditions. By setting the top surface of the first filling structure 205 to be substantially flush with the top surface of the first wafer 101, the flatness of the first wafer 101 during processing can be ensured and a relatively flat surface can be provided for subsequent semiconductor processes.

The first filling structure 205 may be an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. The first filling structure 205 may also be a metal material, such as tungsten, copper, aluminum, or titanium. In this example, the first filling structure 205 is metal.

In embodiments of the present disclosure, by depositing the filling material in the first blind hole, the first filling structure can be formed in the first blind hole. Since the top surface of the first filling structure is substantially flush with the top surface of the first wafer, It is beneficial to provide a relatively flat surface for subsequent semiconductor manufacturing processes and ensure the normal progress of subsequent manufacturing processes.

In some embodiments, as shown in FIGS. 17 to 20 , the above step S300 includes:

Sequentially forming a second mask material layer 206' and a second photoresist material layer 107' covering the first wafer 101 and the first filling structure 205;

forming a second photolithography pattern 1071 in the second photoresist material layer 107';

The second mask material layer 206' is etched according to the second photolithography pattern 1071 to form a mask opening 2061 in the second mask material layer 206'.

Exemplarily, a second mask material layer 206' is deposited on the first wafer 101 and the first filling structure 205 through a thin film deposition process. Here, the composition material of the second mask material layer 206' may be the same as that of the first mask material. The constituent materials of the membrane material layer 102' are the same and will not be described again.

Exemplarily, the second photoresist material layer 107' is coated on the second mask material layer 206' through a glue coating process. Here, the composition material of the second photoresist material layer 107' can be the same as the composition material of the first photoresist material layer 103', which will not be described again.

Exemplarily, through an exposure and development process, the second photoresist layer 107 including the second photolithography pattern 1071 is formed, and the bottom of the second photolithography pattern 1071 exposes the second mask material layer 206'. The second photolithography pattern 1071 is used to define the location of the second blind hole 108 .

Exemplarily, through an etching process, the second mask material layer 206' is etched downward along the z-axis direction to form a first mask structure 206 including a mask opening 2061, the bottom of which exposes the first crystal. The circle 101 continues to etch the first wafer 101 downward along the z-axis direction to form a second blind hole 108 in the first wafer 101 . The first mask structure 206 is used to protect the mask opening 2061 during etching to form the second blind hole 108 and reduce the probability of the mask opening 2061 being deformed.

It can be understood that, in the example shown in FIG. 13 , the first mask structure (ie, the second wafer 106 ) can cover the first wafer 101 and the first filling structure (ie, the first bonding structure) through bonding. Glue layer 105). In the example shown in FIG. 20 , the first mask structure 206 may cover the first wafer 101 and the first filling structure 205 by deposition.

In some embodiments, as shown in Figure 8 and Figure 18b, the above step S200 includes:

Form a first filling structure 205′ covering the sidewall of the first blind hole 104 and the bottom of the first blind hole 104, and form a first sub-blind hole based on the topography of the first blind hole 104;

The above step S300 includes:

A first mask structure covering the first wafer 101 and the first sub-blind hole is formed; wherein the first mask structure is substantially flush with the surface relatively far away from the first wafer 101 .

For example, the first filling structure 205' covering the sidewall of the first blind hole 104 and the bottom of the first blind hole 104 can be formed by controlling the process parameters of film deposition, and the first filling structure 205' can be formed based on the topography of the first blind hole 104. Sub-blind hole (not shown in the figure). It can be understood that the first sub-blind hole is located in the first blind hole 104, and the first filling structure 205' is located between the first blind hole 104 and the first sub-blind hole.

The second mask material layer 206' not only covers the second area 101b, but is also located in the first sub-blind hole. The surface of the second mask material layer 206' relatively far away from the first wafer 101 satisfies the preset flatness condition. Here, satisfying the preset flat condition includes: the surface of the second mask material layer 206' relatively far away from the first wafer 101 is parallel to the horizontal plane, or the surface of the second mask material layer 206' relatively far away from the first wafer 101 is parallel to the horizontal plane. Flatness tolerances on a horizontal plane range from -20 nm to 20 nm.

By performing a process similar to Figures 19 and 20, a first mask structure covering the first wafer 101 and the first sub-blind hole can be formed, and the first mask structure is substantially flush with the surface far away from the first wafer 101. .

In some embodiments, at least one of the first blind hole 104 and the second blind hole 108 serves as a light-transmitting structure. For example, after the first mask structure and the first filling structure are removed, at least one of the first blind hole 104 and the second blind hole 108 is used to transmit light. It can be understood that in this example, when at least one of the first blind hole 104 and the second blind hole 108 is used as a light-transmitting structure, there is no need to fill the light-transmitting structure with material.

In some embodiments, as shown in FIG. 16 , after removing the first mask structure and the first filling structure, the above-mentioned manufacturing method further includes: forming a light-transmitting structure in the first blind hole 104; and/or, in the first blind hole 104; A light-transmitting structure is formed in the two blind holes 108 .

For example, a light-transmitting material may be filled into the first blind hole 104 through a thin film deposition process to form a light-transmitting structure in the first blind hole 104; and/or a light-transmitting material may be filled into the second blind hole 108. material to form a light-transmitting structure in the second blind hole 108 . Here, the light-transmitting material may be a light-transmitting material known in the art, and the disclosure is not limited here.

It can be understood that in this example, when the first blind hole 104 is filled with a light-transmitting material, a light-transmitting structure can be formed in the first blind hole 104 , and the light-transmitting structure allows light to pass through. When the light-transmitting material is filled into the second blind hole 108, a light-transmitting structure may be formed in the second blind hole 108, and the light-transmitting structure allows light to pass through.

In some embodiments, as shown in FIG. 16 , after removing the first mask structure and the first filling structure, the above manufacturing method further includes:

A first conductive structure (not shown in the figure) is formed in the first blind hole 104; and/or a second conductive structure (not shown in the figure) is formed in the second blind hole 108.

For example, the first blind hole 104 may be filled with a first conductive material, and the second blind hole 108 may be filled with a second conductive material by including a thin film deposition process.

In one example, the first conductive material and the second conductive material are the same. The first blind hole 104 and the second blind hole 108 may be filled at the same time, or the first blind hole 104 and the second blind hole 108 may be filled successively, which is not limited by the present disclosure. When the first blind hole 104 and the second blind hole 108 are filled at the same time, the manufacturing process can be saved and the manufacturing cycle of the semiconductor device can be shortened.

In another example, the first conductive material and the second conductive material are different. The second conductive material can be filled first and then the first conductive material. For example, after forming the second blind hole and before removing the first filling structure, a second conductive structure is formed in the second blind hole. After the second conductive structure is formed, the first filling structure is removed, and the first conductive structure is formed in the first blind hole.

The constituent materials of the first conductive structure and the second conductive structure include conductive materials, for example, any one of copper, titanium, aluminum, platinum, tungsten, tantalum, titanium nitride, tungsten nitride, tantalum nitride or a combination thereof.

In the embodiment of the present disclosure, after removing the first mask structure and the first filling structure, the first conductive structure is formed in the first blind hole and the second conductive structure is formed in the second blind hole. Since the first blind hole and The actual depth of the second blind hole is closer to the design depth, so that the actual size (ie, the size in the vertical direction) of the first conductive structure and the second conductive structure is closer to the design size, which is beneficial to ensuring that the first conductive structure and the second conductive structure pass through Stability of the signal transmitted by the structure.

In some embodiments, the first filling structure in the first blind hole can be removed by laser irradiation or heat treatment. For example, as shown in FIG. 15 , when the first filling structure is the first bonding glue layer 105 , it can be dissolved and removed by laser irradiation or heating.

In other embodiments, the first filling structure in the first blind hole may be removed through an etching process. For example, referring to FIG. 22 , when the first filling structure is metal 205 , it can be removed through a wet etching process.

In some embodiments, as shown in FIG. 14 , after forming the second blind hole 108 and before removing the first mask structure and the first filling structure, the above manufacturing method further includes:

forming a second filling structure in the second blind hole 108;

A third blind hole is formed that penetrates the second mask structure and the first mask structure and has a bottom located in the first wafer 101; wherein the depth of the third blind hole is different from the depth of the second blind hole 108, and the third blind hole is The depth of the third blind hole is different from the depth of the first blind hole 104; the position of the third blind hole is different from the position of the second blind hole 108; the position of the third blind hole is different from the position of the first blind hole 104.

By performing a manufacturing process similar to the first blind hole and the second blind hole, a third blind hole with a depth different from the first blind hole and the second blind hole can be formed in the first wafer, and the etching of the third blind hole It is carried out independently of the first blind hole and the second blind hole, which is beneficial to protecting the formed first blind hole and the second blind hole. That is to say, even if two or more through silicon holes of different depths need to be formed in the wafer, the stability of the through silicon hole etching process can be ensured by using the manufacturing method in the present disclosure.

The depth of the third blind hole is different from the depth of the second blind hole 108, and the depth of the third blind hole is different from the depth of the first blind hole 104, including: the depth of the third blind hole is greater than the depth of the second blind hole 108, The depth of the third blind hole is greater than the depth of the first blind hole 104; or, the depth of the third blind hole is less than the depth of the second blind hole 108, the depth of the third blind hole is less than the depth of the first blind hole 104; or, the depth of the third blind hole is less than the depth of the first blind hole 104; The depth of the blind hole is greater than the depth of the second blind hole 108, and the depth of the third blind hole is less than the depth of the first blind hole 104; or, the depth of the third blind hole is less than the depth of the second blind hole 108, and the depth of the third blind hole is The depth is greater than the depth of the first blind hole 104 .

It can be understood that by using the manufacturing method of the present disclosure, at least two or more through silicon holes with different depths can be formed on the wafer, while ensuring good process stability of the through silicon holes with different depths.

In some embodiments, the third blind hole is used as a light-transmitting structure. When the third blind hole is used as a light-transmitting structure, there is no need to fill the light-transmitting structure with material.

In some embodiments, after forming the third blind hole, the above manufacturing method further includes: forming a light-transmitting structure in the third blind hole. For example, a light-transmitting material may be filled into the third blind hole through a thin film deposition process to form a light-transmitting structure in the third blind hole, and the light-transmitting structure allows light to pass through.

In some embodiments, after forming the third blind hole, the above manufacturing method further includes: forming a third conductive structure in the third blind hole.

For example, a third conductive material may be filled into the third blind hole to form a third conductive structure in the third blind hole by including a thin film deposition process.

The constituent materials of the third conductive structure include conductive materials, such as any one of copper, titanium, aluminum, platinum, tungsten, tantalum, titanium nitride, tungsten nitride, tantalum nitride or a combination thereof.

In addition, since the etching of the first blind hole, the etching of the second blind hole and the etching of the third blind hole are performed independently, the fabrication of the through silicon via does not need to be performed in a process from deep to shallow. For example, when the first blind hole is etched, the through silicon hole is etched. The depth of the blind hole h ₁ , the depth of the second blind hole h ₂ and the depth of the third blind hole h ₃ satisfy: h ₁ ＜ h ₂ ＜ h ₃ , the first blind hole with the shallowest depth can be formed first, and then the depth The second shallowest blind hole finally forms the third blind hole with the deepest depth. For another example, when the depth h ₁ of the first blind hole, the depth h ₂ of the second blind hole and the depth h ₃ of the third blind hole satisfy: h ₁ > h ₂ > h ₃ , the first blind hole with the deepest depth can be formed first. hole, then a second blind hole with the next shallowest depth is formed, and finally a third blind hole with the shallowest depth is formed. This will help improve the flexibility of the through silicon via manufacturing process. Moreover, the first blind hole, the second blind hole and the third blind hole are all formed through one etching, which is beneficial to ensuring the continuity of the side wall of the first blind hole, the continuity of the side wall of the second blind hole and the third blind hole. The continuity of the side walls is good, that is, the side walls of the first blind hole, the side walls of the second blind hole, and the side walls of the third blind hole are relatively flat. When it is necessary to form a light-transmitting structure or a third conductive structure in the third blind hole, it is beneficial to fill the light-transmitting material or the conductive material.

Obviously, the above-mentioned embodiments are only examples for clear explanation and are not intended to limit the implementation. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. An exhaustive list of all implementations is neither necessary nor possible. The obvious changes or modifications derived therefrom are still within the protection scope of the present invention.

Claims

A method for manufacturing a semiconductor device, including:

forming a first blind via in the first wafer;

forming a first filling structure in the first blind hole;

Forming a first mask structure covering the first wafer and the first filling structure; wherein the first mask structure includes a mask opening;

The first wafer is etched according to the mask opening to form a second blind hole in the first wafer; wherein the depth of the second blind hole is different from the depth of the first blind hole. ;The position of the second blind hole is different from the position of the first blind hole;

After forming the second blind hole, the first mask structure and the first filling structure are removed.
The manufacturing method according to claim 1, wherein the first filling structure includes: a first bonding glue layer; the first mask structure includes: a second wafer; wherein the second wafer includes The mask opening;

Forming a first filling structure in the first blind hole includes:

Coating the first bonding glue layer into the first blind hole;

The forming a first mask structure covering the first wafer and the first filling structure includes:

Align and bond the first wafer and the second wafer; wherein the first bonding glue layer is located between the first wafer and the second wafer.
The manufacturing method according to claim 2, wherein the first wafer includes: a first area and a second area; wherein the first blind hole is located in the first area; the manufacturing method further includes:

While filling the first blind hole with the first bonding glue layer, the first bonding glue layer covering the second area is formed.
The manufacturing method according to claim 2 or 3, wherein the second wafer includes: a third area and a fourth area; wherein the mask opening is located in the fourth area;

Before aligning and bonding the first wafer and the second wafer, the manufacturing method further includes:

Forming a second bonding glue layer covering the third region;

The bonding of the first wafer and the second wafer includes:

The first bonding glue layer and the second bonding glue layer are bonded, so that the first wafer and the second wafer are bonded.
The manufacturing method according to claim 2, wherein removing the first mask structure and the first filling structure after forming the second blind hole includes:

Perform a debonding process on the first wafer and the second wafer to expose the first bonding glue layer;

Remove the first bonding glue layer.
The manufacturing method according to claim 1, wherein the first wafer includes: a first area and a second area; wherein the first blind hole is located in the first area;

Forming a first filling structure in the first blind hole includes:

Depositing a filling material into the first blind hole; wherein the filling material covers the second area;

The filling material located on the first wafer is removed to form the first filling structure; wherein a top surface of the first filling structure is substantially flush with a top surface of the first wafer.
The manufacturing method according to claim 1, wherein forming the first filling structure in the first blind hole includes:

Form the first filling structure covering the sidewall of the first blind hole and the bottom of the first blind hole, and form a first sub-blind hole based on the topography of the first blind hole;

The forming a first mask structure covering the first wafer and the first filling structure includes:

The first mask structure is formed to cover the first wafer and the first sub-blind hole; wherein the first mask structure is substantially flush with a surface relatively far away from the first wafer.
The manufacturing method according to claim 1, wherein forming the first mask structure covering the first wafer and the first filling structure includes:

bonding the first wafer and the second wafer; wherein the first filling structure is located between the first wafer and the second wafer;

The mask opening is formed through the second wafer; wherein the mask opening exposes the first wafer.
The manufacturing method according to claim 8, wherein after bonding the first wafer and the second wafer and before etching the second wafer, the manufacturing method further includes:

Thinning a side of the second wafer relatively away from the first wafer.
The manufacturing method according to claim 1, wherein after forming the second blind hole and before removing the first mask structure and the first filling structure, the manufacturing method further includes:

forming a second filling structure in the second blind hole;

forming a second mask structure covering the first mask structure and the second filling structure;

Form a third blind hole that penetrates the second mask structure and the first mask structure and has a bottom located in the first wafer; wherein the depth of the third blind hole is the same as that of the second blind hole. The depth of the third blind hole is different from the depth of the first blind hole; the position of the third blind hole is different from the position of the second blind hole, and the position of the third blind hole is different. It is different from the position of the first blind hole.