CN117253780A - Glue brushing method for semiconductor wafer - Google Patents
Glue brushing method for semiconductor wafer Download PDFInfo
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- CN117253780A CN117253780A CN202311532806.0A CN202311532806A CN117253780A CN 117253780 A CN117253780 A CN 117253780A CN 202311532806 A CN202311532806 A CN 202311532806A CN 117253780 A CN117253780 A CN 117253780A
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- 239000003292 glue Substances 0.000 title claims abstract description 97
- 239000004065 semiconductor Substances 0.000 title claims abstract description 78
- 238000000034 method Methods 0.000 title claims abstract description 61
- 230000001680 brushing effect Effects 0.000 title claims abstract description 42
- 239000010410 layer Substances 0.000 claims abstract description 112
- 239000012790 adhesive layer Substances 0.000 claims abstract description 38
- 238000005520 cutting process Methods 0.000 claims abstract description 9
- 239000000853 adhesive Substances 0.000 claims abstract description 8
- 230000001070 adhesive effect Effects 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims description 31
- 238000001816 cooling Methods 0.000 claims description 10
- 238000000608 laser ablation Methods 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000007711 solidification Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 4
- 239000011159 matrix material Substances 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 239000002356 single layer Substances 0.000 claims description 4
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000007606 doctor blade method Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000010309 melting process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02016—Backside treatment
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B05—SPRAYING OR ATOMISING IN GENERAL; APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
- B05D—PROCESSES FOR APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
- B05D7/00—Processes, other than flocking, specially adapted for applying liquids or other fluent materials to particular surfaces or for applying particular liquids or other fluent materials
- B05D7/50—Multilayers
- B05D7/56—Three layers or more
- B05D7/58—No clear coat specified
- B05D7/586—No clear coat specified each layer being cured, at least partially, separately
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Life Sciences & Earth Sciences (AREA)
- Wood Science & Technology (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The invention relates to a method for brushing glue on a semiconductor wafer, which is characterized in that a patterned inorganic medium layer is formed on the back surface of the semiconductor wafer in advance before the first glue brushing treatment, and the inorganic medium layer covers a cutting path of the semiconductor wafer, so that a joint interface of the semiconductor wafer and a first glue layer is prevented from being formed at the cutting path, and further, the phenomenon of stripping the glue layer in the cutting process is effectively avoided. And a plurality of first pits are formed on the surface of the inorganic medium layer, and the first adhesive layer formed by the first adhesive brushing treatment is embedded into the opening of the inorganic medium layer and the first pits, so that the joint stability between the first adhesive layer and the semiconductor wafer is effectively improved. And through setting up two-layer full cured glue film and one deck semi-cured glue film, and the setting of second pit and third pit has effectively increased the area of the joint interface between each glue film, and then increases the joint steadiness between each glue film.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for brushing glue on a semiconductor wafer.
Background
Die bonding is also known as Die Bond or Die attach. The die bonding is to bond the wafer in the designated area of the bracket through the colloid to form a thermal path or an electrical path, so as to provide conditions for subsequent wire bonding connection, and the chip mounter cannot perform dispensing on small-size chips along with the smaller and smaller chip size, so that the operation of the traditional die bonding process can be very difficult. The current common practice for solving this problem is to use a wafer back side glue brushing technology, namely a back side glue process, specifically, firstly, glue is coated on the back side of the whole wafer, then the whole wafer is cut into individual chips, and finally, the individual chips coated with the glue are placed on a bearing base and are bonded with the bearing base. At present, the conventional glue brushing process comprises the steps of twice glue brushing, complete solidification after the first glue brushing and semi-solidification after the second glue brushing. The first adhesive layer completely covers the back surface of the wafer, i.e. covers the chip area and the dicing channels of the wafer at the same time, and the adhesive layer is easily peeled off in the subsequent dicing process.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a method for brushing the glue on a semiconductor wafer.
In order to achieve the above purpose, the invention adopts the following technical scheme:
a method for brushing glue of a semiconductor wafer comprises the following steps:
step (1): providing a semiconductor wafer, wherein the semiconductor wafer comprises a plurality of semiconductor chip units which are arranged in a matrix, cutting channels are arranged between adjacent semiconductor chip units, and the semiconductor wafer comprises a front surface and a back surface opposite to the front surface.
Step (2): and depositing an inorganic medium layer on the back surface of the semiconductor wafer.
Step (3): and patterning the inorganic dielectric layer to form an opening in the inorganic dielectric layer corresponding to the area of each semiconductor chip unit, and reserving the inorganic dielectric layer corresponding to the area of the cutting channel.
Step (4): and forming a plurality of first pits on the surface of the inorganic dielectric layer.
Step (5): and performing first glue brushing treatment on the back surface of the semiconductor wafer to form a first glue layer.
Step (6): and performing primary curing treatment on the first adhesive layer to enable the first adhesive layer to be completely cured.
Step (7): and forming a plurality of second pits which are arranged randomly on the completely solidified first adhesive layer.
Step (8): and then, carrying out a second glue brushing treatment on the completely cured first glue layer to form a second glue layer, and carrying out a second curing treatment on the second glue layer to enable the second glue layer to be completely cured.
Step (9): and forming a plurality of third pits which are arranged randomly on the completely solidified second adhesive layer.
Step (10): and then, carrying out a third glue brushing treatment on the completely cured second glue layer to form a third glue layer, and carrying out a semi-curing treatment on the third glue layer to enable the third glue layer to be partially cured.
In the preferred technical scheme, in the step (2), the material of the inorganic dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, and hafnium oxide, and the inorganic dielectric layer has a single-layer structure or a stacked-layer structure.
As a preferable technical scheme, the total thickness of the inorganic medium layer is 1-10 micrometers.
As a preferable embodiment, the first pit, the second pit, and the third pit are formed by a laser ablation process.
As a preferable technical scheme, the specific processes of the first curing treatment and the second curing treatment are as follows: heating to 50-60 ℃, preserving heat for 10-20 minutes, heating to 90-100 ℃, preserving heat for 15-25 minutes, heating to 150-160 ℃, preserving heat for 30-40 minutes, and cooling to 50-60 ℃.
As a preferable technical scheme, the specific process of the semi-solidification treatment is as follows: heating to 50-60 ℃, preserving heat for 10-20 minutes, heating to 120-130 ℃, preserving heat for 20-30 minutes, and cooling to room temperature.
Compared with the prior art, the method for brushing the glue on the semiconductor wafer has the following beneficial effects: in the invention, before the first glue brushing treatment, a patterned inorganic medium layer is formed on the back surface of the semiconductor wafer in advance, and the inorganic medium layer covers the dicing channels of the semiconductor wafer, so that the formation of the joint interface of the semiconductor wafer and the first glue layer at the dicing channels can be avoided, and the peeling phenomenon of the glue layer in the dicing process can be effectively avoided. And a plurality of first pits are formed on the surface of the inorganic medium layer, and the first adhesive layer formed by the first adhesive brushing treatment is embedded into the opening of the inorganic medium layer and the first pits, so that the joint stability between the first adhesive layer and the semiconductor wafer is effectively improved. And through setting up two-layer full cured glue film and one deck semi-cured glue film, and the setting of second pit and third pit has effectively increased the area of the joint interface between each glue film, and then increases the joint steadiness between each glue film.
Drawings
Fig. 1 is a schematic diagram of a front side structure of a semiconductor wafer.
Fig. 2 is a schematic view of a back surface structure of a semiconductor wafer.
Fig. 3 is a schematic view of the back surface structure of a semiconductor wafer after a laser ablation process.
Fig. 4 is a schematic view of the back surface structure of the semiconductor wafer after the second curing process.
Fig. 5 is a schematic view of the back structure of the semiconductor wafer after the third adhesive layer is partially cured.
Detailed Description
For a better understanding of the technical solution of the present invention, the following detailed description of the embodiments of the present invention refers to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Please refer to fig. 1-5. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1 to 5, the present embodiment provides a method for brushing a semiconductor wafer, which includes the following steps:
as shown in fig. 1, step (1): a semiconductor wafer 100 is provided, wherein the semiconductor wafer 100 includes a plurality of semiconductor chip units 101 arranged in a matrix, and dicing channels 102 are provided between adjacent semiconductor chip units 101, and the semiconductor wafer 100 includes a front surface and a back surface opposite to the front surface.
In a specific embodiment, the semiconductor wafer 100 may be a suitable wafer such as a silicon wafer, a germanium wafer, a silicon nitride wafer, a silicon carbide wafer, etc., the semiconductor chip units 101 have functional circuits, and the dicing streets 102 are used to dice the wafer to form the separated semiconductor chip units 101.
As shown in fig. 2, step (2): an inorganic dielectric layer 200 is deposited on the back side of the semiconductor wafer 100. Step (3): the inorganic dielectric layer 200 is patterned, and then an opening 201 is formed in the inorganic dielectric layer 200 in a region corresponding to each semiconductor chip unit, and the inorganic dielectric layer 200 in a region corresponding to the scribe line is remained. Step (4): a plurality of first pits (not shown) are formed on the surface of the inorganic dielectric layer 200.
In a specific embodiment, in the step (2), the material of the inorganic dielectric layer 200 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, and hafnium oxide, the inorganic dielectric layer is in a single-layer structure or a stacked-layer structure, and the deposition process of the inorganic dielectric layer 200 is one or more of PECVD, ALD, thermal oxidation, and magnetron sputtering.
In a specific embodiment, the total thickness of the inorganic dielectric layer 200 is 1-10 micrometers, and preferably, the total thickness of the inorganic dielectric layer 200 is 3-6 micrometers.
In a specific embodiment, the first pit is formed by a laser ablation process, and may have any suitable shape, such as a hemispherical shape, a square shape, an inverted pyramid shape, or an inverted cone shape, for example, when the first pit is a hemispherical shape or an inverted cone shape, a diameter of a circle of the first pit on the surface of the inorganic dielectric layer 200 is 100-300 nm, and a depth of the first pit is 100-300 nm.
In a specific embodiment, alumina is deposited as an inorganic dielectric layer 200 on the semiconductor wafer 100 by an ALD process, the inorganic dielectric layer 200 having a total thickness of 5 microns. Then, patterning is performed by a wet etching process, wherein the etching rate of the inorganic dielectric layer 200 by the wet etching process is far greater than that of the semiconductor wafer 100, so that damage to the silicon wafer can be reduced. An opening 201 is formed in the inorganic medium layer 200 corresponding to the area of each semiconductor chip unit through a wet etching process, the inorganic medium layer 200 corresponding to the area of the dicing channel is reserved, then a plurality of first pits are formed on the surface of the reserved inorganic medium layer 200 through a laser ablation process, the plurality of first pits can be hemispherical, the diameter of a circle of the first pits on the surface of the inorganic medium layer 200 is 200 nanometers, the depth of the first pits is 200 nanometers, and the plurality of first pits are arranged on the surface of the inorganic medium layer 200 randomly.
As shown in fig. 3, step (5): a first glue layer 300 is formed by performing a first glue brushing process on the back surface of the semiconductor wafer 100. Step (6): and performing a first curing treatment on the first adhesive layer 300, so that the first adhesive layer 300 is completely cured. Step (7): a plurality of randomly arranged second pits (not shown) are formed on the completely cured first adhesive layer 300.
In a specific embodiment, the second pit is formed by a laser ablation process.
In a specific embodiment, the specific processes of the first curing treatment are as follows: heating to 50-60 ℃, preserving heat for 10-20 minutes, heating to 90-100 ℃, preserving heat for 15-25 minutes, heating to 150-160 ℃, preserving heat for 30-40 minutes, and cooling to 50-60 ℃.
In a specific embodiment, the semiconductor wafer 100 obtained in the step (4) is fixed on a glue brushing machine, the first glue layer 300 is formed by a doctor blade through a doctor blade coating process, and then the first glue layer 300 is subjected to a first curing process, so that the first glue layer 300 is completely cured, and the specific process of the first curing process is as follows: heating to 60 ℃, preserving heat for 20 minutes, heating to 100 ℃, preserving heat for 25 minutes, heating to 160 ℃ finally, preserving heat for 30 minutes, and reducing the temperature to 50 ℃, so that a fully cured compact first adhesive layer 300 can be obtained through the curing treatment, the first adhesive layer 300 fills the opening 201 and the first pits, a plurality of randomly arranged second pits (not shown) are formed on the fully cured first adhesive layer 300 through a laser ablation process, and the shape and the size of the second pits are the same as those of the first pits.
As shown in fig. 4, step (8): and then, performing a second glue brushing treatment on the first glue layer 300 which is completely cured to form a second glue layer 400, and performing a second curing treatment on the second glue layer 400 to completely cure the second glue layer 400. Step (9): a plurality of randomly arranged third pits (not shown) are formed on the second adhesive layer 400 that is completely cured.
In a specific embodiment, the third pit is formed by a laser ablation process.
In a specific embodiment, the specific processes of the second curing treatment are as follows: heating to 50-60 ℃, preserving heat for 10-20 minutes, heating to 90-100 ℃, preserving heat for 15-25 minutes, heating to 150-160 ℃, preserving heat for 30-40 minutes, and cooling to 50-60 ℃.
In a specific embodiment, the semiconductor wafer 100 obtained in the step (7) is fixed on a glue brushing machine, a second glue layer 400 is formed on the first glue layer 300 by using a doctor blade through a doctor blade coating process, and then a second curing process is performed on the second glue layer 400, so that the second glue layer 400 is completely cured, and the specific process of the second curing process is as follows: heating to 60 ℃, preserving heat for 20 minutes, heating to 100 ℃, preserving heat for 25 minutes, heating to 160 ℃ finally, preserving heat for 30 minutes, and reducing the temperature to 50 ℃, so that a fully cured compact second adhesive layer 400 can be obtained through the curing treatment, the second adhesive layer 400 is filled with the second pits, a plurality of randomly arranged third pits (not shown) are formed on the fully cured second adhesive layer 400 through a laser ablation process, and the shape and the size of the third pits are the same as those of the second pits.
As shown in fig. 5, step (10): and then, performing a third brushing treatment on the second adhesive layer 400 which is completely cured to form a third adhesive layer 500, and performing a semi-curing treatment on the third adhesive layer 500 to partially cure the third adhesive layer 500.
In a specific embodiment, the specific process of the semi-curing treatment is as follows: heating to 50-60 ℃, preserving heat for 10-20 minutes, heating to 120-130 ℃, preserving heat for 20-30 minutes, and cooling to room temperature.
In a specific embodiment, the semiconductor wafer 100 obtained in the step (9) is fixed on a glue brushing machine, a third glue layer 500 is formed on the second glue layer 400 by using a doctor blade through a doctor blade coating process, and then a semi-curing treatment is performed on the third glue layer 500, so that the third glue layer 500 is partially cured, and the specific process of the semi-curing treatment is as follows: heating to 55 ℃, preserving heat for 15 minutes, heating to 120 ℃ again, preserving heat for 30 minutes, then cooling to room temperature, and obtaining a partially cured third adhesive layer 500 through the semi-curing treatment, wherein the third adhesive layer 500 fills the third pits.
In a specific embodiment, the materials of the first, second and third adhesive layers are all insulating adhesives.
In the subsequent manufacturing process, the glued semiconductor wafer may be cut along the dicing streets 102 to form a plurality of discrete semiconductor chip units 101, and then the individual semiconductor chip units 101 may be glued to the carrier substrate by a glue melting process to soften the third glue layer.
In other embodiments, the present invention provides a method for brushing a semiconductor wafer, which includes the following steps:
step (1): providing a semiconductor wafer, wherein the semiconductor wafer comprises a plurality of semiconductor chip units which are arranged in a matrix, cutting channels are arranged between adjacent semiconductor chip units, and the semiconductor wafer comprises a front surface and a back surface opposite to the front surface.
Step (2): and depositing an inorganic medium layer on the back surface of the semiconductor wafer.
Step (3): and patterning the inorganic dielectric layer to form an opening in the inorganic dielectric layer corresponding to the area of each semiconductor chip unit, and reserving the inorganic dielectric layer corresponding to the area of the cutting channel.
Step (4): and forming a plurality of first pits on the surface of the inorganic dielectric layer.
Step (5): and performing first glue brushing treatment on the back surface of the semiconductor wafer to form a first glue layer.
Step (6): and performing primary curing treatment on the first adhesive layer to enable the first adhesive layer to be completely cured.
Step (7): and forming a plurality of second pits which are arranged randomly on the completely solidified first adhesive layer.
Step (8): and then, carrying out a second glue brushing treatment on the completely cured first glue layer to form a second glue layer, and carrying out a second curing treatment on the second glue layer to enable the second glue layer to be completely cured.
Step (9): and forming a plurality of third pits which are arranged randomly on the completely solidified second adhesive layer.
Step (10): and then, carrying out a third glue brushing treatment on the completely cured second glue layer to form a third glue layer, and carrying out a semi-curing treatment on the third glue layer to enable the third glue layer to be partially cured.
According to an embodiment of the present invention, in the step (2), the material of the inorganic dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, and hafnium oxide, and the inorganic dielectric layer has a single-layer structure or a stacked-layer structure.
According to one embodiment of the invention, the inorganic dielectric layer has a total thickness of 1-10 microns.
According to one embodiment of the present invention, the first pit, the second pit, and the third pit are formed by a laser ablation process.
According to one embodiment of the present invention, the specific processes of the first curing treatment and the second curing treatment are: heating to 50-60 ℃, preserving heat for 10-20 minutes, heating to 90-100 ℃, preserving heat for 15-25 minutes, heating to 150-160 ℃, preserving heat for 30-40 minutes, and cooling to 50-60 ℃.
According to one embodiment of the invention, the specific process of the semi-solidification treatment is as follows: heating to 50-60 ℃, preserving heat for 10-20 minutes, heating to 120-130 ℃, preserving heat for 20-30 minutes, and cooling to room temperature.
In the invention, before the first glue brushing treatment, a patterned inorganic medium layer is formed on the back surface of the semiconductor wafer in advance, and the inorganic medium layer covers the dicing channels of the semiconductor wafer, so that the formation of the joint interface of the semiconductor wafer and the first glue layer at the dicing channels can be avoided, and the peeling phenomenon of the glue layer in the dicing process can be effectively avoided. And a plurality of first pits are formed on the surface of the inorganic medium layer, and the first adhesive layer formed by the first adhesive brushing treatment is embedded into the opening of the inorganic medium layer and the first pits, so that the joint stability between the first adhesive layer and the semiconductor wafer is effectively improved. And through setting up two-layer full cured glue film and one deck semi-cured glue film, and the setting of second pit and third pit has effectively increased the area of the joint interface between each glue film, and then increases the joint steadiness between each glue film.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (6)
1. A method for brushing glue on a semiconductor wafer is characterized in that: the method for brushing the glue of the semiconductor wafer comprises the following steps:
step (1): providing a semiconductor wafer, wherein the semiconductor wafer comprises a plurality of semiconductor chip units which are arranged in a matrix, cutting channels are arranged between adjacent semiconductor chip units, and the semiconductor wafer comprises a front surface and a back surface opposite to the front surface;
step (2): depositing an inorganic medium layer on the back surface of the semiconductor wafer;
step (3): patterning the inorganic dielectric layer to form an opening in the inorganic dielectric layer corresponding to the area of each semiconductor chip unit, and reserving the inorganic dielectric layer corresponding to the area of the cutting channel;
step (4): forming a plurality of first pits on the surface of the inorganic dielectric layer;
step (5): performing first glue brushing treatment on the back surface of the semiconductor wafer to form a first glue layer;
step (6): performing primary curing treatment on the first adhesive layer to enable the first adhesive layer to be completely cured;
step (7): forming a plurality of randomly arranged second pits on the completely cured first adhesive layer;
step (8): then, performing a second glue brushing treatment on the completely cured first glue layer to form a second glue layer, and performing a second curing treatment on the second glue layer to enable the second glue layer to be completely cured;
step (9): forming a plurality of third pits which are randomly arranged on the completely solidified second adhesive layer;
step (10): and then, carrying out a third glue brushing treatment on the completely cured second glue layer to form a third glue layer, and carrying out a semi-curing treatment on the third glue layer to enable the third glue layer to be partially cured.
2. The method for brushing the adhesive on the semiconductor wafer according to claim 1, wherein the method comprises the following steps: in the step (2), the material of the inorganic dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, and hafnium oxide, and the inorganic dielectric layer has a single-layer structure or a stacked-layer structure.
3. The method for brushing the semiconductor wafer according to claim 2, wherein: the total thickness of the inorganic dielectric layer is 1-10 micrometers.
4. The method for brushing the adhesive on the semiconductor wafer according to claim 1, wherein the method comprises the following steps: the first, second, and third pits are formed by a laser ablation process.
5. The method for brushing the adhesive on the semiconductor wafer according to claim 1, wherein the method comprises the following steps: the specific processes of the first curing treatment and the second curing treatment are as follows: heating to 50-60 ℃, preserving heat for 10-20 minutes, heating to 90-100 ℃, preserving heat for 15-25 minutes, heating to 150-160 ℃, preserving heat for 30-40 minutes, and cooling to 50-60 ℃.
6. The method for brushing the adhesive on the semiconductor wafer according to claim 1, wherein the method comprises the following steps: the specific process of the semi-solidification treatment comprises the following steps: heating to 50-60 ℃, preserving heat for 10-20 minutes, heating to 120-130 ℃, preserving heat for 20-30 minutes, and cooling to room temperature.
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| CN202311532806.0A CN117253780B (en) | 2023-11-17 | 2023-11-17 | Glue brushing method for semiconductor wafer |
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| CN202311532806.0A CN117253780B (en) | 2023-11-17 | 2023-11-17 | Glue brushing method for semiconductor wafer |
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| CN117253780A true CN117253780A (en) | 2023-12-19 |
| CN117253780B CN117253780B (en) | 2024-01-23 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070080324A (en) * | 2006-02-07 | 2007-08-10 | 삼성전자주식회사 | Attaching and stacking method of semiconductor chip using polyimide layer with adhesive strength |
| CN102184872A (en) * | 2011-04-08 | 2011-09-14 | 嘉盛半导体(苏州)有限公司 | Semiconductor packaging bonding process |
| JP2017212345A (en) * | 2016-05-25 | 2017-11-30 | ラピスセミコンダクタ株式会社 | Semiconductor manufacturing device, and semiconductor manufacturing method |
| CN111524815A (en) * | 2020-03-26 | 2020-08-11 | 江苏长电科技股份有限公司 | Glue brushing process method for semiconductor wafer |
| WO2023213085A1 (en) * | 2022-05-05 | 2023-11-09 | 湖北江城芯片中试服务有限公司 | Method for manufacturing semiconductor device |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070080324A (en) * | 2006-02-07 | 2007-08-10 | 삼성전자주식회사 | Attaching and stacking method of semiconductor chip using polyimide layer with adhesive strength |
| CN102184872A (en) * | 2011-04-08 | 2011-09-14 | 嘉盛半导体(苏州)有限公司 | Semiconductor packaging bonding process |
| JP2017212345A (en) * | 2016-05-25 | 2017-11-30 | ラピスセミコンダクタ株式会社 | Semiconductor manufacturing device, and semiconductor manufacturing method |
| CN111524815A (en) * | 2020-03-26 | 2020-08-11 | 江苏长电科技股份有限公司 | Glue brushing process method for semiconductor wafer |
| WO2023213085A1 (en) * | 2022-05-05 | 2023-11-09 | 湖北江城芯片中试服务有限公司 | Method for manufacturing semiconductor device |
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