JP3706492B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a chip size package and a manufacturing method thereof. A chip size package (Chip Size Package) is also called a CSP, and is a generic name of packages that are equal to or slightly larger than the chip size, and is a package intended for high-density mounting. The present invention relates to improvement of moisture resistance of CSP.
[0002]
[Prior art]
Conventionally, in this field, generally called a BGA (Ball Grid Array), a structure having a plurality of solder balls arranged in a plane, called a fine pitch BGA, the BGA ball pitch is made narrower and the outer shape is reduced. A structure close to the chip size is known.
[0003]
Recently, there is a wafer CSP described in “Nikkei Microdevice”, August 1998, pages 44-71. This wafer CSP is basically a CSP in which wiring and array-like pads are formed by a wafer process (pre-process) before dicing a chip. With this technology, it is expected that the wafer process and the package process (post-process) are integrated, and the package cost can be greatly reduced.
[0004]
The types of wafer CSP include a sealing resin type and a rewiring type. The sealing resin mold has a structure in which the surface is covered with a sealing resin as in a conventional package, and a metal post is formed on the wiring layer on the chip surface and the periphery thereof is solidified with the sealing resin.
[0005]
Generally, when a package is mounted on a printed circuit board, it is said that the stress generated by the difference in thermal expansion coefficient from the printed circuit board is concentrated on the metal post. However, in the resin-encapsulated type, the metal post becomes longer, so the stress is dispersed. It is thought to be done.
[0006]
On the other hand, the rewiring type has a structure in which rewiring is formed without using sealing resin, as shown in FIG. That is, the Al electrode 52, the wiring layer 53, and the insulating layer 54 are laminated on the surface of the chip 51, the metal post 55 is formed on the wiring layer 53, and the solder ball 56 is formed thereon. The wiring layer 53 is used as rewiring for arranging the solder balls 56 in a predetermined array on the chip.
[0007]
In the sealing resin mold, the metal post is made as long as about 100 μm and is reinforced with the sealing resin, whereby high reliability can be obtained. However, the process of forming the sealing resin needs to be performed using a mold in a subsequent process, and the process becomes complicated.
[0008]
On the other hand, in the rewiring type, the process is relatively simple, and there is an advantage that most processes can be performed by a wafer process. However, it is necessary to relieve stress and improve reliability by some method.
[0009]
11 omits the wiring layer 53 of FIG. 10 and forms an opening through which the Al electrode 52 is exposed, and a barrier metal 58 is formed between the metal post 55 and the aluminum electrode 52 in the opening. At least one layer is formed, and a solder ball 56 is formed on the metal post 55.
[0010]
[Problems to be solved by the invention]
However, in FIG. 10, a polyimide resin is applied so as to completely cover the metal post 55, the upper surface is polished after curing, the head of the metal post is exposed, and a solder ball is formed on the exposed portion. Then, dicing together with this polyimide resin was made into individual chips.
[0011]
Therefore, the side surface exposed by dicing has an interface between an insulating layer (for example, a BPSG film) formed under the Al electrode 52 and an insulating resin layer, and the hygroscopicity of the insulating layer is high. Intruded and the device deteriorated.
[0012]
Further, the insulating resin layer 54 and the Si3N4 film made of resin, the insulating resin layer 54 and the SiO2 film, etc. have different thermal expansion coefficients, so that moisture or the like enters the interface, and the insulating resin layer may peel off. there were.
[0013]
The present invention solves the above problems.
[0014]
[Means for Solving the Problems]
The present invention has been made in view of the above problems. First, a first groove provided around a chip and reaching a semiconductor substrate constituting the chip;
A first insulating resin layer filling the first groove;
This is solved by providing a dicing line that is separated into individual chips by the second groove formed in the first insulating resin layer of the first groove.
[0015]
The first insulating resin layer is embedded in the first groove, and the insulating resin layer r and the passivation film, the passivation film and the interlayer insulating film, or lower layers are formed by dicing with a width narrower than the first groove. Can be protected by the insulating resin layer R. Therefore, improvement in moisture resistance and environmental resistance as a product can be realized.
Second, the problem can be solved by providing a wiring layer below the metal post, and can also be applied to a CSP employing the wiring layer.
Thirdly, the first insulating resin layer and the second insulating resin layer are made of the same material and can be covered with the first insulating resin layer including the first groove. In addition, the wafer strength due to the formation of the first groove can be maintained by embedding the first insulating resin layer.
[0016]
Fourth, the first groove can be solved by forming the semiconductor substrate by being half-cut by dicing, and can be greatly simplified as compared with the formation of the first groove by etching.
[0017]
Fifth, located around the chip including the wiring layer, forming a first groove for half-cutting the wafer,
Covering the wafer surface including the first insulating layer, the wiring layer, the metal post and the first groove with an insulating layer made of resin;
The problem is solved by leaving the insulating layer formed in the first groove and full-cutting the wafer.
[0018]
Sixth, the first groove is solved by forming it so as to reach the semiconductor substrate constituting the wafer.
[0019]
By forming the first groove and embedding the first insulating resin layer therein, the strength of the entire wafer can be maintained. Further, as shown in FIG. 9, the side surface of the first groove and the side surface after dicing Since the first insulating resin layer remains in between, the interface generated by the conventional dicing is covered with the first insulating resin layer.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of the present invention will be described.
[0021]
In FIG. 9, reference numeral 1 is the uppermost metal (portion that also functions as a bonding pad) portion of a normal wire bonding type IC chip. An interlayer insulating film to be formed is indicated by reference numeral 2.
[0022]
In the lower layer of the contact hole C, a plurality of metals are formed, and are in contact with, for example, a transistor (a MOS type transistor or a BIP type transistor), a diffusion region, a poly-Si gate, or poly-Si.
[0023]
Here, although the present embodiment has been described in the MOS type, it goes without saying that the present embodiment can also be implemented by BIP.
[0024]
This structure is an IC generally called single layer metal, double layer metal,.
[0025]
That is, although not shown in the figure, as the number of layers increases, that is, two layers, three layers, etc., the interface between the metal and the insulating layer, and the insulating layer and another insulating layer formed above and below the lower layer of the interlayer insulating film 2 Yes, this interface is exposed in a first groove to be described later.
[0026]
Further, the passivation film is indicated by reference numeral 3. Here, the passivation film 3 is made of Si nitride film, epoxy resin, polyimide, or the like, and further, an insulating resin layer r is coated thereon. Since this insulating resin layer r can realize flatness as will be described later, the wiring layer 7 can be made flat, and the height of the solder balls is made constant. In particular, when a shrink resin with a sheet is used, when the film before curing is pressed with a plate-shaped pressurizing device, the height of the metal post 8 heads becomes uniform, so all metal post heads are pressed. Since it can contact | abut to a part, metal exposure with high precision is attained. Details will be explained in the process.
A Ti nitride film 5 is formed on the Al electrode 1.
[0027]
In the passivation film 3 and the insulating resin layer r, an opening K exposing the Ti nitride film 5 is formed, and a Cu thin film layer 6 is formed as a plating electrode (seed layer) of the wiring layer 7 here. On this, a wiring layer 7 formed by Cu plating is formed.
[0028]
A resin layer R made of resin is formed on the entire surface of the chip including the wiring layer 7. However, although omitted in the drawing, a Si 3 N 4 film may be provided at the interface between the resin layer R and the wiring layer 7 and between the resin layer R and the metal post 8.
[0029]
The resin layer R can be implemented as long as it is a thermosetting or thermoplastic resin, and an amic acid film, a polyimide resin, or an epoxy resin is particularly preferable as the thermosetting resin. Moreover, if it is a thermoplastic resin, a thermoplastic polymer (Hitachi Chemical: Hymal) etc. are preferable. The amic acid film has a shrinkage rate of 30 to 50%.
Here, the resin R is prepared using a liquid amic acid as a main material, and is spun on the entire surface of the wafer. The thickness is about 20 to 60 μm. Thereafter, the resin R is polymerized by a thermosetting reaction. The temperature is 300 ° C or higher. However, a resin composed of an amic acid before thermosetting becomes active under the above temperature, reacts with Cu, and has a problem of deteriorating its interface. However, the reaction with Cu can be prevented by coating the surface of the wiring layer with a Si3N4 film. Here, the film thickness of the Si3N4 film is about 1000 to 3000 mm.
[0030]
The Si3N4 film is an insulating film having an excellent barrier property, and the SiO2 film is inferior to the Si3N4 film in the barrier property. However, when the SiO2 film is used, it is necessary to make the film thickness thicker than the Si3N4 film. Further, since the Si3N4 film can be formed by the plasma CVD method, its step coverage is excellent and preferable. Further, since the resin layer R is coated after the metal post 8 is formed, the formation of the Si3N4 film not only prevents the reaction between the wiring layer 7 made of Cu and the resin layer mainly composed of amic acid, but also Cu The reaction between the metal post 8 made of the resin layer R and the resin layer R mainly composed of amic acid can also be prevented.
[0031]
The resin R shrinks during curing when the resin layer R in a fluid state before curing is cured, and its film thickness is greatly reduced as shown in FIG. Therefore, the surface of the resin layer R is located at the lower end of the head of the metal post 8 and the metal post 8 is exposed. Therefore, it is not necessary to scrape the resin layer R and expose the head. Further, evenly exposing the head in this polishing step requires very difficult control, but it can be easily exposed by contraction of the resin.
[0032]
In this step, of course, a resin R having a small shrinkage rate may be applied and polished to expose the head of the metal post 8 after curing.
[0033]
Therefore, the head of the metal post 8 is exposed at the end of the wiring layer 7, and a barrier metal can be formed on the head of the metal post 8. In particular, here, Ni10 and Au11 are formed by electroless plating.
[0034]
When a solder ball is formed directly on the metal post 8 made of Cu, the connection strength with the solder ball deteriorates due to oxidized Cu. Further, when Au is formed directly to prevent oxidation, Au is diffused, so Ni is inserted therebetween. Ni prevents oxidation of Cu, and Au prevents oxidation of Ni. Therefore, deterioration of the solder ball and strength are suppressed.
[0035]
A solder ball 12 is formed on the head of the metal post 8.
[0036]
Here, the difference between the solder ball and the solder bump will be described. As the solder balls, ball-shaped solder is prepared separately and fixed to the metal posts 8. The solder bumps are formed by electrolytic plating through the wiring layers 7 and the metal posts 8. The solder bump is initially formed as a film having a thickness, and is formed into a spherical shape by post heat treatment.
[0037]
Here, since the seed layer is removed in the step of FIG. 6, electrolytic plating cannot be employed, and actually solder balls are prepared.
[0038]
Finally, a first groove indicated by TC is formed around each chip prepared in a wafer state, and an insulating resin layer is embedded in the groove. Here, the same layer as the resin layer R is formed to simplify the process, but it is not necessary to be the same if the simplification of the process is not taken into consideration.
[0039]
The groove TC and the resin layer are features of the present invention, and are fully cut by a dicing blade DC that is narrower than the first groove TC. In other words, a resin layer is disposed at least between the first groove TC reaching the semiconductor substrate and the full cut line DL, and can cover the interface edge of each layer causing moisture resistance deterioration, thereby preventing element deterioration. Become.
[0040]
Generally, the wafer has a thickness of 200 to 300 μm. Further, as described above, the first groove TC only needs to reach the semiconductor substrate (Si substrate) from the substrate surface of FIG. 8, and considering the thickness of the wafer, the depth of the groove is 1 from the Si substrate. About ~ 100 μm is preferable.
[0041]
Next, the manufacturing method of the structure of FIG. 9 will be described more simply than FIG.
[0042]
First, a semiconductor substrate (wafer) on which an LSI having an Al electrode 1 is formed is prepared. Here, as described above, in the IC of the first layer metal, the second layer metal,..., For example, the source electrode and drain electrode of the transistor are formed as the first layer metal, and the Al electrode 1 in contact with the drain electrode is the second layer metal. It is formed as metal.
[0043]
Here, after forming the opening C of the interlayer insulating film 2 from which the drain electrode is exposed, an electrode material mainly made of Al and a Ti nitride film 5 are formed on the entire surface of the wafer, and the Al electrode 1 and the nitride are formed using a photoresist as a mask. The Ti film 5 is dry etched into a predetermined shape.
[0044]
Here, unlike the case where the passivation film 3 is formed and then the barrier metal is formed from above the opening C which has been opened, the TiN film as the barrier metal can be formed at one time with the photoresist, and the number of processes can be simplified. Is possible.
[0045]
The Ti nitride film 5 functions as a barrier metal for a Cu thin film layer 6 to be formed later. Moreover, attention is paid to the fact that the Ti nitride film is effective as an antireflection film. That is, it is also effective for preventing halation of a resist used in patterning. In order to prevent halation, a minimum of about 1200 to 1300 mm is required, and in order to combine this with the function of a barrier metal, about 2000 to 3000 mm is preferable. If it is formed thicker than this, stress generated due to the Ti nitride film will occur.
[0046]
Further, after the Al electrode 1 and the Ti nitride film 5 are patterned, the entire surface is covered with the passivation film 3. Here, a Si3N4 film is employed as the passivation film, but polyimide or the like is also possible. (See Figure 1 above)
Subsequently, the surface of the passivation film 3 is covered with an insulating resin layer r. Here, a positive type photosensitive polyimide film is employed as the insulating resin layer, and the insulating resin layer is covered with about 3 to 5 μm. Then, an opening K is formed.
The use of this photosensitive polyimide film eliminates the need for forming a photoresist by separately forming a photoresist in the patterning of the opening K in FIG. Can be simplified. Of course, photoresist is also possible. Moreover, this polyimide film is also used for the purpose of planarization. That is, in order for the height of the solder ball 12 to be uniform in all regions, the height of the metal post 8 needs to be uniform in all regions, and the wiring layer 7 also needs to be formed flat and with high accuracy. . Therefore, since the polyimide resin is applied and the resin has fluidity with a certain viscosity, the surface is flattened by leaving it for a desired time before curing.
[0047]
Here, the Al electrode 1 also serves as an external connection pad of the LSI, and is a portion that functions as a wire bonding pad when not formed as a chip size package composed of solder balls (solder bumps). (See Figure 2 above)
Subsequently, a Cu thin film layer 6 is formed on the entire surface. The Cu thin film layer 6 later becomes a plating electrode for the wiring layer 7 and is formed to a thickness of about 1000 to 2000 mm by sputtering, for example.
[0048]
Subsequently, for example, a photoresist layer PR1 is applied to the entire surface, and the photoresist PR1 corresponding to the wiring layer 7 is removed. (See Figure 3 above)
Subsequently, a wiring layer 7 is formed using the Cu thin film layer 6 exposed in the opening of the photoresist PR1 as a plating electrode. The wiring layer 7 needs to be formed as thick as about 2 to 5 μm in order to ensure mechanical strength. Although the plating method is used here, it may be formed by vapor deposition or sputtering.
[0049]
Thereafter, the photoresist layer PR1 is removed. (See Figure 4 above)
Subsequently, a photoresist exposing a region where the metal post 8 is to be formed is formed, and a Cu metal post 8 is formed on the exposed portion by electrolytic plating. This also uses the Cu thin film layer 6 as a plating electrode. This metal post is formed to a height of about 30 to 40 μm.
[0050]
Again, sputtering is conceivable as a method other than electrolytic plating.
[0051]
Here, there are various timings for forming the first groove TC, but the first timing may be after the formation of the metal post. Here, if the photoresist PR2 is formed so that the line of the first groove TC is exposed, dicing can be performed along the exposed portion of the TC. Further, if a photoresist that exposes only the first trench TC is separately formed, it can also be formed by etching.
[0052]
Subsequently, the photoresist is removed, and the Cu thin film layer 6 is removed using the wiring layer 7 as a mask. (See Figure 6 above)
Although the following steps are omitted in the drawing, the Si 3 N 4 film may be deposited on the entire surface including the wiring layer 7 and the metal post 8 by plasma CVD.
[0053]
This is because the uncured resin R and Cu formed in a later process react with heat. Therefore, there is a problem that this interface deteriorates. Therefore, it is necessary to cover the wiring layer 7 and the metal post 8 with this Si3N4 film. Of course, the Si3N4 film can be omitted if the interface does not deteriorate.
[0054]
If the Si 3 N 4 film is formed after the metal post 8 is formed, the wiring layer 7 and the metal post 8 can be covered. Further, it is necessary to protect the exposed side surface M together with patterning, but here, since both sides are patterned and the Si3 N4 film is coated, the side surface M is also protected together.
[0055]
As described above, the formation timing of the first trench TC may be after the Si3N4 film is formed.
[0056]
That is, since the entire surface is protected by the Si3N4 film, the first groove TC can be diced or etched in this state. Since the Si3N4 film is formed on the entire surface of the wafer, the oxidation of the metal post 8 can be prevented.
[0057]
Even when the Si3N4 film is not provided, the first groove TC needs to be formed before the resin layer R is covered because the resin layer R needs to be embedded in the first groove.
[0058]
Subsequently, the resin layer R is applied to the entire surface.
[0059]
This resin is fluid at first, and its film thickness is greatly reduced when the thermosetting reaction is completed.
[0060]
Since this resin has fluidity, flatness can be realized before curing, and because the film thickness is reduced, it is positioned at the lower end from the metal post head.
[0061]
Further, the insulating resin layers R and r have the following merits.
In general, when a viscous resin is applied with a dispenser, there is a problem that bubbles are taken in even if defoaming occurs. If sintering is performed with air bubbles taken in, there is a problem that the air bubbles burst due to a future process or use of a high temperature atmosphere on the user side.
[0062]
In this step, the viscosity is adjusted so that the film can be applied by spin-on and formed into a film thickness of about 20 to 30 μm by one spin. As a result, bubbles larger than this film thickness bounce off and disappear because the film thickness is thin. Also, bubbles smaller than this film thickness are blown out together with the resin blown to the outside by spin-on centrifugal force, and a film without bubbles can be formed.
[0063]
Further, the insulating resin layer R requires a film thickness of about 50 μm. In this case, the above-described principle can be adopted, and the insulating resin layer R can be formed by applying a plurality of times by spin-on and removing bubbles.
[0064]
Of course, you may apply | coat with a dispenser, without employ | adopting spin-on.
[0065]
Furthermore, the point of this insulating resin layer R is to shrink during curing. Generally, the resin shrinks to some extent after being cured. However, the insulating resin layer R contracts during baking, and the surface of the insulating resin layer R is positioned at the lower end than the head of the metal post 8. Therefore, since the head of the metal post 8 is exposed, the solder ball can be fixed.
[0066]
Further, in order to increase the strength of the solder ball, it is necessary to increase the exposure rate including the side surface of the metal post 8, but this can also be controlled by controlling the coating amount of the insulating resin layer R. it can.
[0067]
In addition, after curing, an extremely thin film may remain on the head of the metal post 8, but in this case, the surface may be simply polished or plasma ashed. In particular, since the height of the metal posts is uniform as described above, all the heads can be cleaned by using a flat polishing plate.
[0068]
Alternatively, after the insulating resin layer R is coated, it may be semi-cured to such an extent that it can be polished, polished to the vicinity of the head of the metal post 8, and then completely cured. In this case, since only an extremely thin film remains on the head of the metal post 8, even if the shrinkage rate of the insulating resin layer R is small, the metal post can be exposed by the shrinkage of the insulating resin layer. In other words, since the film thickness that can be disposed on the metal post 8 is determined by the shrinkage rate of the resin, if the metal post is exposed by determining whether or not to polish according to the film thickness, and how much to polish. Good.
[0069]
When the Si3N4 film is formed, the Si3N4 film is formed on the head of the metal post. In this case, the Si3N4 film is removed by wet etching, dry etching or polishing.
[0070]
Further, Ni 10 and Au are plated on the exposed metal post 8. Here, since the Cu thin film layer 6 is removed using the wiring layer 7 as a mask, electroless plating is employed, and Ni is formed with a thickness of about 1 μm and Au11 with a thickness of about 5000 mm.
[0071]
As described with reference to FIG. 16, when the insulating resin layer is applied up to the upper layer of the metal post head and polished, it is very difficult to cue the metal post. Also, since Au is the uppermost layer with a film thickness of about 5000 mm, if flat polishing is not realized, one post has Au, and another post has an insulating resin layer over Au, Another post creates a state where Au has been removed. In other words, since it also serves to oxidize Ni, there are places where the solder balls are fixed, weak, and completely impossible.
[0072]
In the present invention, since the metal post 8 is exposed, the barrier metals 10 and 11 can be formed with high accuracy, and the adhesion of the solder balls 12 is improved.
[0073]
The resin layer R has been described as a shrinkable type, but may be polished as described above. That is, the metal post 8 may be completely covered with the resin layer R and then polished until the metal post 8 is exposed. In this polishing process, since the resin layer R fills the first groove, cracks and the like can be prevented. (See Figure 7 above)
Further, although not shown in the drawing, the wafer surface is covered with a protective sheet and back-grinded as shown by an arrow to reduce the thickness of the wafer.
[0074]
Although not shown in the figure, the back surface of the wafer may be coated with a resin after back grinding. This is to prevent the wafer from being chipped due to scratches generated during back grinding, and at the same time to prevent the wafer from warping due to the shrinkage of the insulating resin layer R.
[0075]
Therefore, since the resin layer R having large shrinkage is on the surface, it is necessary to provide the resin layer R having the same thickness on the back surface. In addition, the insulating resin layer r is also considered, and it is necessary to have a film thickness that is at least as large as or thicker than that of the resin layer R, and approximately equal to the maximum resin layer R and resin layer r. Further, since dicing is performed thereafter, the protection resin formed on the back surface can be left as a product in consideration of chip chip protection and warping when the chip size is large. (See Figure 8 above)
Finally, the prepared solder balls 12 are aligned and mounted and reflowed. Then, the semiconductor substrate is divided into chips along a scribe line by a dicing process to complete a chip size package.
[0076]
Here, the timing for melting the solder is before dicing.
[0077]
This dicing is a feature of the present invention. A dicing blade DC having a width smaller than that of the first groove TC is prepared, and this is used to perform a full cut substantially at the center of the first groove. Since the first groove TC is realized by, for example, a half cut reaching the semiconductor substrate, the interface end portion of each layer formed from the semiconductor substrate to the upper layer is protected by the resin layer R and becomes a CSP. .
[0078]
As described above, the present invention has been described with the rewiring type.
[0079]
In the present application, the film F with the sheet 30 may be adopted as the insulating resin layer R.
[0080]
This will be briefly described below. FIG. 12 shows a state in which the metal post 8 is on the entire wafer, and schematically shows the configuration of FIG. As an upper layer, for example, an insulating resin layer 31 made of amic acid is applied to a Teflon sheet 30 to form a film F. In FIG. 12, the thick line is the sheet 30.
When the film F is arranged on the entire surface of the wafer and pressed against a flat press plate from above, since the insulating resin layer 31 is soft since it is not cured, all the metal posts can be covered with the insulating resin layer 31. . (See Fig. 13 above)
Further, when the film F is pressed by the press plate and the sheet 30 comes into contact with the metal post 8, the pressing is stopped. In this state, the insulating resin layer 31 is pushed between the head of the metal post and the sheet 30.
[0081]
Then, as in the previous example, heat is applied to cure. By this curing, the insulating resin layer 31 contracts, and the surface thereof is positioned at the lower end than the head of the metal post 8. In this state, the sheet 30 is attached to the state shown in FIG. (See Figure 14 above)
And if the sheet | seat 30 is peeled off like FIG. 15, the structure of FIG. 7 is realizable.
[0082]
There are two points here. One is to evacuate in the state of FIG. That is, since the film is bonded, air bubbles are mixed. Second, since the pressing is performed by the press plate, the insulating resin layer 31 between the sheet 30 and the metal post 8 can be eliminated. Therefore, if the sheet 30 is peeled off after curing, the head of the metal post 8 can be exposed.
[0083]
Even in this case, the insulating resin layer 31 may remain thinly on the head of the metal post 8, but since the amount thereof is very small, it can be completely removed by simple polishing or plasmo ashing. In addition, since the insulating resin layers r and R are employed, the entire wafer is flat, and the height of the head of the metal post 8 is uniform, the head of the metal post 8 existing over the entire wafer can be cleaned by the polishing.
[0084]
After the sheet is peeled off in FIG. 15, the process enters the barrier metal forming process of FIG.
[0085]
Although the CSP using the wiring layer shown in FIG. 10 has been described above, it can also be realized in the CSP without the wiring layer, that is, the structure of FIG. In this case, only the wiring layer is omitted, a first groove is formed around the chip, and the same material as the insulating layer is embedded in the first groove.
[0086]
【The invention's effect】
According to the present invention, first, the first insulating resin layer is embedded in the first groove, and dicing is performed with a width smaller than that of the first groove, whereby the insulating resin layer r, the passivation film, and the passivation are formed. The insulating resin layer R can protect the interface between the film and the interlayer insulating film or the lower layer. Therefore, improvement in moisture resistance and environmental resistance as a product can be realized.
[0087]
Second, it can also be applied to a CSP in which a wiring layer is provided below a metal post.
[0088]
Third, by forming the first insulating resin layer and the second insulating resin layer from the same material, the process can be simplified, and the deterioration of the wafer strength due to the formation of the first groove is also first. This can be maintained by embedding the insulating resin layer.
[0089]
Fourth, the first groove can be solved by forming the semiconductor substrate by being half-cut by dicing, and can be greatly simplified as compared with the formation of the first groove by etching.
[0090]
Fifth, the strength of the entire wafer can be maintained by forming the first groove and embedding the first insulating resin layer therein, and further, after dicing with the side surface of the first groove as shown in FIG. Since the first insulating resin layer remains between the first and second side surfaces, the interface generated by the conventional dicing is covered with the first insulating resin layer.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 6 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 7 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 8 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 9 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 10 is a diagram illustrating a conventional chip size package.
FIG. 11 is a diagram illustrating a conventional chip size package.
FIG. 12 is a diagram for explaining a production method employing an insulating resin layer film with a sheet.
FIG. 13 is a diagram for explaining a production method employing an insulating resin layer film with a sheet.
FIG. 14 is a diagram for explaining a production method employing an insulating resin layer film with a sheet.
FIG. 15 is a diagram for explaining a production method employing an insulating resin layer film with a sheet.
FIG. 16 is a diagram illustrating a polishing method for exposing a metal post.

Claims (6)

In a semiconductor device separated into a plurality of chips by a dicing line on the wafer,
A metal electrode pad made of a metal material provided on the chip;
An insulating layer provided on the chip surface and having an opening exposing a part of the metal electrode pad ;
A groove that is provided to reach the wafer and that exposes a part of the insulating layer and a part of the wafer on a side wall of the chip;
A metal post mainly made of Cu and electrically connected to the metal electrode pad;
A Si ₃ N ₄ film covering a side surface of the metal post;
A thermosetting insulating resin layer that covers the chip surface including the metal post and the sidewall of the groove and is exposed to the dicing line;
Solder bumps fixed to the metal posts exposed from the surface of the insulating resin layer;
A semiconductor device comprising:   The semiconductor device according to claim 1, further comprising a wiring layer made of Cu as a main material and extending on the insulating layer and connected to the metal post. The semiconductor device according to claim 2, wherein a surface of the wiring layer and a side surface of the metal post are continuously covered with the Si ₃ N ₄ film. The semiconductor device according to claim 1, wherein the groove is formed by half-cutting the wafer by dicing. Forming a plurality of chips and metal electrode pads on the wafer, and forming an insulating layer having an opening exposing a part of the metal electrode pads on the wafer;
Forming Cu as a main material and forming a wiring layer connected to the metal electrode pad and extending on the insulating layer;
Forming a metal post connected to the wiring layer using Cu as a main material;
Half-cutting the wafer, forming the insulating layer serving as the end of the chip on the side wall and a groove exposing a part of the wafer;
Forming a Si ₃ N ₄ film covering a side surface of the metal post;
Forming an insulating resin layer covering the insulating layer, the wiring layer, and the side wall of the groove;
Forming solder balls on top of the metal posts exposed from the insulating layer;
Exposing the insulating resin layer covering the side wall of the groove and full-cutting the wafer;
A method for manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to claim 5, wherein the Si ₃ N ₄ film continuously covers a surface of the wiring layer and a side surface of the metal post.

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