CN114582721B - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN114582721B CN114582721B CN202210479744.0A CN202210479744A CN114582721B CN 114582721 B CN114582721 B CN 114582721B CN 202210479744 A CN202210479744 A CN 202210479744A CN 114582721 B CN114582721 B CN 114582721B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Abstract
The embodiment of the disclosure discloses a manufacturing method of a semiconductor device, which comprises the following steps: forming a first blind hole in a first wafer; forming a first filling structure in the first blind hole; forming a first mask structure covering the first wafer and the first filling structure; wherein the first mask structure comprises a mask opening; etching the first wafer according to the mask opening to form a second blind hole in the first wafer; wherein the depth of the second blind hole is different from the depth of the first blind hole; the position of the second blind hole is different from that of the first blind hole; after the second blind hole is formed, removing the first mask structure and the first filling structure.
Description
Technical Field
The embodiment of the disclosure relates to but is not limited to the field of semiconductor manufacturing, and particularly relates to a manufacturing method of a semiconductor device.
Background
During the fabrication of semiconductor devices, via structures (including vias and/or blind vias) may be formed in a wafer by a via-etching process.
The hole etching process only etches a hole structure with one depth on the surface of the wafer at present, and if the etching of a hole structure with two or more depths is involved, for example, when a second hole structure is formed by etching, the depth and the sidewall morphology of the formed first hole structure (the depth is different from that of the second hole structure) are difficult to control, so that the stability of the hole etching process is poor.
Disclosure of Invention
The embodiment of the disclosure provides a manufacturing method of a semiconductor device, which includes:
forming a first blind hole in a first wafer;
forming a first filling structure in the first blind hole;
forming a first mask structure covering the first wafer and the first filling structure; wherein the first mask structure comprises a mask opening;
etching the first wafer according to the mask opening to form a second blind hole in the first wafer; wherein the depth of the second blind hole is different from the depth of the first blind hole; the position of the second blind hole is different from that of the first blind hole;
after the second blind hole is formed, removing the first mask structure and the first filling structure.
In some embodiments, the first filling structure comprises: a first bonding glue layer; the first mask structure includes: a second wafer; wherein the second wafer comprises the mask opening;
the forming a first fill structure in the first blind via includes:
coating the first bonding glue layer in the first blind hole;
the forming a first mask structure covering the first wafer and the first filling structure includes:
aligning and bonding the first wafer and the second wafer; the first bonding glue layer is located between the first wafer and the second wafer.
In some embodiments, the first wafer comprises: a first region and a second region; wherein the first blind hole is located in the first region; the manufacturing method further comprises the following steps:
and forming the first bonding glue layer covering the second area while filling the first bonding glue layer into the first blind hole.
In some embodiments, the second wafer comprises: a third region and a fourth region; wherein the mask opening is located in the fourth region;
before aligning and bonding the first wafer and the second wafer, the fabrication method further comprises:
forming a second bonding glue layer covering the third area;
the bonding the first wafer and the second wafer comprises:
and bonding the first bonding glue layer and the second bonding glue layer so as to bond the first wafer and the second wafer.
In some embodiments, the removing the first mask structure and the first fill structure after forming the second blind via includes:
performing debonding treatment on the first wafer and the second wafer to expose the first bonding glue layer;
and removing the first bonding glue layer.
In some embodiments, the first wafer comprises: a first region and a second region; wherein the first blind hole is located in the first region;
the forming a first fill structure in the first blind via includes:
depositing a filling material into the first blind hole; wherein the filler material covers the second region;
removing the filling material on the first wafer to form the first filling structure; wherein a top surface of the first fill structure is substantially flush with a top surface of the first wafer.
In some embodiments, the forming a first fill structure in the first blind via comprises:
forming the first filling structure covering the side wall of the first blind hole and the bottom of the first blind hole, and forming a first sub blind hole based on the appearance of the first blind hole;
the forming a first mask structure covering the first wafer and the first filling structure includes:
forming the first mask structure covering the first wafer and the first sub-blind holes; wherein the first mask structure is substantially flush with a surface relatively distant from the first wafer.
In some embodiments, the forming a first mask structure covering the first wafer and the first fill structure comprises:
bonding the first wafer and the second wafer; wherein the first fill structure is located between the first wafer and the second wafer;
forming the mask opening penetrating through the second wafer; wherein the mask opening exposes the first wafer.
In some embodiments, after bonding the first wafer and the second wafer and before etching the second wafer, the method further comprises:
and thinning one side of the second wafer relatively far away from the first wafer.
In some embodiments, after forming the second blind via and before removing the first mask structure and the first fill structure, the fabrication method further comprises:
forming a second filling structure in the second blind hole;
forming a second mask structure covering the first mask structure and the second filling structure;
forming a third blind hole which penetrates through the second mask structure and the first mask structure and is positioned in the first wafer at the bottom; wherein the depth of the third blind hole is different from the depth of the second blind hole, and the depth of the third blind hole is different from the depth of the first blind hole; the position of the third blind hole is different from that of the second blind hole, and the position of the third blind hole is different from that of the first blind hole.
In the embodiment of the disclosure, a first filling structure is formed in the first blind hole, a first mask structure covering the first wafer and the first filling structure is formed, and then the first wafer is etched according to the mask opening in the first mask structure, so that a second blind hole with a depth different from that of the first blind hole can be formed in the first wafer. In the process of forming the second blind hole, because the first filling structure is formed in the first blind hole, and the first filling structure is covered by the first mask structure, the side wall and the bottom of the first blind hole can be better protected by the first mask structure and the first filling structure, the probability that the formed first blind hole is exposed in the etching environment is reduced, the appearance of the side wall of the first blind hole is better, the probability that the first blind hole is further etched is reduced, the actual depth of the first blind hole is closer to the design depth, and the process stability of silicon through hole etching is improved.
Further, if the first blind via and the second blind via are required to be formed in different first wafers, the first mask structure including the mask opening may be reused, that is, the first mask structure may be reused. Therefore, the demand of the subsequent processing on the using amount of the first mask structure can be reduced, and the manufacturing cost of the semiconductor device is reduced.
Drawings
Fig. 1 is a flow chart illustrating a method of fabricating a semiconductor device according to an embodiment of the present disclosure;
FIG. 2 is a first schematic diagram illustrating a semiconductor device fabrication process according to an embodiment of the present disclosure;
FIG. 3 is a second schematic diagram illustrating a semiconductor device fabrication process according to an embodiment of the present disclosure;
FIG. 4 is a third schematic diagram illustrating a semiconductor device fabrication process in accordance with an embodiment of the present disclosure;
FIG. 5 is a fourth schematic diagram illustrating a semiconductor device fabrication process in accordance with an embodiment of the present disclosure;
FIG. 6 is a fifth schematic diagram illustrating a semiconductor device fabrication process in accordance with an embodiment of the present disclosure;
FIG. 7 is a sixth schematic diagram illustrating a semiconductor device fabrication process in accordance with an embodiment of the present disclosure;
FIG. 8 is a seventh schematic diagram illustrating a semiconductor device fabrication process according to an embodiment of the present disclosure;
FIG. 9a is an eighth schematic illustration of a semiconductor device fabrication process in accordance with an embodiment of the present disclosure;
FIG. 9b is a ninth schematic illustration of a semiconductor device fabrication process, in accordance with an embodiment of the present disclosure;
fig. 9c is a ten schematic diagram illustrating a semiconductor device fabrication process in accordance with an embodiment of the present disclosure;
FIG. 10 is an eleventh schematic diagram illustrating a semiconductor device fabrication process in accordance with an embodiment of the present disclosure;
FIG. 11 is a twelve schematic illustration of a semiconductor device fabrication process in accordance with an embodiment of the present disclosure;
FIG. 12 is a thirteen schematic diagram illustrating a semiconductor device fabrication process in accordance with an embodiment of the present disclosure;
FIG. 13 is a fourteenth schematic diagram illustrating a semiconductor device fabrication process in accordance with an embodiment of the present disclosure;
FIG. 14 is a schematic fifteen view illustrating a semiconductor device fabrication process in accordance with an embodiment of the present disclosure;
FIG. 15 is a sixteen schematic illustration of a semiconductor device fabrication process in accordance with an embodiment of the present disclosure;
FIG. 16 is a seventeenth schematic diagram illustrating a semiconductor device fabrication process according to an embodiment of the present disclosure;
FIG. 17 is a first schematic diagram illustrating another semiconductor device fabrication process in accordance with an embodiment of the present disclosure;
FIG. 18a is a second schematic diagram illustrating another fabrication process for a semiconductor device according to an embodiment of the present disclosure;
FIG. 18b is a third schematic diagram illustrating another fabrication process for a semiconductor device according to an embodiment of the present disclosure;
FIG. 19 is a fourth schematic diagram illustrating another fabrication process for a semiconductor device in accordance with an embodiment of the present disclosure;
FIG. 20 is a fifth schematic diagram illustrating another fabrication process for a semiconductor device in accordance with an embodiment of the present disclosure;
FIG. 21 is a sixth schematic diagram illustrating another fabrication process for a semiconductor device according to an embodiment of the present disclosure;
fig. 22 is a seventh schematic diagram illustrating another fabrication process for a semiconductor device according to an embodiment of the present disclosure.
Detailed Description
The technical solutions of the present disclosure will be further explained in detail with reference to the drawings and examples. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The present disclosure is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present disclosure will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present disclosure.
In the embodiments of the present disclosure, the terms "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a particular order or sequence.
The technical means described in the embodiments of the present disclosure may be arbitrarily combined without conflict.
With the development of semiconductor technology, the feature size of integrated circuits is continuously reduced, and the interconnection density of devices is continuously increased. The conventional two-dimensional package has not been able to meet the needs of the industry, and therefore, the interposer package method based on Through Silicon Via (TSV) vertical interconnection gradually leads the development of the package technology with the key technical advantages of short-distance interconnection, high-density integration and low cost.
Through carrying out the two times of hole carving processes, silicon through holes with two different depths can be formed in the wafer. And forming a photoresist layer covering the wafer, the side wall and the bottom of the first through silicon via after the first hole etching process is carried out and before the second hole etching process is carried out. And forming a patterned photoresist layer by performing exposure and development processes, and performing a second hole etching process according to the pattern in the photoresist layer to form a second through silicon via in the wafer.
Here, the first through-silicon-via and the second through-silicon-via may function as a light-transmitting structure, i.e., allow light to pass through. Alternatively, the first through-silicon-via and the second through-silicon-via may be filled with a conductive material to form a conductive interconnect structure, which is used to realize an electrical connection between the two functional structures.
However, the sidewall of the first through silicon via formed after the first via etching process is performed is almost perpendicular to the bottom of the first through silicon via, the photoresist covering the sidewall of the first through silicon via may fall off, and when the second via etching process is performed, the sidewall of the first through silicon via is exposed to the etching environment due to the falling off of the photoresist covering the sidewall of the first through silicon via, resulting in damage to the sidewall of the first through silicon via.
In the related art, a bump is formed at a predetermined position of the second through-silicon via, after the first hole-etching process is performed, the bump is removed to expose the wafer, and a second hole-etching process is performed on the wafer exposed by the bump. Therefore, the photoresist layer is not required to be coated, and the photoresist covering the side wall of the first through silicon via is prevented from falling off.
However, in the above-mentioned scheme of removing the bump and then performing the second via etching process, when the first through-silicon via reaches the design depth after performing the first via etching process, in the process of performing the second via etching process, since the first through-silicon via is not protected, the first through-silicon via is exposed in the etching environment, which results in an increase in the actual depth of the first through-silicon via (i.e., greater than the design depth of the first through-silicon via), and reduces the process stability of the via etching.
Also, when the first through-silicon-via is used as a light-transmitting structure, other structures located below the first through-silicon-via may be damaged due to the first through-silicon-via being further etched. When the conductive material is filled into the first through silicon via, the actual depth of the interconnection structure filling the first through silicon via is increased due to the increase of the actual depth of the first through silicon via, which affects the transmission of signals. For example, signal delay occurs, etc.
Further, if more than two through-silicon vias with different depths need to be formed in the wafer, the actual depth of the first through-silicon via is further increased, and the actual depth of the second through-silicon via is increased, so that the process stability of the through-silicon via hole etching is further reduced.
When the first through silicon via does not reach the design depth after the first hole etching process is performed, the first through silicon via may be further etched to the design depth in the process of performing the second hole etching process. However, in this solution, a first deep through silicon via needs to be formed first, and then a second shallow through silicon via needs to be formed, that is, the through silicon via needs to be fabricated according to a process from deep to shallow, which results in low flexibility of the through silicon via fabrication process, and the deep first through silicon via needs to be subjected to a double etching process, which results in poor continuity of the sidewall of the first through silicon via.
Moreover, when the first through silicon via is used as a light-transmitting structure, the continuity of the sidewall of the first through silicon via is poor, which may cause an increase in the probability of light refraction and affect the transmission of light. When filling the conductive material into the first through silicon via, due to poor continuity of the sidewall of the first through silicon via, filling of the subsequent conductive material may be affected.
In view of the above, the present disclosure provides a method for manufacturing a semiconductor device.
Fig. 1 is a flow chart illustrating a method of fabricating a semiconductor device according to an embodiment of the present disclosure, the method of fabricating including at least the steps of:
s100: forming a first blind hole in a first wafer;
s200: forming a first filling structure in the first blind hole;
s300: forming a first mask structure covering the first wafer and the first filling structure; wherein the first mask structure comprises a mask opening;
s400: etching the first wafer according to the mask opening to form a second blind hole in the first wafer; the depth of the second blind hole is different from that of the first blind hole; the position of the second blind hole is different from that of the first blind hole;
s500: after the second blind holes are formed, the first mask structure and the first filling structure are removed.
In the embodiment of the disclosure, a first filling structure is formed in the first blind hole, a first mask structure covering the first wafer and the first filling structure is formed, and then the first wafer is etched according to the mask opening in the first mask structure, so that a second blind hole with a depth different from that of the first blind hole can be formed in the first wafer. In the process of forming the second blind hole, because the first filling structure is formed in the first blind hole, and the first filling structure is covered by the first mask structure, the side wall and the bottom of the first blind hole can be better protected by the first mask structure and the first filling structure, the probability that the formed first blind hole is exposed in the etching environment is reduced, the appearance of the side wall of the first blind hole is better, the probability that the first blind hole is further etched is reduced, the actual depth of the first blind hole is closer to the design depth, and the process stability of silicon through hole etching is improved.
And because the probability that the first blind hole is further etched is reduced, the probability that other structures below the first silicon through hole are damaged is favorably reduced, and other structures below the first silicon through hole can be better protected.
In addition, because the etching of the second blind hole and the etching of the first blind hole are respectively and independently carried out, the continuity of the side walls of the second blind hole and the first blind hole is favorably ensured to be better.
Fig. 2 to 22 are schematic views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present disclosure. The present disclosure will be described in further detail with reference to fig. 1, 2 to 22.
First, referring to fig. 2 to 8, step S100 is performed: a first blind via 104 is formed in the first wafer 101.
In some embodiments, before performing step S100, the manufacturing method further includes:
providing a first wafer 101;
sequentially forming a first mask material layer 102 'and a first photoresist material layer 103' covering the first wafer 101;
forming a first photoresist pattern 1031 in the first photoresist material layer 103';
etching the first mask material layer 102 'according to the first lithographic pattern 1031 to form a mask pattern 1021 in the first mask material layer 102';
the step S100 includes:
the first wafer 101 is etched according to the mask pattern 1021 to form first blind vias 104 in the first wafer 101.
Illustratively, the first mask material layer 102' is deposited on the first wafer 101 by a thin film deposition process including, but not limited to, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, an Atomic Layer Deposition (ALD) process, or a combination thereof.
Illustratively, a first photoresist material layer 103 'is coated on the first mask material layer 102' by a paste coating process. The gumming process includes, but is not limited to, a spin coating process, a spray coating process, a roll coating process, a dip coating process, a printing process, or a combination thereof.
Illustratively, through an exposure and development process, a first photoresist layer 103 including a first photoresist pattern 1031 is formed, and the bottom of the first photoresist pattern 1031 reveals a first masking material layer 102'. The first lithographic pattern 1031 is used to define the position of the first blind via 104.
Illustratively, the first mask material layer 102' is etched downward along the z-axis direction by an etching process to form a mask layer 102 including a mask pattern 1021, a bottom of the mask pattern 1021 exposes the first wafer 101, and the first wafer 101 is continuously etched downward along the z-axis direction to form a first blind via 104 in the first wafer 101, wherein a bottom of the first blind via 104 is located in the first wafer 101. The etching process includes, but is not limited to, dry etching, wet etching, or a combination thereof. The mask layer 102 is used for protecting the mask pattern 1021 in the process of forming the first blind hole 104 through etching, and the probability of deformation of the mask pattern 1021 is reduced.
The first wafer 101 comprises the following constituent materials: elemental semiconductor materials (e.g., silicon, germanium), group iii-v compound semiconductor materials, group ii-vi compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. In this embodiment, the first wafer 101 is a silicon wafer.
The first masking material layer 102' comprises the following materials: any one or any combination of silicon oxide, silicon nitride, polysilicon, amorphous carbon, spin-on carbon.
The first photoresist material layer 103' comprises the following materials: photosensitive resin or radiation sensitive material, etc.
The first blind via 104 may be a via structure located in the first wafer 101, or may be a trench structure located in the first wafer 101. The projection of the first blind hole 104 in the horizontal plane includes a circle, an ellipse, a square, a rectangle, or the like. Here, the horizontal plane may be a plane perpendicular to the z-axis.
Then, step S200 is performed: a first fill structure is formed in the first blind via 104.
In some embodiments, the first filling structure comprises: a first bonding glue layer;
the step S200 includes: a first layer of bonding paste is applied to the first blind via 104.
Illustratively, the first bonding paste layer 105' may be applied to the first blind via 104 by a paste application process. The gumming process includes, but is not limited to, a spin coating process, a spray coating process, a roll coating process, a dip coating process, a printing process, or a combination thereof.
In one example, referring to fig. 9a, the first bonding glue layer 105 'includes voids 1051, i.e., the first bonding glue layer 105' in fig. 9a is a hollow structure. In another example, referring to fig. 9b, the first bonding glue layer 105 'completely fills the first blind holes 104, i.e., the first bonding glue layer 105' in fig. 9b is a solid structure.
In an example, the top surface of the first layer of bonding glue 105' is substantially flush with the top surface of the first wafer 101. Here, substantially flush includes the top surface of the first layer of bonding glue 105 'being completely flush with the top surface of the first wafer 101, or the distance between the top surface of the first layer of bonding glue 105' and the top surface of the first wafer 101 being very small and negligible.
It is noted that during the process of applying the first bonding paste layer 105' into the first blind via 104, a void 1051 as shown in fig. 9a may occur due to the influence or limitation of the actual process conditions. By providing the top surface of the first bonding glue layer 105' substantially flush with the top surface of the first wafer 101, the flatness of the first wafer 101 during processing can be ensured, providing a relatively flat surface for subsequent semiconductor processing.
Moreover, the top surface of the first bonding glue layer 105' is ensured to be basically flush with the top surface of the first wafer 101, so that the alignment precision and the bonding precision between the subsequent first wafer and the second wafer are improved, and the process stability of the subsequent second blind hole manufacturing is further improved.
The first Bonding paste layer 105' includes a Temporary Bonding (TB) paste for temporarily Bonding the first wafer and the second wafer or debonding the first wafer and the second wafer in a subsequent process. The material of the temporary bonding glue comprises a polymer material dissolved after laser irradiation or a polymer material dissolved after heating. For example, thermoplastic resins, etc.
In the embodiment of the disclosure, the first bonding adhesive layer is coated in the first blind hole, the first bonding adhesive layer can be used for bonding a first wafer and a second wafer in a subsequent process while protecting the side wall and the bottom of the first blind hole, and the bonded second wafer can further protect the first bonding adhesive layer in the first blind hole, so that the subsequent etching of the second blind hole is performed independently of the first blind hole, the probability of further etching the first blind hole is favorably reduced, and the process stability of the through silicon via hole etching is improved.
In some embodiments, referring to fig. 8, the first wafer 101 includes: a first region 101a and a second region 101 b; wherein, the first blind hole 104 is located in the first region 101 a; the manufacturing method further comprises the following steps:
while filling the first blind via 104 with the first bonding glue layer 105, the first bonding glue layer 105 covering the second region 101b is formed.
For example, the first region 101a may be a region of the first wafer 101 for forming the first blind via 104, and the second region 101b may be a region of the first wafer 101 other than the first region 101 a. While applying the first bonding glue layer into the first blind hole 104, a portion of the first bonding glue layer is applied on the second region 101b, thereby forming a first bonding glue layer 105 as shown in fig. 9 c.
In some embodiments, the surface of the first bonding glue layer 105 relatively far from the first wafer 101 satisfies the predetermined flat condition. Here, satisfying the preset flat condition includes: the surface of the first bonding glue layer 105 relatively far away from the first wafer 101 is parallel to the horizontal plane, or the flatness tolerance range of the surface of the first bonding glue layer 105 relatively far away from the first wafer 101 relative to the horizontal plane includes-20 nm to 20 nm.
In the embodiment of the disclosure, the first bonding adhesive layer covering the second area is formed while the first bonding adhesive layer is filled in the first blind hole, which is beneficial to increasing the area of the first bonding adhesive layer coated on the surface of the first wafer, thereby increasing the adhesive strength between the first wafer and the second wafer in subsequent bonding, ensuring the bonding firmness between the first wafer and the second wafer in a bonding adhesive mode, reducing the probability of deviation or bonding failure in advance due to the undersize adhesive strength between the first wafer and the second wafer, and being beneficial to ensuring the normal operation of the subsequent second blind hole manufacturing.
Next, step S300 is executed: forming a first mask structure covering the first wafer 101 and the first filling structure; wherein the first mask structure includes a mask opening 1061. The following will be explained taking the example shown in fig. 9c as an example, however, the present disclosure is not limited thereto.
In some embodiments, referring to fig. 13, the first mask structure includes: a second wafer 106; wherein the second wafer 106 includes mask openings 1061;
the step S300 includes: aligning and bonding the first wafer 101 and the second wafer 106; the first bonding glue layer 105 is located between the first wafer 101 and the second wafer 106.
The constituent materials of the second wafer 106 include: elemental semiconductor materials (e.g., silicon, germanium), group iii-v compound semiconductor materials, group ii-vi compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art.
It is understood that, in the present embodiment, the second wafer 106 is a wafer including a mask opening 1061, and the mask opening 1061 is used to define the position of a second blind via to be formed subsequently. The second wafer 106 is used for protecting the mask opening 1061 in the process of forming the second blind hole by etching, so that the probability of deformation of the mask opening 1061 is reduced. In other examples, the second wafer 106 may be a complete wafer, which will be described in detail below and will not be described herein.
In some embodiments, referring to fig. 13, the second wafer 106 includes: a third region and a fourth region; wherein the mask opening 1061 is located in the fourth region;
before aligning and bonding the first wafer 101 and the second wafer 106, the manufacturing method further includes:
forming a second bonding glue layer covering the third area;
the bonding of the first wafer 101 and the second wafer 106 includes:
the first bonding glue layer 105 and the second bonding glue layer are bonded so that the first wafer 101 and the second wafer 106 are bonded.
For example, the fourth area may be an area of the second wafer 106 for forming the mask opening 1061, and the third area may be an area of the second wafer 106 other than the fourth area. By adopting the above gluing process, the second bonding glue layer is coated on the third area of the second wafer 106, the second wafer 106 is inverted so that the surface of the third area coated with the second bonding glue layer faces the first wafer 101, and then the first bonding glue layer 105 and the second bonding glue layer are bonded.
It is understood that after bonding the first wafer 101 and the second wafer 106, the first bonding glue layer 105 is located between the first wafer 101 and the second wafer 106, and the second bonding glue layer (not shown) is located between the first bonding glue layer 105 and the second wafer 106.
The second bonding glue layer comprises a temporary bonding glue used for temporarily bonding the first wafer and the second wafer or debonding the first wafer and the second wafer in a subsequent process. The material of the temporary bonding paste includes a polymer material, such as a thermoplastic resin, which is dissolved after laser irradiation. In this embodiment, the second bonding glue layer is the same as the first bonding glue layer. In other embodiments, the second layer of bonding glue is different from the first layer of bonding glue.
Compared with the method that the first bonding adhesive layer is coated only in the first wafer, in the embodiment of the disclosure, the second bonding adhesive layer is coated in the third area of the second wafer, so that the adhesive strength between the first wafer and the second wafer in subsequent bonding is favorably increased, the bonding firmness between the first wafer and the second wafer in a bonding adhesive mode is further ensured, the probability of deviation or bonding failure in advance due to the fact that the adhesive strength between the first wafer and the second wafer is too small is reduced, and the normal operation of the subsequent second blind hole manufacturing is favorably ensured.
In some embodiments, as shown in fig. 10 and 13, the step S300 includes:
bonding the first wafer 101 and the second wafer 106'; wherein the first filling structure is located between the first wafer 101 and the second wafer 106';
forming a mask opening 1061 through the second wafer 106'; the mask opening 1061 exposes the first wafer 101.
Illustratively, a second photoresist material layer is formed overlying the second wafer 106 ", and a second photoresist layer 107 including a second photoresist pattern 1071 is formed by performing an exposure and development process on the second photoresist material layer. Here, the composition material of the second photoresist layer 107 may be the same as that of the first photoresist layer 103, and thus, the description thereof is omitted.
Illustratively, the second wafer 106 ″ is etched down in the z-axis direction by an etching process to form the second wafer 106 including the mask opening 1061. In one example, the first bonding glue layer 105 is only located in the first blind via, and the bottom of the mask opening 1061 exposes the first wafer 101. In another example, the first bonding glue layer 105 is further located on the second area, the bottom of the mask opening 1061 exposes the first bonding glue layer 105, and the first bonding glue layer 105 exposed at the bottom of the mask opening 1061 is removed to expose the first wafer 101.
Unlike the second wafer 106 of fig. 13, the second wafer 106' is a complete wafer in this example. Here, the complete wafer means a wafer which is not processed by photolithography, etching, deposition, or the like, or a wafer on which a mask opening or a circuit pattern is not formed.
In practical applications, it is usually necessary to process a lot of first wafers to form at least a first blind via and a second blind via in each first wafer of the lot. For example, when the first blind via is formed in the 1 st first wafer, the 1 st first wafer is processed by using the second wafer 106 ″ to form the second wafer 106 including the mask opening 1061 (as shown in fig. 13), and when the second blind via is formed in the 2 nd first wafer, the second wafer 106 can be reused without using another complete second wafer 106 ″, so that the requirement for the amount of the second wafer 106 ″ can be reduced, and the manufacturing cost of the semiconductor device can be reduced.
In some embodiments, as shown in fig. 10 and 11, after bonding the first wafer 101 and the second wafer 106 ″ and before etching the second wafer 106 ″, the method further includes:
the second wafer 106' is thinned on the side relatively away from the first wafer 101.
For example, a thinning process may be performed on a side of the second wafer 106 ″ opposite to the side away from the first wafer 101 to form a thinned second wafer 106 'as shown in fig. 11, and then a second photoresist material layer may be coated on the thinned second wafer 106'. Here, the thinning process includes a planarization process or an etching process.
It is understood that the second wafer 106 is used as a hard mask layer for forming the second blind via 108, and the thickness of the second wafer 106 "can be reduced by performing a thinning process on the second wafer 106", so that the final thickness of the second wafer 106 meets the process requirements for use as a hard mask layer.
It is emphasized that in practical applications, the thinning process may not be performed when the thickness of the second wafer 106 "is provided to meet the process requirements for the hard mask layer, and the disclosure is not limited thereto.
Next, as shown in fig. 13 and 14, step S400 is performed: etching the first wafer 101 according to the mask opening 1061 to form a second blind hole 108 in the first wafer 101; wherein the depth of the second blind hole 108 is different from the depth of the first blind hole 104; the second blind hole 108 is located differently from the first blind hole 104.
Illustratively, the first wafer 101 is etched down in the z-axis direction by an etching process to form a second blind via 108 in the first wafer 101, the bottom of the second blind via 108 being located within the first wafer 101. The etching process includes, but is not limited to, dry etching, wet etching, or a combination thereof.
The second blind via 108 may be a via structure located in the first wafer 101, or may be a slot structure located in the first wafer 101. The projection of the second blind hole 108 in the horizontal plane includes a circle, an ellipse, a square, a rectangle, or the like. Here, the horizontal plane may be a plane perpendicular to the z-axis.
The depth of the second blind hole 108 different from the depth of the first blind hole 104 includes: the depth of the second blind hole 108 is greater than the depth of the first blind hole 104, or alternatively, the depth of the second blind hole 108 is less than the depth of the first blind hole 104.
It can be understood that, since the first blind via is formed with the first filling structure therein and the second wafer covers the first blind via formed with the first filling structure, the probability of the first blind via being exposed to the etching environment during the process of forming the second blind via by etching can be reduced, that is, the probability of the first blind via being further etched can be reduced. Therefore, the manufacturing method provided by the embodiment of the disclosure is beneficial to ensuring that the sidewall appearance of the formed first blind hole is good, and the depth of the formed first blind hole cannot be increased.
In addition, because the etching of the first blind hole and the etching of the second blind hole are independently performed, the fabrication of the through silicon via does not need to be performed according to a process from deep to shallow, for example, when the depth h of the first blind hole is small 1 And depth h of second blind hole 2 Satisfies the following conditions: h is 1 ＜h 2 First blind holes with shallow depth can be formed first, and then second blind holes with deep depth can be formed. As another example, when the depth h of the first blind hole 1 And depth h of second blind hole 2 Satisfies the following conditions: h is 1 ＞h 2 First blind holes with deep depth can be formed first, and then second blind holes with shallow depth can be formed. Therefore, the flexibility of the through silicon via manufacturing process is improved. And first blind hole and second blind hole are all formed through once etching, are favorable to guaranteeing that the continuity of first blind hole lateral wall and the continuity of second blind hole lateral wall are better, and the lateral wall of first blind hole and the lateral wall of second blind hole are comparatively flat promptly.
Finally, as shown in fig. 14 to 16, step S500 is executed: after the second blind via 108 is formed, the first mask structure and the first fill structure are removed.
In some embodiments, after forming the second blind via 108, the step S500 includes:
performing a debonding process on the first wafer 101 and the second wafer 106 to expose the first bonding glue layer 105;
the first bonding glue layer 105 is removed.
Illustratively, after forming the second blind via 108, the first bonding glue layer 105 is irradiated by laser or the first bonding glue layer 105 is heated to dissolve the first bonding glue layer 105, so that the first wafer 101 and the second wafer 106 are separated, i.e. the first wafer 101 and the second wafer 106 are debonded. After the first wafer 101 and the second wafer 106 are debonded, the first bonding glue layer 105 is removed, thereby forming the structure shown in fig. 16.
In one example, referring to FIG. 16, the depth h of the second blind hole 108 2 Is greater than the depth h of the first blind hole 104 1 . In other examples, the depth h of the second blind hole 108 2 May be smaller than the depth h of the first blind hole 104 1 The disclosure is not limited thereto.
In the embodiment of the disclosure, since the first wafer and the second wafer are bonded by using a physical method (i.e., a temporary bonding adhesive), after the first blind hole and the second blind hole are independently formed, the first wafer and the second wafer can be separated by a bonding-off method without damaging the first wafer and the second wafer, on one hand, the integrity of the first wafer is ensured, and on the other hand, the bonded-off second wafer can be reused in the processing process of other first wafers in the same batch, so that the utilization rate of the second wafer is improved, and the manufacturing cost of the semiconductor device is reduced.
In some embodiments, as shown in fig. 8 and 17, the step S200 includes:
depositing a filler material into the first blind via 104; wherein the filling material covers the second region 101 b;
removing the filling material on the first wafer 101 to form a first filling structure 205; wherein a top surface of the first fill structure 205 is substantially flush with a top surface of the first wafer 101.
Illustratively, the fill material may be deposited into the first blind via 104 by a thin film deposition process. During the deposition of the filling material into the first blind via 104, a portion of the filling material covers the second region 101b, and the filling material on the first wafer 101 is removed by performing a planarization process, thereby forming a first filling structure 205 as shown in fig. 17.
In an example, the first filling structure 205 comprises voids, i.e. the first filling structure 205 is a hollow structure. In another example, the first fill structures 205 completely fill the first blind holes 104, i.e., the first fill structures 205 are solid structures.
In an example, a top surface of the first fill structure 205 is substantially flush with a top surface of the first wafer 101. Here, substantially flush includes the top surface of the first fill structure 205 being completely flush with the top surface of the first wafer 101, or the distance between the top surface of the first fill structure 205 and the top surface of the first wafer 101 being very small and negligible.
It is noted that voids may occur in the first fill structure 205 due to the influence or limitation of actual process conditions during the deposition of the fill material into the first blind via 104. By providing the top surface of the first fill structure 205 substantially flush with the top surface of the first wafer 101, planarity of the first wafer 101 during processing is ensured, providing a relatively flat surface for subsequent semiconductor processing.
The first filling-up structure 205 may be an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and the first filling-up structure 205 may also be a metal material, such as tungsten, copper, aluminum, titanium, or the like. In this example, the first fill structure 205 is a metal.
In the embodiment of the disclosure, the first filling structure can be formed in the first blind hole by depositing the filling material in the first blind hole, and since the top surface of the first filling structure is substantially flush with the top surface of the first wafer, the provision of a relatively flat surface for a subsequent semiconductor process is facilitated, and the normal operation of a subsequent manufacturing process is ensured.
In some embodiments, as shown in fig. 17 to 20, the step S300 includes:
sequentially forming a second mask material layer 206 'and a second photoresist material layer 107' covering the first wafer 101 and the first filling structure 205;
forming a second photoresist pattern 1071 in the second photoresist material layer 107';
the second masking material layer 206 'is etched according to the second lithographic pattern 1071 to form a mask opening 2061 in the second masking material layer 206'.
Illustratively, the second mask material layer 206 ' is deposited on the first wafer 101 and the first filling structure 205 by a thin film deposition process, where the composition material of the second mask material layer 206 ' may be the same as that of the first mask material layer 102 ', and will not be described again.
Illustratively, a second layer of photoresist material 107 'is coated over the second layer of masking material 206' by a paste coating process. Here, the composition material of the second photoresist material layer 107 'may be the same as that of the first photoresist material layer 103', and thus, the description thereof is omitted.
Illustratively, the second photoresist layer 107 including the second photoresist pattern 1071 is formed through an exposure and development process, and the bottom of the second photoresist pattern 1071 reveals the second mask material layer 206'. The second lithographic pattern 1071 is used to define the location of the second blind via 108.
Illustratively, the second mask material layer 206' is etched down along the z-axis direction by an etching process to form the first mask structure 206 including the mask opening 2061, the bottom of the mask opening 2061 exposing the first wafer 101, and the first wafer 101 is continuously etched down along the z-axis direction to form the second blind via 108 in the first wafer 101. The first mask structure 206 is used to protect the mask opening 2061 during the etching process to form the second blind via 108, so as to reduce the probability of deformation of the mask opening 2061.
It is understood that, in the example shown in fig. 13, the first mask structure (i.e., the second wafer 106) may cover the first wafer 101 and the first filling structure (i.e., the first bonding glue layer 105) by means of bonding. In the example shown in fig. 20, the first mask structure 206 may cover the first wafer 101 and the first fill structure 205 by deposition.
In some embodiments, as shown in fig. 8 and fig. 18b, the step S200 includes:
forming a first filling structure 205' covering the side wall of the first blind hole 104 and the bottom of the first blind hole 104, and forming a first sub-blind hole based on the morphology of the first blind hole 104;
the step S300 includes:
forming a first mask structure covering the first wafer 101 and the first sub-blind holes; wherein the first mask structure is substantially flush with respect to a surface away from the first wafer 101.
Illustratively, the first filling structure 205' covering the sidewall of the first blind via 104 and the bottom of the first blind via 104 can be formed by controlling the process parameters of the thin film deposition, and a first sub-blind via (not shown) can be formed based on the topography of the first blind via 104. It will be appreciated that the first sub-blind via is located within the first blind via 104 and the first fill structure 205' is located between the first blind via 104 and the first sub-blind via.
The second mask material layer 206 'not only covers the second region 101b, but also is located in the first sub-blind via, and the surface of the second mask material layer 206' relatively far away from the first wafer 101 satisfies a predetermined flat condition. Here, satisfying the preset flat condition includes: the second masking material layer 206 'is parallel to the horizontal plane relative to the surface away from the first wafer 101, or the flatness tolerance range of the surface of the second masking material layer 206' relative to the surface away from the first wafer 101 relative to the horizontal plane includes-20 nm to 20 nm.
By performing a process similar to that of fig. 19 and 20, a first mask structure covering the first wafer 101 and the first sub-blind via may be formed, and the first mask structure is substantially flush with respect to a surface away from the first wafer 101.
In some embodiments, at least one of the first blind via 104 and the second blind via 108 functions as a light transmissive structure. For example, after removing the first mask structure and the first fill structure, at least one of the first blind via 104 and the second blind via 108 is used to transmit light. It is to be understood that, in the present example, when at least one of the first and second blind holes 104 and 108 is used as a light-transmitting structure, there is no need to fill a material into the light-transmitting structure.
In some embodiments, as shown in fig. 16, after removing the first mask structure and the first filling structure, the method further includes: forming a light-transmitting structure in the first blind hole 104; and/or forming a light-transmitting structure in the second blind hole 108.
Illustratively, the light-transmitting material may be filled into the first blind via 104 by including a thin film deposition process to form a light-transmitting structure in the first blind via 104; and/or filling the second blind hole 108 with a light-transmitting material to form a light-transmitting structure in the second blind hole 108. Here, the light transmissive material may be a light transmissive material known in the art, and the present disclosure is not limited thereto.
It is understood that, in the present example, when the light-transmitting material is filled into the first blind holes 104, a light-transmitting structure may be formed in the first blind holes 104, the light-transmitting structure allowing light to pass through. When the second blind holes 108 are filled with the light-transmitting material, a light-transmitting structure may be formed in the second blind holes 108, and the light-transmitting structure allows light to pass through.
In some embodiments, as shown in fig. 16, after removing the first mask structure and the first filling structure, the method further includes:
forming a first conductive structure (not shown) in the first blind via 104; and/or forming a second conductive structure (not shown) in the second blind via 108.
Illustratively, the first blind via 104 may be filled with a first conductive material and the second blind via 108 may be filled with a second conductive material by including a thin film deposition process.
In one example, the first conductive material and the second conductive material are the same. The first blind via 104 and the second blind via 108 may be filled simultaneously, or the first blind via 104 and the second blind via 108 may be filled sequentially, which is not limited in this disclosure. When the first blind via 104 and the second blind via 108 are filled simultaneously, the manufacturing process can be saved, and the manufacturing cycle of the semiconductor device can be shortened.
In another example, the first conductive material and the second conductive material are different. The second conductive material may be filled first and the first conductive material may be refilled. For example, after forming the second blind via, and before removing the first fill structure, a second conductive structure is formed in the second blind via. After the second conductive structure is formed, the first filling structure is removed, and a first conductive structure is formed in the first blind hole.
The composition material of the first conductive structure and the second conductive structure includes a conductive material, such as any one of copper, titanium, aluminum, platinum, tungsten, tantalum, titanium nitride, tungsten nitride, tantalum nitride, or a combination thereof.
In the embodiment of the present disclosure, after the first mask structure and the first filling structure are removed, the first conductive structure is formed in the first blind via and the second conductive structure is formed in the second blind via, because the actual depth of the first blind via and the second blind via is closer to the design depth, the actual size (i.e., the size in the vertical direction) of the first conductive structure and the second conductive structure is closer to the design size, which is beneficial to ensuring the stability of the signal transmitted through the first conductive structure and the second conductive structure.
In some embodiments, the first filling structure in the first blind via may be removed by means of a laser irradiation process or a heat treatment. For example, referring to fig. 15, when the first filling structure is the first bonding glue layer 105, it can be dissolved and removed by laser irradiation or heating.
In other embodiments, the first fill structures in the first blind holes may be removed by an etching process. For example, referring to fig. 22, when the first fill structure is a metal 205, it may be removed by a wet etch process.
In some embodiments, as shown in fig. 14, after forming the second blind via 108 and before removing the first mask structure and the first filling structure, the method further includes:
forming a second filling structure in the second blind hole 108;
forming a second mask structure covering the first mask structure and the second filling structure;
forming a third blind hole which penetrates through the second mask structure and the first mask structure and is positioned in the first wafer 101 at the bottom; wherein the depth of the third blind hole is different from the depth of the second blind hole 108, and the depth of the third blind hole is different from the depth of the first blind hole 104; the position of the third blind hole is different from the position of the second blind hole 108, and the position of the third blind hole is different from the position of the first blind hole 104.
By executing the manufacturing process similar to the first blind hole and the second blind hole, a third blind hole with the depth different from that of the first blind hole and the second blind hole can be formed in the first wafer, and the etching of the third blind hole is independent of the first blind hole and the second blind hole, so that the formed first blind hole and the second blind hole are protected. That is, even if more than two through-silicon vias with different depths need to be formed in a wafer, the manufacturing method disclosed by the disclosure can ensure the stability of the through-silicon via etching process.
The depth of the third blind hole is different from the depth of the second blind hole 108, and the depth of the third blind hole is different from the depth of the first blind hole 104, including: the depth of the third blind hole is greater than the depth of the second blind hole 108, and the depth of the third blind hole is greater than the depth of the first blind hole 104; or the depth of the third blind hole is smaller than that of the second blind hole 108, and the depth of the third blind hole is smaller than that of the first blind hole 104; or the depth of the third blind hole is greater than that of the second blind hole 108, and the depth of the third blind hole is less than that of the first blind hole 104; alternatively, the depth of the third blind hole is less than the depth of the second blind hole 108, and the depth of the third blind hole is greater than the depth of the first blind hole 104.
It can be understood that by adopting the manufacturing method disclosed by the invention, at least more than two through silicon vias with different depths can be formed on the wafer, and meanwhile, the process stability of the through silicon vias with different depths is ensured to be better.
In some embodiments, the third blind hole serves as a light-transmitting structure. When the third blind hole is used as a light-transmitting structure, there is no need to fill a material into the light-transmitting structure.
In some embodiments, after forming the third blind via, the method further includes: and forming a light-transmitting structure in the third blind hole. For example, the third blind holes may be filled with a light-transmitting material by including a thin film deposition process to form light-transmitting structures in the third blind holes, the light-transmitting structures allowing light to pass through.
In some embodiments, after forming the third blind via, the method further includes: and forming a third conductive structure in the third blind hole.
Illustratively, the third conductive material may be filled into the third blind via by including a thin film deposition process to form a third conductive structure in the third blind via.
The composition material of the third conductive structure includes a conductive material, such as any one of copper, titanium, aluminum, platinum, tungsten, tantalum, titanium nitride, tungsten nitride, tantalum nitride, or a combination thereof.
In addition, because the etching of the first blind hole, the etching of the second blind hole and the etching of the third blind hole are independently performed, the fabrication of the through silicon via does not need to be performed according to a process from deep to shallow, for example, when the depth h of the first blind hole is small 1 Depth h of the second blind hole 2 And depth h of third blind hole 3 Satisfies the following conditions: h is 1 ＜h 2 ＜h 3 The first blind hole with the shallowest depth can be formed first, then the second blind hole with the second shallowest depth can be formed, and finally the third blind hole with the deepest depth can be formed. As another example, when the depth h of the first blind hole 1 Depth h of the second blind hole 2 And depth h of third blind hole 3 Satisfies the following conditions: h is 1 ＞h 2 ＞h 3 The first blind hole with the deepest depth can be formed first, then the second blind hole with the second shallowest depth can be formed, and finally the third blind hole with the shallowest depth can be formed. Therefore, the flexibility of the through silicon via manufacturing process is improved. And first blind hole, second blind hole and third blind hole all form through once-through etching, are favorable to guaranteeing that the continuity of first blind hole lateral wall, the continuity of second blind hole lateral wall and the continuity of third blind hole lateral wall are better, and the lateral wall of first blind hole, the lateral wall of second blind hole and the lateral wall of third blind hole are comparatively flat promptly. When the light-transmitting structure or the third conductive structure needs to be formed in the third blind hole, the filling of the light-transmitting material or the conductive material is facilitated.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (9)
1. A method for manufacturing a semiconductor device, comprising:
forming a first blind hole in a first wafer;
forming a first filling structure in the first blind hole;
forming a first mask structure covering the first wafer and the first filling structure; wherein the first mask structure comprises a mask opening;
etching the first wafer according to the mask opening to form a second blind hole in the first wafer; wherein the depth of the second blind hole is different from the depth of the first blind hole; the position of the second blind hole is different from that of the first blind hole;
after the second blind hole is formed, removing the first mask structure and the first filling structure;
the forming a first mask structure covering the first wafer and the first filling structure includes:
bonding the first wafer and the second wafer; wherein the first fill structure is located between the first wafer and the second wafer;
forming the mask opening penetrating through the second wafer; the mask opening exposes the first wafer.
2. The method of manufacturing according to claim 1, wherein the first filling structure comprises: a first bonding glue layer;
the forming a first fill structure in the first blind via includes:
coating the first bonding glue layer in the first blind hole; the first bonding glue layer is located between the first wafer and the second wafer.
3. The method of manufacturing of claim 2, wherein the first wafer comprises: a first region and a second region; wherein the first blind hole is located in the first region; the manufacturing method further comprises the following steps:
and forming the first bonding glue layer covering the second area while filling the first bonding glue layer into the first blind hole.
4. The method of manufacturing according to claim 2 or 3, wherein the second wafer comprises: a third region and a fourth region; wherein the mask opening is located in the fourth region;
before bonding the first wafer and the second wafer, the manufacturing method further includes:
forming a second bonding glue layer covering the third area;
the bonding the first wafer and the second wafer comprises:
and bonding the first bonding glue layer and the second bonding glue layer so as to bond the first wafer and the second wafer.
5. The method according to claim 2, wherein the removing the first mask structure and the first filling structure after the forming the second blind via comprises:
performing a debonding process on the first wafer and the second wafer to expose the first bonding glue layer;
and removing the first bonding glue layer.
6. The method of manufacturing of claim 1, wherein the first wafer comprises: a first region and a second region; wherein the first blind hole is located in the first region;
the forming a first fill structure in the first blind via includes:
depositing a filling material into the first blind hole; wherein the filler material covers the second region;
removing the filling material on the first wafer to form the first filling structure; wherein a top surface of the first fill structure is substantially flush with a top surface of the first wafer.
7. The method of claim 1, wherein the forming a first fill structure in the first blind via comprises:
forming the first filling structure covering the side wall of the first blind hole and the bottom of the first blind hole, and forming a first sub blind hole based on the appearance of the first blind hole;
the forming a first mask structure covering the first wafer and the first filling structure includes:
forming the first mask structure covering the first wafer and the first sub-blind holes; wherein the first mask structure is substantially flush with a surface relatively distant from the first wafer.
8. The fabrication method of claim 1, wherein after bonding the first wafer and the second wafer and before etching the second wafer, the fabrication method further comprises:
and thinning one side of the second wafer relatively far away from the first wafer.
9. The method of claim 1, wherein after forming the second blind via and before removing the first mask structure and the first fill structure, the method further comprises:
forming a second filling structure in the second blind hole;
forming a second mask structure covering the first mask structure and the second filling structure;
forming a third blind hole which penetrates through the second mask structure and the first mask structure and is positioned in the first wafer at the bottom; wherein the depth of the third blind hole is different from the depth of the second blind hole, and the depth of the third blind hole is different from the depth of the first blind hole; the position of the third blind hole is different from that of the second blind hole, and the position of the third blind hole is different from that of the first blind hole.
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| CN115799049B (en) * | 2022-11-28 | 2023-08-08 | 湖北江城芯片中试服务有限公司 | Method for preparing semiconductor structure |
| CN117253780B (en) * | 2023-11-17 | 2024-01-23 | 西安天光半导体有限公司 | Glue brushing method for semiconductor wafer |
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| CN101913553A (en) * | 2010-08-11 | 2010-12-15 | 电子科技大学 | Bulk silicon etching and gold silicon bonding combined process method |
| CN102208342A (en) * | 2010-03-30 | 2011-10-05 | 台湾积体电路制造股份有限公司 | Method of forming through-silicon via |
| CN104752323A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof |
| CN105374747A (en) * | 2015-12-16 | 2016-03-02 | 华进半导体封装先导技术研发中心有限公司 | Technology method for etching TSV holes with various depth on wafer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102208342A (en) * | 2010-03-30 | 2011-10-05 | 台湾积体电路制造股份有限公司 | Method of forming through-silicon via |
| CN101913553A (en) * | 2010-08-11 | 2010-12-15 | 电子科技大学 | Bulk silicon etching and gold silicon bonding combined process method |
| CN104752323A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof |
| CN105374747A (en) * | 2015-12-16 | 2016-03-02 | 华进半导体封装先导技术研发中心有限公司 | Technology method for etching TSV holes with various depth on wafer |
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