CN108667437B

CN108667437B - Film bulk acoustic resonator, manufacturing method thereof and electronic device

Info

Publication number: CN108667437B
Application number: CN201810354998.3A
Authority: CN
Inventors: 杨天伦
Original assignee: Ningbo Semiconductor International Corp
Current assignee: Ningbo Semiconductor International Corp
Priority date: 2018-04-19
Filing date: 2018-04-19
Publication date: 2022-04-26
Anticipated expiration: 2038-04-19
Also published as: CN108667437A

Abstract

The invention provides a film bulk acoustic resonator, a manufacturing method thereof and an electronic device, wherein the method comprises the following steps: providing a substrate, wherein a bottom cavity is formed in the substrate, and a sacrificial material layer is filled in the bottom cavity; sequentially forming a lower electrode, a piezoelectric layer and an upper electrode on part of the surface of the sacrificial material layer and part of the surface of the substrate, exposing part of the surface of the sacrificial material layer, and overlapping the upper part and the lower part of the upper electrode and the lower electrode; forming a dielectric layer to cover the front surface of the substrate, wherein the top surface of the dielectric layer is higher than the top surface of the upper electrode; forming a top cavity penetrating through the dielectric layer, wherein the top cavity exposes a part of the upper electrode and a part of the surface of the sacrificial material layer; providing a cap substrate, and combining the cap substrate with one side of the base, wherein the dielectric layer is formed on the side; forming at least one release hole, wherein the release hole penetrates through the base to expose part of the sacrificial material layer, or the release hole penetrates through the cap substrate to expose part of the top cavity; and removing the sacrificial material layer.

Description

Film bulk acoustic resonator, manufacturing method thereof and electronic device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a film bulk acoustic resonator, a manufacturing method thereof and an electronic device.

Background

Film Bulk Acoustic Resonators (FBARs) are widely used in the world, especially in the field of wireless communications, due to their advantages of high Q value, small size, good compatibility with silicon wafer processes, and good reliability.

Everything in the world in the future is linked to wireless, and it is statistically estimated that there are about 3600 million consumers worldwide for rf devices in 2015, and 25000 million is expected to be reached by 2020. The demand for radio frequency equipment will increase by several times, with an average of 3 devices per person worldwide. Smartphones typically include 8 or 9 radio frequency filters (RF filters) and 8 duplexers (duplexers). The demand for radio frequency devices is increasing if 5G technology is used. The demand for rf filters is expected to increase from 5000 to 1300 billions by 2020. Therefore, the demand for a thin film bulk acoustic resonator, which is one of the main elements of a radio frequency filter and a duplexer, is also increasing.

However, the conventional process for manufacturing the film bulk acoustic resonator usually forms a bottom cavity in a substrate, forms a sacrificial material layer in the bottom cavity, and then sequentially forms a lower electrode, a piezoelectric layer and an upper electrode on the sacrificial material layer, and in order to release the sacrificial material layer in the bottom cavity, it is usually necessary to form a release hole sequentially penetrating the upper electrode, the piezoelectric layer and the lower electrode, and using the release hole, the sacrificial material layer in the bottom cavity is removed through a wet etching process to finally release the structure. However, due to the existence of the release holes, the upper electrode, the piezoelectric layer and the lower electrode are not continuous, which has a negative effect on the overall resonance performance of the film bulk acoustic resonator, and the release holes need to be opened by a new mask, so that the process is complicated and the process cost is increased.

In view of the above problems, the present invention provides a novel thin film bulk acoustic resonator and a method for manufacturing the same.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In view of the existing problems, the invention provides a method for manufacturing a film bulk acoustic resonator, comprising:

providing a substrate, wherein a bottom cavity is formed in the substrate, and a sacrificial material layer is filled in the bottom cavity;

sequentially forming a lower electrode, a piezoelectric layer and an upper electrode on part of the surface of the sacrificial material layer and part of the surface of the substrate, and exposing part of the surface of the sacrificial material layer, wherein the upper electrode and the lower electrode are overlapped in upper and lower parts;

forming a dielectric layer to cover the front surface of the substrate, and a top surface of the dielectric layer is higher than a top surface of the upper electrode;

forming a top cavity penetrating through the dielectric layer, wherein the top cavity exposes a part of the upper electrode and a part of the surface of the sacrificial material layer;

providing a cap substrate, and combining the cap substrate with one side of the base, wherein the dielectric layer is formed on the side of the base;

forming at least one release hole, wherein the release hole penetrates through the base to expose part of the sacrificial material layer, or penetrates through the cap substrate to expose part of the top cavity;

and removing the sacrificial material layer.

Illustratively, the cross-sectional shape of the bottom cavity is a polygon with any two parallel sides;

the overlooking shape of the lower electrode is a polygon with any two parallel sides;

the overlooking shape of the piezoelectric layer is a polygon with any two parallel sides;

the overlooking shape of the upper electrode is a polygon with any two parallel sides;

the cross section of the top cavity is in a polygonal shape with any two parallel sides.

Illustratively, the overlapped parts of the top cavity and the bottom cavity form a common inner circumference, and the projection of the common inner circumference on the plane of the piezoelectric layer is an irregular polygon which does not contain any pair of opposite and parallel straight line segments.

Illustratively, the sacrificial material layer is removed by wet etching or dry etching.

Illustratively, the method of bonding the cap substrate to the side of the base on which the dielectric layer is formed includes:

before the bottom cavity is formed, or after the sacrificial material layer is formed and before the lower electrode is formed, a bonding pad is formed on the front surface of the substrate, and the bonding pad is annular in the top view shape and surrounds the bottom cavity;

providing a cap substrate, wherein a groove and a bonding ring protruding around the groove are formed on the cap substrate;

forming an opening in the dielectric layer exposing the bond pad, the opening matching the bond ring;

a bonding process is performed to bond the bonding ring and the bonding pad, and the trench encloses the top cavity to effect bonding of the cap substrate and the base.

Exemplarily, the method further comprises the following steps: before the lower electrode is formed, a first bonding pad and a second bonding pad are formed, the first bonding pad and the second bonding pad are located on two sides of the bottom cavity, the lower electrode is electrically connected with the first bonding pad, and the upper electrode is electrically connected with the second bonding pad.

Illustratively, the top of the bonding ring includes a layer of bonding material.

Illustratively, after bonding the cap substrate and the base, before or after removing the sacrificial material layer, further comprises:

and forming an interconnection structure on the back surface of the substrate to electrically connect the lower electrode and the upper electrode, respectively.

Illustratively, before forming the release holes through the substrate to expose portions of the sacrificial material layer, the method further comprises: and thinning the back surface of the substrate.

providing a cap substrate, and directly bonding the cap substrate and the dielectric layer.

Illustratively, after removing the sacrificial layer, the method further comprises:

forming a sealing material to fill the release hole.

In still another aspect, the present invention provides a film bulk acoustic resonator, including:

a substrate;

a bottom cavity formed in the substrate;

the lower electrode is formed on the front surface of the substrate and covers at least part of the bottom cavity;

a piezoelectric layer disposed on the lower electrode;

an upper electrode disposed on the piezoelectric layer;

a dielectric layer covering the front surface of the substrate, and having a top surface higher than a top surface of the upper electrode;

a top cavity penetrating the dielectric layer and exposing at least a portion of the upper electrode;

a cap substrate disposed on the base and bonded to a side of the base on which the dielectric layer is disposed;

a release hole opposite the bottom cavity and through the base, or through the cap substrate opposite the top cavity.

Exemplarily, the method further comprises the following steps:

the bonding ring is convexly arranged on the cap substrate;

and the bonding pad is formed on the front surface of the substrate, the bonding pad is annular in shape in a plan view and surrounds the bottom cavity, and the bonding ring penetrates through the dielectric layer and is bonded with the bonding ring.

Exemplarily, the method further comprises the following steps: the first bonding pad and the second bonding pad are positioned on the surfaces of the substrates on two sides of the bottom cavity and positioned below the lower electrode, the lower electrode is electrically connected with the first bonding pad, and the upper electrode is electrically connected with the second bonding pad.

Illustratively, an interconnection structure is formed on the rear surface of the substrate to electrically connect the lower electrode and the upper electrode, respectively.

Exemplarily, a sealing material is further included, and the sealing material fills the release hole.

The invention also provides an electronic device which comprises the film bulk acoustic resonator.

According to the manufacturing method of the film bulk acoustic resonator, the release hole penetrating through the sacrificial material layer of the exposed part of the substrate is formed, or the release hole penetrating through the top cavity of the exposed part of the cap substrate is formed and used for removing the sacrificial material layer, so that the release hole used for removing the sacrificial material layer is not required to be formed in the lower electrode, the piezoelectric layer and the upper electrode, the continuity of the lower electrode, the piezoelectric layer and the upper electrode is guaranteed, the resonance performance of the film bulk acoustic resonator is improved, a new mask plate with the release hole is not required to be formed, the process is simpler, and the process cost is saved.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

fig. 1A to 1B are schematic cross-sectional views illustrating a conventional film bulk acoustic resonator;

fig. 2A to 2N are schematic cross-sectional views showing structures obtained by sequentially performing the manufacturing method of the thin film bulk acoustic resonator according to the embodiment of the present invention;

FIG. 3 illustrates a partial top view of a thin film bulk acoustic resonator in accordance with an embodiment of the present invention;

fig. 4A to 4E are schematic cross-sectional views showing structures obtained by sequentially performing a manufacturing method of a thin film bulk acoustic resonator according to another embodiment of the present invention;

FIG. 5 is a flow chart illustrating a method of fabricating a thin film bulk acoustic resonator in accordance with an embodiment of the present invention;

fig. 6 shows a schematic view of an electronic device according to an embodiment of the invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

As shown in fig. 1A and 1B, however, the conventional process for manufacturing a thin film bulk acoustic resonator generally forms a bottom cavity in a substrate, forms a sacrificial material layer 101 in the bottom cavity, and then sequentially forms a lower electrode 102, a piezoelectric layer 103 and an upper electrode 104 on the sacrificial material layer 101, and in order to remove the sacrificial material layer 101 in the bottom cavity, it is generally required to form a release hole 105 sequentially penetrating the upper electrode 104, the piezoelectric layer 103 and the lower electrode 102, and using the release hole, the sacrificial material layer 101 in the bottom cavity is removed by a wet etching process to finally release the structure. However, due to the existence of the release holes, the upper electrode, the piezoelectric layer and the lower electrode are not continuous, which has a negative effect on the overall resonance performance of the film bulk acoustic resonator, and the release holes need to be opened by a new mask, so that the process is complicated and the process cost is increased.

In view of the above-mentioned problems, the present invention provides a method for manufacturing a thin film bulk acoustic resonator, as shown in fig. 5, including:

step S1, providing a substrate, forming a bottom cavity in the substrate, filling the bottom cavity with a sacrificial material layer,

step S2, sequentially forming a lower electrode, a piezoelectric layer and an upper electrode on a part of the surface of the sacrificial material layer and a part of the surface of the substrate, and exposing a part of the surface of the sacrificial material layer, wherein the upper electrode and the lower electrode are overlapped;

step S3, forming a dielectric layer to cover the front surface of the substrate, wherein the top surface of the dielectric layer is higher than the top surface of the upper electrode;

step S4, forming a top cavity penetrating through the dielectric layer, the top cavity exposing a portion of the upper electrode and a portion of the surface of the sacrificial material layer;

step S5, providing a cap substrate, and combining the cap substrate and the side of the base, on which the dielectric layer is formed;

step S6, forming at least one release hole, wherein the release hole penetrates through the base to expose part of the sacrificial material layer, or penetrates through the cap substrate to expose part of the top cavity;

step S7, removing the sacrificial material layer.

Example one

The method for manufacturing the thin film bulk acoustic resonator of the present invention will be explained and explained in detail with reference to fig. 2A to 2N, fig. 3, and fig. 5.

First, as shown in fig. 2C, a first step is performed, in which a substrate 201 is provided, a bonding pad 2043 and a bottom cavity are formed on a front surface of the substrate 201, and a sacrificial material layer 2061 is filled in the bottom cavity, wherein the bonding pad 2043 is annular in a top view and surrounds the bottom cavity.

The base 201 may be any suitable semiconductor substrate, such as a bulk silicon substrate, which may also be at least one of the following mentioned materials: the semiconductor layer may be a multilayer structure of Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductor, or may be a silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), or germanium-on-insulator (GeOI), or may be a Double Side Polished silicon wafer (DSP), or may be a ceramic substrate such as alumina, a quartz substrate, or a glass substrate.

In one example, as shown in fig. 2A, before forming the bonding pad, the method further includes: an isolation layer 202 is formed to cover the front surface of the substrate 201.

The material of the isolation layer 202 may be any suitable dielectric material, including but not limited to at least one of silicon oxide, silicon nitride, silicon oxynitride, and the like, the isolation layer 202 is used to increase the stability of the device structure, increase the isolation between the device and the substrate 201, reduce the resistivity requirement of the substrate 201, prevent the occurrence of leakage between the electrodes of the device, and the isolation layer may serve as a transition layer between the device (e.g., a lower electrode) and the substrate 201, improve the growth uniformity of the device structure, and the adhesion between the substrate and the device film layer, thereby improving the performance and reliability of the device.

The isolation layer 202 may be deposited on the substrate 201 by any suitable deposition method, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

Further, the thickness of the isolation layer 202 may be set reasonably according to the actual device process requirements, and is not limited herein.

In one example, the bonding pad 2043 is formed simultaneously with forming a first pad 2041 and a second pad 2042, the first pad 2041 and the second pad 2042 being located between the bonding pad 2043 and the bottom cavity, wherein the first pad is used for electrically connecting a subsequently formed lower electrode to draw out the lower electrode, and the second pad is used for electrically connecting a subsequently formed upper electrode to draw out the upper electrode.

In one example, as shown in fig. 2A and 2B, a method of forming the bonding pad 2043, the first pad 2041, and the second pad 2042 includes:

first, as shown in fig. 2A, a patterned first mask layer (not shown) is formed on the front surface of the substrate 201, and patterns of the first pads, the second pads, and the bonding pads are defined. Optionally, the material of the patterned first mask layer includes a photoresist material, and the patterned first mask layer is patterned by using a photolithography process to form a patterned first mask layer, where the patterned first mask layer exposes regions where the first pad, the second pad, and the bonding pad are to be formed.

Next, as shown in fig. 2A, the patterned first mask layer is used as a mask to etch a portion of the substrate to form a first groove 2031, a second groove 2032, and a third groove 2033, and when the isolation layer 202 is formed, the first groove 2031, the second groove 2032, and the third groove 2033 penetrate through the isolation layer 202 into the substrate 201.

The etching process may be a wet etching process or a dry etching process, wherein a dry etching process is preferably used, and the dry etching process includes but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting, followed by removal of the patterned first mask layer, e.g., by ashing, of the first mask layer of the photoresist mask material.

Next, as shown in fig. 2B, a first pad 2041, a second pad 2042 and the bonding pad 2043 are formed at the bottom of the first groove 2031, the second groove 2032 and the third groove 2033, respectively.

The material of the first bonding pad 2041, the second bonding pad 2042 and the bonding pad 2043 may comprise any suitable metal material, including but not limited to at least one metal of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, Sn, W and Al, preferably the material of the first bonding pad 2041, the second bonding pad 2042 and the bonding pad 2043 comprises Al.

The first pad 2041, the second pad 2042 and the bonding pad 2043 may be formed using any suitable method, for example, a pad material layer may be formed in the first groove 2031, the second groove 2032 and the third groove 2033 by a deposition method including, but not limited to, a physical vapor deposition method, a chemical vapor deposition method or magnetron sputtering, wherein the pad material layer in the first groove 2031 serves as the first pad 2041, the pad material layer in the second groove 2032 serves as the second pad 2042 and the pad material layer in the third groove serves as the bonding pad 2043.

It should be noted that the first bonding pad 2041, the second bonding pad 2042, and the bonding pad 2043 may also be formed by other suitable processes, for example, a bonding pad material layer may be formed first to cover the front surface of the substrate 201, and then patterned by using a photolithography process and an etching process to form the first bonding pad, the second bonding pad, and the bonding pad.

In one example, as shown in fig. 2B, after forming the first pad 2041, the second pad 2042 and the bonding pad 2043, forming a passivation layer 205 to cover the first pad 2041, the second pad 2042 and the bonding pad 2043 is further included.

The passivation layer 205 may be made of any suitable insulating material, for example, the passivation layer 205 is made of an inorganic insulating layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, and the passivation layer 205 may be formed by deposition such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition; an insulating layer or the like such as a layer containing polyvinyl phenol, polyimide, siloxane, or the like can also be used. Polyvinyl phenol, polyimide, or siloxane can be effectively formed by a droplet discharge method, printing, or spin coating method. Siloxanes can be classified according to their structure into silica glass, alkyl siloxane polymers, alkyl silsesquioxane polymers, silsesquioxane hydride polymers, alkyl silsesquioxane hydride polymers, and the like. Further, the insulating material may be formed with a material including a polymer having a Si — N bond (polysilazane). Further, these films may be stacked to form a passivation layer.

The thickness of the passivation layer may be any suitable thickness and is not particularly limited herein.

Optionally, after forming the passivation layer, the passivation layer may be planarized, for example, by chemical mechanical polishing, stopping on the surface of the isolation layer 202, so that the surface of the passivation layer 205 is flush with the surface of the isolation layer 202.

In one example, an opening exposing the first pad may be further formed in the passivation layer so that a subsequently formed lower electrode is in direct contact with the first pad to form an electrical connection.

In one example, after the bonding pad 2043 is formed, the bottom cavity is formed, as shown in fig. 2C, and the method of forming the bottom cavity includes: the method of forming the bottom cavity comprises: first, a patterned second mask layer (not shown) is formed on the front surface of the substrate 201, which defines the pattern of the bottom cavity; sequentially etching the isolation layer 202 and a part of the substrate 201 by using the patterned second mask layer as a mask to form the bottom cavity, wherein the bottom cavity penetrates through the isolation layer 202 to the substrate 201; and removing the patterned second mask layer.

Illustratively, the cross-sectional shape of the bottom cavity is any polygon with two parallel sides. The cross-section is taken by cutting the bottom cavity with a plane parallel to the surface of the substrate.

Optionally, as shown in fig. 2C, the bonding pad 2043 surrounds the bottom cavity, the first pad 2041 and the second pad 2042 are respectively disposed on two sides of the bottom cavity and between the bonding pad 2043 and the bottom cavity, or the first pad and the second pad are both disposed on the same side of the bottom cavity, and the first pad for electrically connecting to the lower electrode is disposed between the second pad and the bottom cavity.

Further, after forming the bottom cavity, the method further comprises: a sacrificial material layer 2061 is deposited to fill the bottom cavity, for example, the sacrificial material layer 2061 may be deposited to fill the bottom cavity and cover the substrate, and then a planarization process such as a chemical mechanical polishing is performed to stop on the surface of the isolation layer 202, so as to remove the excess sacrificial material layer on the surface of the substrate.

The material of the sacrificial material layer 2061 may be any suitable material, such as silicon oxide, germanium, polysilicon, photoresist, or amorphous carbon, and the sacrificial material layer 2061 may be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

It is worth mentioning that in other examples, the bottom cavity and the sacrificial material layer 2061 filling the bottom cavity may also be formed before forming the bond pad.

Next, step two is performed, as shown in fig. 2D, a lower electrode 2071 and a piezoelectric layer 2072 are sequentially formed on the sacrificial material layer 2061 and a part of the surface of the substrate 201, and a part of the surface of the sacrificial material layer 2061 is exposed.

Further, as shown in fig. 3, which is a schematic top view of a part of the structure of the FBAR, the top view is divided into an X axis and a Y axis perpendicular to each other on a plane, the top view shape of the lower electrode 2071 and the piezoelectric layer 2072 are both polygons with two arbitrary sides parallel, such as a quadrangle, a pentagon or a hexagon, wherein the shape of the piezoelectric layer 2072 may be especially a parallelogram, the lower electrode 2071 covers part of the sacrificial material layer, for example, the lower electrode covers the whole sacrificial material layer in the Y direction, while the sacrificial material layer at two ends is exposed in the X direction, the sacrificial material layer at two ends is exposed, and then the sacrificial material layer is used as a release passage of the sacrificial material layer, while the lower electrode and the piezoelectric layer 2072 are overlapped at the upper and lower parts, and the piezoelectric layer 2072 may extend a part of the length to the outside of the lower electrode in the Y direction.

Further, the bonding pads 2043 surround the lower electrode 2071 and the piezoelectric layer 2072.

The lower electrode 2071 may be made of a conductive material or a semiconductor material, wherein the conductive material may be a metal material having a conductive property, for example, one or more of aluminum (Al), copper (Cu), platinum (Pt), gold (Au), iridium (Ir), osmium (Os), rhenium (Re), palladium (Pd), rhodium (Rh), and ruthenium (Ru), or a metal thin film such as molybdenum (Mo) or tungsten (W). Any suitable semiconductor material, such as Si, Ge, SiGe, SiC, SiGeC, etc., may also be used for the lower electrode 2071.

The thickness of the lower electrode 2071 may be set according to the target resonance frequency, for example, about 1/10 of the wavelength.

In one example, a method of forming the lower electrode 2071 includes: first, a lower electrode material layer is formed to cover a surface of the substrate on which a sacrificial material layer is formed, for example, the first pad, the substrate, the passivation layer, and a portion of the surface of the sacrificial material layer. The lower electrode material layer may be formed by selecting an appropriate method according to a material of a lower electrode to be formed, and may be formed, for example, by magnetron sputtering, physical vapor deposition, or the like. Then, the lower electrode material layer is patterned to form the lower electrode 2071, for example, a photoresist layer with a lower electrode pattern defined thereon may be formed on the lower electrode material layer by using a photolithography process, and then the lower electrode material layer is etched by using the photoresist layer as a mask to form the lower electrode. Wherein the lower electrode covers the entire bottom cavity except for the region serving as the sacrificial material layer release via. After the lower electrode is formed, the photoresist layer is removed.

Further, as shown in fig. 2D, when the passivation layer 205 is covered on the first pad 2041, an opening exposing the first pad 2041 is formed in the passivation layer 205, and a part of the lower electrode formed subsequently covers the sidewall and the bottom of the opening and is electrically connected to the first pad.

Further, as a material of the piezoelectric layer 2072, a piezoelectric material having a wurtzite crystal structure such as ZnO, AlN, GaN, lead zirconate titanate, and lead titanate can be used, and in this embodiment, AlN is preferably used as the piezoelectric layer.

The piezoelectric layer 2072 can be deposited using any suitable method known to those skilled in the art, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

The thickness of the piezoelectric layer 2072 can be set according to the target resonance frequency, and is preferably set to about 1/2 of the wavelength.

Illustratively, the method of forming the piezoelectric layer 2072 includes: forming a piezoelectric material to cover the lower electrode, then forming a patterned mask layer on the piezoelectric layer 2072, defining a pattern of the piezoelectric layer 2072 to be formed, etching the piezoelectric material with the patterned mask layer as a mask to form the piezoelectric layer 2072, and finally removing the patterned mask layer.

Further, the cross-sectional shape of the piezoelectric layer may be a trapezoid, wherein one side of the trapezoid is perpendicular to the surface of the base, and the included angle between the other side wall and the surface of the base is an acute angle.

Next, step three is performed, as shown in fig. 2E, an upper electrode 2073 is formed on a part of the surface of the piezoelectric layer 2072 and a part of the surface of the substrate 201, and a part of the surface of the sacrificial material layer 2061 is exposed, and the upper electrode 2073 and the lower electrode 2071 are partially overlapped.

Illustratively, the top view shape of the upper electrode 2073 is a polygon with two parallel sides, such as a quadrangle, a pentagon, a hexagon, a heptagon, or an octagon, and particularly may be a parallelogram.

The top electrode 2073 may partially cover the bottom cavity, and the bottom cavity is filled with a sacrificial material layer, so that the top electrode is located above the sacrificial material layer, and the overlapping region of the bottom electrode and the top electrode is entirely located above the bottom cavity.

In one example, a method of forming the upper electrode 2073 includes: depositing an upper electrode material layer to cover the substrate, for example, covering a part of the isolation layer 202, the passivation layer 205, and the piezoelectric layer 2072, forming a patterned mask layer on the upper electrode material layer, defining a pattern of the upper electrode, etching the upper electrode material layer using the patterned mask layer as a mask to form an upper electrode 2073, and finally removing the patterned mask layer.

Further, one end of the upper electrode extends outward from the piezoelectric layer to the second pad 2042, so that the upper electrode is electrically connected to the second pad, where when the passivation layer 205 is covered on the second pad, before forming the upper electrode, the method further includes: and forming an opening in the passivation layer to expose the second pad, wherein the upper electrode covers the bottom and the side wall of the opening and is electrically connected with the second pad.

The upper electrode 2073 may be made of a conductive material or a semiconductor material, wherein the conductive material may be a metal material with conductive performance, and the metal material may be a metal such as aluminum (Al), copper (Cu), gold (Au), platinum (Pt), or an alloy of the metal and the copper. The semiconductor material may use Si, Ge, SiGe, SiC, SiGeC, or the like. The thickness of the upper electrode 2073 may be set according to the target resonance frequency, and is preferably set to about 1/10 of the wavelength.

The upper electrode 2073 may be formed by Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Metal Organic Chemical Vapor Deposition (MOCVD), and Atomic Layer Deposition (ALD) or other advanced deposition techniques.

The lower electrode 2071, the piezoelectric layer 2072 and the upper electrode 2073 form an acoustic wave resonance composite film of the acoustic wave resonator, and the acoustic wave resonance composite film may further include other film layers besides the above film layers, and may be reasonably arranged according to actual devices, which is not limited herein.

Next, step four is performed, as shown in fig. 2F, a dielectric layer 208 is formed to cover the front surface of the substrate 201, and a top surface of the dielectric layer 208 is higher than a top surface of the upper electrode 2073. The FBAR meets the required boundary conditions through subsequent photoetching and etching;

the material of the dielectric layer 208 may include, but is not limited to, silicon oxide or silicon nitride, such as SiO₂Fluorocarbon (CF), silicon oxide doped with carbon (SiOC), silicon nitride (SiN), or silicon carbonitride (SiCN). Alternatively, a film in which a SiCN thin film is formed on fluorocarbon (CF) or the like may be used. The fluorocarbon compound contains fluorine (F) and carbon (C) as main components. As the fluorocarbon, a fluorocarbon having an amorphous (non-crystalline) structure may be used.

The dielectric layer 208 may be formed by any deposition process known to those skilled in the art, such as a chemical vapor deposition process, a physical vapor deposition process, and the like, wherein the chemical vapor deposition process may be selected from a thermal chemical vapor deposition (thermal CVD) process or a High Density Plasma (HDP) process.

The deposition thickness may be selected as appropriate according to the size of the device to be formed, and is not particularly limited herein.

Next, step five is performed, with continued reference to fig. 2F, to form a top cavity 209 penetrating the dielectric layer 208, wherein the top cavity 209 exposes a portion of the upper electrode 2073 and a portion of the surface of the sacrificial material layer 2061.

The top cavities 209 may be formed using any suitable method known to those skilled in the art, such as by a photolithographic process, forming a mask layer on the dielectric layer 208 defining the pattern of the top cavities 209, etching the dielectric layer 208 using the mask layer as a mask until the upper electrode 2073 is exposed to form the top cavities 209, and finally removing the mask layer.

Illustratively, as shown in fig. 3, the cross-sectional shape of the top cavity 209 is a polygon with two parallel sides, such as a quadrangle, a pentagon, a hexagon, etc., and particularly may be a parallelogram. This cross-section refers to the interface obtained by truncating the top cavity 209 with a plane parallel to the surface of the substrate.

Wherein the size of the top cavity may be larger than the size of the bottom cavity, thereby exposing a portion of the sacrificial material layer filled in the bottom cavity.

Next, step six is performed, as shown in fig. 2G, an opening 210 exposing the bonding pad 2043 is formed in the dielectric layer 208.

The method for forming the opening 210 may use any suitable method known to those skilled in the art, for example, defining a pattern of the opening by a photolithography process, forming a patterned mask layer on the dielectric layer, and etching the dielectric layer 208 by using the mask layer as a mask until the bonding pad 2043 is exposed, where the etching may be dry etching or wet etching, and the top view shape of the opening is also a ring shape, such as a circular ring shape or a square ring shape, since the bonding pad 2043 is exposed.

The opening 210 serves to expose the bond pad to facilitate subsequent bonding of the bond pad to the bond ring.

Subsequently, step seven is performed, as shown in fig. 2I, providing a cap substrate 300 on which a groove 302 and a bonding ring 301 protruding around the groove 302 are formed.

The material of the cap substrate 300 may be any semiconductor substrate, such as a bulk silicon substrate, which may also be at least one of the following materials: the semiconductor layer may be a multilayer structure of Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductor, or may be a silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), or germanium-on-insulator (GeOI), or may be a Double Side Polished silicon wafer (DSP), or may be a ceramic substrate such as alumina, a quartz substrate, or a glass substrate.

Optionally, the bonding ring 301 and the opening 210 in the dielectric layer 208 are matched, for example, the size of the opening 210 may be larger than the size of the bonding ring 301, such that upon subsequent bonding, the bonding ring may be inserted into the opening 210 to engage the bonding pad.

Further, the height of the bonding ring 301 may be made larger than the depth of the opening 210, so that the bonding ring 301 can contact with the bonding pad at the bottom of the opening 210.

In one example, the top of the bond ring 301 includes a layer of bonding material 3011.

In one example, as shown in fig. 2H to 2J, the method of forming the bonding ring 301 and the groove includes:

first, as shown in fig. 2H, a bonding material layer 3011 is formed to cover the surface of the cap substrate 300. The bonding material layer 3011 includes a material capable of bonding with the bonding pad, for example, a material capable of forming a eutectic bond with the bonding pad. Illustratively, the bonding material layer 3011 may include, but is not limited to, at least one of Au, Sn, Ge, Si, and the like, and particularly, an appropriate bonding material layer may be selected according to a material of the bonding pad, for example, when the material of the bonding pad includes Al, the material of the bonding material layer may include at least one of Cu, Ge, or Si, and when the material of the bonding pad includes Au, the material of the bonding material layer may include at least one of Si, Sn, and Ge.

The thickness of the bonding material layer 3011 can be set reasonably according to actual process requirements, and is not limited specifically here.

The bonding material layer may be formed using any deposition method known to those skilled in the art, such as magnetron sputtering, physical vapor deposition, or evaporation.

Next, a patterned mask layer is formed on the surface of the bonding material layer 3011, where the patterned mask layer defines a pattern of a bonding ring and a trench to be formed, that is, the patterned mask layer covers an area to be a bonding ring and exposes an area to be a trench to be formed by etching.

A patterned photoresist layer may be formed on the surface of the bonding material layer 3011 by a photolithography process.

Next, as shown in fig. 2I and fig. 2J, the bonding material layer 3011 and a portion of the cap substrate 300 are sequentially etched by using the patterned mask layer as a mask to form the bonding ring 301 and the trench 302, where the etching may be dry etching or wet etching, preferably dry etching, where the bonding ring 301 and the bonding pad 2043 are matched. And finally, removing the patterned mask layer.

Subsequently, step eight is performed, as shown in fig. 2K, the bonding ring 301 and the bonding pad 2043 are bonded to achieve the bonding of the cap substrate 300 and the base 201, and the trench encloses the top cavity 209.

Specifically, the bonding ring 301 is inserted into the opening to contact with the bonding pad 2043, and a bonding process is performed to melt and contact the bonding material layer 3011 and the bonding pad 2043 on the bonding ring 301, so as to form a liquid-phase alloy with eutectic composition, such as an aluminum-germanium liquid-phase alloy, after diffusion, the liquid-phase alloy layer is thickened continuously as diffusion time increases, and after cooling, the metal in the liquid-phase alloy layer grows on the basis of the original solid phase of the metal, and two metals are alternately precipitated continuously to form a more stable crystal structure, so that bonding is achieved.

The parameters of the bonding process, such as bonding temperature, time, pressure, etc., may depend on the material of the bonding material layer and the material of the bonding pad, for example, a bonding temperature of 420 ℃ to 480 ℃ may be used, a bonding time of 2 minutes to 20 minutes, such as 5min, 10 minutes, 15 minutes, etc., and a bonding pressure of 5000mbar to 8000mbar, etc.

Wherein the dimensions of the trench on the cap substrate are larger than the dimensions of the top cavity 209 such that the entire top cavity 209 is enclosed within the trench.

It is worth mentioning that the above method only shows one of the methods of bonding the cap substrate and the base substrate by bonding the bonding pad and the bonding ring, and for other bonding methods, such as silicon-silicon direct bonding processes, e.g., Si-Si, Si-SiO₂And SiO₂-SiO₂Bonding and the like are also applicable to the present invention.

Subsequently, step nine is performed, as shown in fig. 2M, to remove the sacrificial material layer.

In one example, after bonding the bonding ring 301 and the bonding pad 2043, and before removing the sacrificial material layer 2061, as shown in fig. 2L, the method further includes: an interconnection structure 211 is formed on the back surface of the substrate to electrically connect the lower electrode 2071 and the upper electrode 2073, for example, when the lower electrode 2071 is electrically connected to the first pad 2041 and the upper electrode 2073 is electrically connected to the second pad, the interconnection structure 211 may be electrically connected to the first pad 2041 and the second pad 2042, respectively, so as to electrically connect to the lower electrode and the upper electrode, respectively.

The interconnect structure 211 may be formed using any suitable method known to those skilled in the art, the interconnect structure 211 further comprising plugs formed in the substrate, the plugs electrically connecting the first and second pads, respectively, and an interconnect metal layer formed on the backside of the substrate. The material of the interconnect structure 211 may be any suitable metal material, including but not limited to copper, gold, tungsten, aluminum, and the like.

The interconnect structure 211 may further include a plurality of interconnect metal layers and a plug electrically connecting the interconnect metal layers of adjacent layers.

In one example, the backside of the substrate may also be selectively thinned prior to forming the interconnect structure 211. The thinning method may be a chemical mechanical polishing method or an etching method, and is not specifically limited herein.

In one example, a release hole (not shown) may also be formed in the trench bottom of the cap substrate prior to bonding the cap substrate to the base, the release hole extending through the cap substrate for subsequent removal of the sacrificial material layer.

Alternatively, in another example, as shown in fig. 2M, after the cap substrate is bonded to the base, a release hole 303 is formed through the cap substrate 300 exposing a portion of the top cavity 209, which may be formed by any suitable method known to those skilled in the art, such as etching the cap substrate 300 using a photolithography process and an etching process.

In other embodiments, at least one release hole penetrating the substrate from the back surface of the substrate and exposing a portion of the sacrificial material layer may be formed after thinning the back surface of the substrate.

The number of the release holes can be set as appropriate according to the actual process requirements, and can be, for example, 1, 2, 3, 4, 5, etc.

After the release holes are formed, the sacrificial material layer is removed, specifically, as shown in fig. 2M, wherein the sacrificial material layer may be removed by wet etching or dry etching, wherein an etchant of the wet etching enters the top cavity 209 enclosed by the cap substrate 300 through the release holes 303 (as shown by arrows in fig. 2M) to contact with the sacrificial material layer exposed in the top cavity 209, so as to etch and remove the sacrificial material layer, and release the bottom cavity 206. As shown in fig. 3, the upper electrode 2073 in the top cavity 209 only covers part of the piezoelectric layer 2072 and the lower electrode 2071, and the release channel that keeps the sacrificial material layer is exposed in the top cavity 209, once an etchant enters into the top cavity and contacts the sacrificial material layer, the etchant etches the sacrificial material layer, and the etchant has a high etching selectivity of the sacrificial material layer to the upper electrode, the lower electrode, the substrate, the cap substrate, the piezoelectric layer, etc., and does not damage other exposed film layers while etching the sacrificial material layer.

Illustratively, the sacrificial material layer is etched by selecting a suitable etchant according to the material of the sacrificial material layer, for example, when the sacrificial material layer comprises silicon nitride, the sacrificial material layer can be removed by a wet method using hot phosphoric acid as the etchant.

After removal of the sacrificial material layer, the bottom cavity 206 is obtained. As shown in fig. 3, the top cavity 209 and the bottom cavity 206 are opposite to each other, and the cross-sectional shapes of the top cavity 209 and the bottom cavity 206 may be polygons, where the top cavity 209 and the bottom cavity 206 have an overlapped portion (also referred to as an overlapped effective area), and the overlapped portion forms a common inner circumference, and a projection of the common inner circumference on a plane where the piezoelectric layer is located is a polygon, such as a quadrangle, a pentagon, a hexagon, a heptagon, an octagon, and the like, and the polygon should not include any pair of opposite and parallel straight line segments. In order to avoid horizontal acoustic resonance generated at any point of the acoustic resonance composite film, horizontal direction propagation to the boundary of the common inner periphery of the polygon generates reflection, and the reflection continuously propagates and generates derivative horizontal resonance, and the common inner periphery of the polygon does not contain any pair of opposite and parallel straight line segments.

Subsequently, as shown in fig. 2N, an encapsulant 304 is further formed to fill the release hole, seal the top cavity 209, and maintain the vacuum seal of the top cavity 209 with a vacuum degree of less than 1Mbar, so as to ensure the normal operation of the device, and further, the encapsulant 304 further covers the top surface of the cap substrate 300.

The sealing material 304 may be any sealing material known to those skilled in the art, such as silicon dioxide, and the sealing material 304 may be the same material as the dielectric layer.

Thus, the introduction of the key manufacturing method of the semiconductor device of the present invention is completed, and other pre-steps, intermediate steps or subsequent steps are required for the complete device manufacturing, which is not described herein again.

In summary, in the method for manufacturing the film bulk acoustic resonator of the present invention, the release hole penetrating through the exposed portion of the sacrificial material layer of the substrate is formed, or the release hole penetrating through the exposed portion of the cap substrate and the top cavity is formed, and the release hole is used for removing the sacrificial material layer, and the release structure does not need to form a release hole for removing the sacrificial material layer in the lower electrode, the piezoelectric layer, and the upper electrode, so that the continuity of the lower electrode, the piezoelectric layer, and the upper electrode is ensured, the resonance performance of the film bulk acoustic resonator is improved, and a new mask plate with the release hole is not needed, the process is simpler, and the process cost is saved.

Example two

The invention also provides a method for manufacturing the film bulk acoustic resonator, which has the same steps as those shown in the first embodiment, and detailed description is not given here, but only for the steps of the two methods which are obviously different.

Specifically, the method of manufacturing the thin film bulk acoustic resonator in the present embodiment is described in detail below with reference to fig. 4A to 4E.

Illustratively, the method for manufacturing a film bulk acoustic resonator of the present invention includes:

first, as shown in fig. 2A to 2D, a first step is performed to provide a substrate 201, a bottom cavity is formed in the substrate 201, and a sacrificial material layer 2061 is filled in the bottom cavity; among them, the method of forming the bottom cavity and the sacrificial material layer 2061 may refer to the foregoing embodiment.

In one example, prior to forming the bottom cavity, forming an isolation layer 202 on the front side of the substrate is also included.

Further, before the lower electrode is formed, a first pad 2041 and a second pad 2042 are formed, the first pad 2041 and the second pad 2042 are located at two sides of the bottom cavity, the lower electrode is electrically connected to the first pad, and the upper electrode is electrically connected to the second pad. Specifically, the method for forming the first pad and the second pad may use the method in the first embodiment, and in this embodiment, the bonding pad in the first embodiment does not need to be formed.

In one example, after forming the first and

second pads

2041 and 2042, forming a passivation layer 205 covering the first and

second pads

2041 and 2042 is further included.

Next, step two is performed, as shown in fig. 2D to fig. 2E, a lower electrode 2071, a piezoelectric layer 2072 and an upper electrode 2073 are sequentially formed on the partial surface of the sacrificial material layer 2061 and the partial surface of the substrate 201, and the upper electrode 2073 and the lower electrode 2071 are partially overlapped.

Next, step three is performed, as shown in fig. 2F and fig. 4A, a dielectric layer 208 is formed to cover the front surface of the substrate 201, and a top surface of the dielectric layer 208 is higher than a top surface of the upper electrode 2073; the FBAR meets the required boundary conditions through subsequent photoetching and etching;

next, step four is performed to form a top cavity 209 penetrating through the dielectric layer 208, wherein the top cavity 209 exposes a portion of the upper electrode 2073; specific methods for forming the top cavity 209, and the like can refer to the first embodiment described above.

Next, step five is performed, as shown in fig. 4A and 4B, a cap substrate 300 is provided, and the cap substrate 300 is bonded to the side of the base 201 on which the dielectric layer 208 is formed.

Illustratively, as shown in fig. 4B, the method of bonding the cap substrate 300 to the side of the base 201 on which the dielectric layer 208 is formed includes: the cap substrate 300 is directly bonded to the dielectric layer 208, for example, by a silicon-silicon direct bonding process, e.g., Si-Si, Si-SiO₂And SiO₂-SiO₂Bonding methods such as bonding.

The cap substrate 300 seals the top cavity 209 after bonding to form a closed vacuum chamber.

Next, step six is executed, as shown in fig. 4C, the back surface of the substrate 201 is thinned.

The thinning of this step may be performed using any suitable process, such as a mechanical grinding (grinding) process, a chemical mechanical grinding process, or an etching process, among others. The thickness of the thinned substrate may be set reasonably according to the actual process, for example, the thickness of the thinned substrate 100 is between 10 μm and 100 μm, or the thickness may vary according to the difference of the technology nodes, and is not limited specifically herein.

Next, step seven is executed, as shown in fig. 4D, at least one release hole 212 is formed on the back surface of the substrate, and the release hole penetrates through the substrate to expose a portion of the sacrificial material layer.

The substrate 201 may be etched from its backside using a photolithography process and an etching process until a portion of the sacrificial material layer is exposed through the substrate.

In another example, the cap substrate may be etched to form a release hole in the cap substrate opposite the top cavity, the release hole extending through the cap substrate and exposing a portion of the top cavity.

Next, step eight is performed, and as shown in fig. 4D, the sacrificial material layer is removed to release the structure, so as to obtain the bottom cavity 206.

The sacrificial material layer may be removed by any suitable dry etching or wet etching method, preferably by wet etching, during which an etchant contacts the sacrificial material layer through the release holes 212 to etch and remove the sacrificial material layer. The etchant used for the etching can refer to the first embodiment.

Next, step nine is performed, referring to fig. 4E, a sealing material 213 is formed to fill the release hole 212.

When the release hole is formed on the back surface of the substrate, the sealing material fills the release hole to seal the bottom cavity 206, so that the bottom cavity 206 is kept vacuum-sealed to ensure the normal operation of the device, and further, the sealing material 213 further covers the back surface of the substrate 201.

The sealing material 213 may be any sealing material known to those skilled in the art, such as silicon dioxide, and the sealing material 213 may be the same material as the dielectric layer.

In one example, when the release hole is formed in the cap substrate, then the sealing material fills the release hole.

Subsequently, an interconnection structure 211 is formed on the back surface of the substrate to electrically connect the lower electrode 2071 and the upper electrode 2073, for example, when the lower electrode 2071 is electrically connected to the first pad 2041 and the upper electrode 2073 is electrically connected to the second pad 2042, the interconnection structure 211 can electrically connect the first pad 2041 and the second pad 2042, respectively, so as to electrically connect the lower electrode and the upper electrode, respectively.

In one example, forming the interconnect structure includes first forming vias through the sealing material 213 and a portion of the substrate 201 over the first and second pads, respectively, which vias expose the first and

second pads

2041 and 2042, respectively, then filling the vias with a conductive material to form plugs, and then forming a wiring layer on the backside of the substrate to electrically connect the corresponding plugs, respectively.

Thus, the explanation and the explanation of the manufacturing method in this embodiment are completed, and the preparation of the complete device may include other steps, which are not described in detail herein.

The manufacturing method of the present embodiment also has the advantages of the manufacturing method of the first embodiment.

EXAMPLE III

The invention also provides a film bulk acoustic resonator, which can be prepared by the method in the first embodiment.

Hereinafter, the film bulk acoustic resonator of the present invention will be described and explained in detail with reference to fig. 2N and 3, and it should be noted that, in order to avoid repetition, the same components and structures as those in the first embodiment will be described only briefly, and the detailed explanation and explanation thereof will be referred to the description of the first embodiment.

Specifically, the film bulk acoustic resonator of the present invention includes a substrate 201, wherein the substrate includes a front surface and a back surface opposite to the front surface.

Further, a bottom cavity 206 is formed in the substrate 201, wherein the bottom cavity is recessed into the substrate from the front surface of the substrate.

Illustratively, the cross-sectional shape of the bottom cavity 206 is any polygon with two parallel sides. The cross-section is taken by cutting the bottom cavity with a plane parallel to the surface of the substrate.

In one example, the film bulk acoustic resonator further includes a lower electrode 2071 formed on the front surface of the substrate 201 and covering at least a portion of the bottom cavity 206.

Illustratively, a piezoelectric layer 2072 is disposed on the lower electrode, and an upper electrode 2073 is disposed on the piezoelectric layer 2072, wherein the piezoelectric layer covers the lower electrode 2071 and isolates the lower electrode 2071 from the upper electrode 2073, and optionally, the upper electrode 2073 covers part of the piezoelectric layer 2072.

Further, as shown in fig. 3, which is a schematic top view of a part of the structure of the FBAR, the top view is divided into an X axis and a Y axis perpendicular to each other on a plane, the top view shapes of the lower electrode 2071, the piezoelectric layer 2072 and the upper electrode 2073 are all polygons with two parallel sides, such as a quadrangle, a pentagon or a hexagon, the lower electrode 2071 covers part of the bottom cavity 206, for example, the lower electrode covers the whole bottom cavity 206 in the Y direction, the bottom cavities 206 at two ends are exposed in the X direction, and at the same time, the lower electrode and the piezoelectric layer 2072 are overlapped up and down, and the piezoelectric layer 2072 may extend a part of the length to the outside of the lower electrode in the Y direction.

The material of the upper electrode 2073 and the lower electrode 2071 may be a conductive material or a semiconductor material, wherein the conductive material may be a metal material having a conductive property, and the metal material may be a metal such as aluminum (Al), copper (Cu), gold (Au), platinum (Pt), or an alloy of the metal and the copper. The semiconductor material may use Si, Ge, SiGe, SiC, SiGeC, or the like. The thicknesses of the upper electrode 2073 and the lower electrode 2071 may be set according to a target resonance frequency, and preferably, the thicknesses of the upper electrode 2073 and the lower electrode 2071 may be set to about 1/10 of the wavelength.

In one example, an isolation layer 202 is disposed between the lower electrode 2071 and the substrate 201, and the bottom cavity 206 penetrates the isolation layer 202 into the substrate 201.

In one example, a bonding pad 2043 is further formed on the front surface of the substrate 201, wherein the bonding pad 2043 has a ring shape in a top view and surrounds the bottom cavity 206.

In one example, the film bulk acoustic resonator of the present invention further includes: a first pad 2041 and a second pad 2042, the first pad 2041 and the second pad 2042 are located on the substrate 201 between the bonding pad 2043 and the bottom cavity 206 and are located below the lower electrode 2071, the lower electrode 2071 is electrically connected with the first pad 2041, the upper electrode 2073 is electrically connected with the second pad 2042, and the upper electrode and the lower electrode are isolated from each other.

Illustratively, a first groove, a second groove and a third groove are further formed in the substrate 201, and the first pad 2041, the second pad and the bonding pad are respectively disposed at the bottoms of the first groove, the second groove and the third groove.

In one example, the first, second, and third grooves extend through the isolation layer 202 into the substrate 201.

Illustratively, the first pad 2041 and the second pad 2042 are respectively located at two sides of the bottom cavity 206, wherein an end of the lower electrode 2071 as a lead is located on a surface of the first pad 2041 and electrically connected to the first pad, and an end of the upper electrode 2073 as a lead is located on the second pad 2042 and electrically connected to the second pad 2042, optionally, a plug may be further disposed between the first pad 2041 and the lower electrode 2071 to electrically connect the first pad 2041 and the lower electrode 2071, and a plug may be further disposed between the second pad 2042 and the upper electrode 2073 to electrically connect the second pad 2042 and the upper electrode 2073.

In one example, a dielectric layer 208 covering the front surface of the substrate is further included, and a top surface of the dielectric layer 208 is higher than a top surface of the upper electrode 2073.

In one example, a passivation layer 205 may be further selectively disposed between the dielectric layer and the first, second and bond pads.

In one example, an opening penetrating the passivation layer 205 and exposing the first pad 2041 is provided in the passivation layer 205, wherein one end of the lower electrode 2071 is located at the bottom of the opening and electrically connected to the first pad 2041.

In one example, an opening penetrating the passivation layer 205 and exposing the second pad 2042 is provided in the passivation layer 205, wherein one end of the upper electrode 2073 is located at the bottom of the opening and electrically connected to the second pad 2042.

Further, the dielectric layer 208 covers a portion of the isolation layer 202 and a portion of the passivation layer 205.

In one example, the top cavity 209 is further included, the top cavity 209 penetrates through the dielectric layer 208 and exposes at least a portion of the upper electrode 2073, wherein when the upper electrode 2073 covers a portion of the piezoelectric layer 2072, the top cavity 209 also exposes a portion of the piezoelectric layer 2072, and wherein the upper electrode 2073 not exposed at the top cavity 209 is covered by the portion of the dielectric layer 208.

Further, the top cavity 209 may have a size larger than the bottom cavity 206, such that a portion of the bottom cavity 206 is exposed in the top cavity 209.

It is noted that the rectangular region shown in fig. 3 may represent an area of overlap between the upper electrode 2073 and the top cavity 209.

Optionally, the cross-sectional shape of the top cavity 209 is any polygon with two parallel sides, such as a quadrangle, a pentagon, a hexagon, a heptagon, or an octagon.

It is worth mentioning that in the present invention, the top view shapes of the upper electrode, the lower electrode and the piezoelectric layer and the cross-sectional shapes of the bottom cavity and the top cavity may also be other suitable shapes.

In one example, a cap substrate 300 is also disposed over the base.

Further, a trench is provided in the cap substrate that encloses the top cavity. Optionally, the dimensions of the trench are larger than the dimensions of the top cavity, so that the trench can encapsulate all of the top cavity.

Illustratively, the semiconductor device further comprises a protruding bonding ring 301 disposed on the cap substrate, wherein the bonding ring 301 is bonded to the bonding pad 2043. Wherein the bonding ring 301 surrounds the groove. Wherein the bonding ring and the trench are obtained by etching a cap substrate.

Optionally, the bonding ring 301 and the opening in the dielectric layer 208 exposing the bonding pad are matched, e.g., the size of the opening may be larger than the size of the bonding ring 301 inserted into the opening to engage the bonding pad, i.e., the bonding ring engages the bonding pad through the dielectric layer.

Further, the height of the bonding ring 301 may be made larger than the depth of the opening in the dielectric layer 208 exposing the bonding pad, so that the bonding ring 301 can contact the bonding pad at the bottom of the opening.

In one example, the top of the bonding ring 301 further includes a bonding material layer 3011, and the bonding material layer 3011 is a material capable of forming eutectic bonding with the bonding pad.

In one example, as shown in fig. 2N, a release hole is also included through the cap substrate opposite the top cavity.

Or, in another example, the release hole penetrates through the substrate and is opposite to the bottom cavity, namely, the release hole exposes a part of the bottom cavity.

Further, as shown in fig. 2N, a sealing material 304 is further included, the sealing material 304 fills the release hole, seals the top cavity 209, and keeps the top cavity 209 vacuum-sealed to ensure the normal operation of the device, and further, the sealing material 304 further covers the top surface of the cap substrate 300.

In one example, as shown in fig. 2N, an interconnection structure 211 is formed on the back surface of the substrate to electrically connect the lower electrode 2071 and the upper electrode 2073, respectively, and when the lower electrode 2071 is electrically connected to the first pad 2041 and the upper electrode 2073 is electrically connected to the second pad, the interconnection structure 211 may electrically connect the first pad and the second pad, respectively, so as to electrically connect the lower electrode and the upper electrode, respectively.

The material of the interconnect structure 211 may be any suitable metal material, including but not limited to copper, gold, tungsten, aluminum, and the like.

As shown in fig. 3, the top cavity 209 and the bottom cavity 206 are opposite to each other, and the cross-sectional shapes of the top cavity 209 and the bottom cavity 206 may be polygons, and the top cavity 209 and the bottom cavity 206 have overlapped portions (also referred to as overlapped effective areas, which refers to areas corresponding to overlapped areas of the upper electrode, the piezoelectric layer, and the lower electrode), and the overlapped portions form a common inner circumference, and a projection of the common inner circumference on a plane where the piezoelectric layer is located is a polygon, such as a quadrangle, a pentagon, a hexagon, a heptagon, an octagon, and the like, and the polygon should not include any pair of opposite and parallel straight line segments. In order to avoid horizontal acoustic resonance generated at any point of the acoustic resonance composite film, horizontal direction propagation to the boundary of the common inner periphery of the polygon generates reflection, and the reflection continuously propagates and generates derivative horizontal resonance, and the common inner periphery of the polygon does not contain any pair of opposite and parallel straight line segments.

According to the film bulk acoustic resonator, the release holes for removing the sacrificial material layer are not formed in the lower electrode, the piezoelectric layer and the upper electrode, so that the lower electrode, the piezoelectric layer and the upper electrode have good continuity, and the resonance performance of the film bulk acoustic resonator is improved.

Example four

The invention also provides a film bulk acoustic resonator as shown in fig. 4E, which is prepared by the method in the second embodiment. Only the portions of the film bulk acoustic resonator different from the film bulk acoustic resonator in the third embodiment are described in detail herein, and the other portions that are the same as those in the previous embodiments are not described herein again.

The film bulk acoustic resonator in this embodiment includes: a substrate 201; a bottom cavity 206 formed in the base; a lower electrode 2071 formed on the front surface of the substrate 201 and covering at least a part of the bottom cavity 206; a piezoelectric layer 2072 provided on the lower electrode 2071; an upper electrode 2073 disposed on the piezoelectric layer 2072; a dielectric layer 208 covering the front surface of the substrate 201, and a top surface of the dielectric layer 208 is higher than a top surface of the upper electrode 2073; a top cavity extending through the dielectric layer 208 and exposing at least a portion of the top electrode 2073.

In one example, the package further includes a first pad 2041 and a second pad 2042, the first pad 2041 and the second pad 2042 are located at two sides of the bottom cavity 206, the lower electrode 2071 is electrically connected to the first pad 2041, and the upper electrode 2073 is electrically connected to the second pad 2042. Specifically, in this embodiment, the bonding pad of the first embodiment is not included.

Further, a cap substrate 300 is provided on the base 201 and bonded to the side of the base 201 where the dielectric layer 208 is provided. Wherein the cap substrate 300 and the dielectric layer 208 are bonded directly together, the cap substrate 300 sealing the top vacancy 209.

In one example, the substrate 201 further includes a release hole, which is opposite to the bottom cavity 206 and penetrates through the substrate 201, that is, the release hole penetrates through the substrate 201 from the back surface of the substrate 201 and exposes a portion of the bottom cavity 206.

Further, an encapsulant 213 is further included, which fills the release hole to seal the bottom cavity 206, so that the bottom cavity 206 is kept vacuum-sealed to ensure the normal operation of the device, and further, the encapsulant 213 further covers the back surface of the substrate 201.

In one example, as shown in FIG. 3, the cross-sectional shape of the bottom cavity is a polygon with any two parallel sides; the overlooking shape of the lower electrode is a polygon with any two parallel sides; the overlooking shape of the piezoelectric layer is a polygon with any two parallel sides; the overlooking shape of the upper electrode is a polygon with any two parallel sides; the cross section of the top cavity is in a polygonal shape with any two parallel sides.

Further, the overlapped parts of the top cavity and the bottom cavity form a common inner circumference, the projection of the common inner circumference on the plane of the piezoelectric layer is an irregular polygon, and the polygon does not contain any pair of opposite and parallel straight line segments.

So far, the explanation and explanation of the thin film bulk acoustic resonator of another embodiment of the present invention have been completed, and the device also has the advantages of the device in the foregoing embodiment.

EXAMPLE five

In another embodiment of the present invention, an electronic device is further provided, which includes the foregoing thin film bulk acoustic resonator, and the thin film bulk acoustic resonator is prepared according to the foregoing method.

The electronic device of this embodiment may be any electronic product or device, such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, and the like, and may also be any intermediate product including a circuit. The electronic device of the embodiment of the invention has better performance due to the use of the film bulk acoustic resonator.

Wherein figure 6 shows an example of a mobile telephone handset. The mobile phone handset 400 is provided with a display portion 402, operation buttons 403, an external connection port 404, a speaker 405, a microphone 406, and the like, which are included in a housing 401.

Wherein the mobile phone handset includes the film bulk acoustic resonator described in the third embodiment or the fourth embodiment, the film bulk acoustic resonator includes:

a substrate;

a bottom cavity formed in the substrate;

a piezoelectric layer disposed on the lower electrode;

an upper electrode disposed on the piezoelectric layer;

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A method of manufacturing a film bulk acoustic resonator, comprising:

sequentially forming a lower electrode, a piezoelectric layer and an upper electrode on part of the surface of the sacrificial material layer and part of the surface of the substrate, and exposing part of the surface of the sacrificial material layer; wherein, the forming of the lower electrode, the piezoelectric layer and the upper electrode on the partial surface of the sacrificial material layer and the partial surface of the substrate in sequence to expose the partial surface of the sacrificial material layer comprises: sequentially forming a lower electrode and a piezoelectric layer on the sacrificial material layer and part of the surface of the substrate, exposing part of the surface of the sacrificial material layer, and forming an upper electrode on part of the surface of the piezoelectric layer and part of the surface of the substrate, exposing part of the surface of the sacrificial material layer; wherein the upper electrode and the lower electrode are overlapped at the upper part and the lower part; wherein the upper electrode and the lower electrode are overlapped at the upper part and the lower part;

and removing the sacrificial material layer.

2. The method of manufacturing according to claim 1, wherein the cross-sectional shape of the bottom cavity is a polygon with any two parallel sides;

3. The manufacturing method according to claim 1 or 2, wherein the overlapped portions of the top cavity and the bottom cavity form a common inner circumference, and a projection of the common inner circumference on a plane where the piezoelectric layer is located is an irregular polygon which does not include any pair of opposing and parallel straight line segments.

4. The manufacturing method according to claim 1, wherein the sacrificial material layer is removed by wet etching or dry etching.

5. The method of manufacturing according to claim 1, wherein the method of bonding the cap substrate to the side of the base on which the dielectric layer is formed comprises:

providing the cap substrate, and forming a groove and a bonding ring protruding around the groove on the cap substrate;

6. The method of manufacturing of claim 1, further comprising: before the lower electrode is formed, a first bonding pad and a second bonding pad are formed, the first bonding pad and the second bonding pad are located on two sides of the bottom cavity, the lower electrode is electrically connected with the first bonding pad, and the upper electrode is electrically connected with the second bonding pad.

7. The method of manufacturing of claim 1, wherein a top portion of the bonding ring comprises a layer of bonding material.

8. The method of manufacturing of claim 1, wherein after joining the cap substrate and the base, before or after removing the layer of sacrificial material, further comprises:

9. The method of manufacturing of claim 1, further comprising, prior to forming the release hole through the substrate exposing the portion of the layer of sacrificial material: and thinning the back surface of the substrate.

10. The method of manufacturing according to claim 1, wherein the method of bonding the cap substrate to the side of the base on which the dielectric layer is formed comprises:

11. The method of manufacturing of claim 1, further comprising, after removing the sacrificial layer:

forming a sealing material to fill the release hole.

12. A thin film bulk acoustic resonator, comprising:

a substrate;

a bottom cavity formed in the substrate;

a piezoelectric layer disposed on the lower electrode;

an upper electrode disposed on the piezoelectric layer;

the lower electrode, the piezoelectric layer and the upper electrode are all continuous

a top cavity penetrating the dielectric layer and exposing at least a portion of the upper electrode; a portion of the bottom cavity is exposed in the top cavity;

13. The film bulk acoustic resonator of claim 12, wherein the bottom cavity has a cross-sectional shape that is a polygon with any two sides parallel;

14. The film bulk acoustic resonator according to claim 12 or 13, wherein the top cavity and the bottom cavity overlap to form a common inner circumference, and a projection of the common inner circumference onto a plane of the piezoelectric layer is an irregular polygon, and the irregular polygon does not include any pair of opposite and parallel straight line segments.

15. The thin film bulk acoustic resonator of claim 12, further comprising:

the bonding ring is convexly arranged on the cap substrate;

16. The thin film bulk acoustic resonator of claim 12, further comprising: the first bonding pad and the second bonding pad are positioned on the surfaces of the substrates on two sides of the bottom cavity and positioned below the lower electrode, the lower electrode is electrically connected with the first bonding pad, and the upper electrode is electrically connected with the second bonding pad.

17. The film bulk acoustic resonator of claim 12, wherein the top of the bond ring includes a layer of bonding material.

18. The film bulk acoustic resonator of claim 12, wherein an interconnection structure is formed on the back surface of the substrate to electrically connect the lower electrode and the upper electrode, respectively.

19. The film bulk acoustic resonator of claim 12, further comprising an encapsulation material filling the release hole.

20. An electronic device, characterized in that the electronic device comprises a thin film bulk acoustic resonator according to any one of claims 12 to 19.