CN111446940B

CN111446940B - Stacked bulk acoustic wave resonator and method of manufacturing the same

Info

Publication number: CN111446940B
Application number: CN202010314204.8A
Authority: CN
Inventors: 吴明; 唐兆云; 杨清华; 赖志国; 王家友
Original assignee: Suzhou Huntersun Electronics Co Ltd
Current assignee: Suzhou Huntersun Electronics Co Ltd
Priority date: 2020-04-20
Filing date: 2020-04-20
Publication date: 2023-09-12
Anticipated expiration: 2040-04-20
Also published as: CN111446940A

Abstract

A stack type bulk acoustic wave resonator and a manufacturing method thereof, comprising a piezoelectric film array, wherein the piezoelectric film array comprises a plurality of piezoelectric films between a substrate and a cap layer, a plurality of first cavities are arranged between the piezoelectric films adjacent to each other in the vertical direction, between the piezoelectric films and the cap layer and between the piezoelectric films and the substrate, a second cavity is shared between the piezoelectric films adjacent to each other in the horizontal first direction, and a third cavity is shared between the piezoelectric films adjacent to each other in the horizontal second direction; a plurality of electrode layers covering at least the top and bottom surfaces of each piezoelectric film; a plurality of electrode interconnection layers connected to the electrode layer on the bottom surface of the piezoelectric film along the side surface of the third cavity; and the driving transistor is positioned in the cap layer, and the drain electrode of the driving transistor is electrically connected with the top electrode layer of the top piezoelectric film. According to the stacked BAW resonator and the manufacturing method thereof, the three-dimensional resonator with the plurality of cavities surrounding the piezoelectric film is manufactured by adopting a CMOS compatible process, and the plurality of chips are bonded together by utilizing the rewiring layer, so that the volume is reduced, the integration level is increased, and the cost is reduced.

Description

Stacked bulk acoustic wave resonator and method of manufacturing the same

Technical Field

The present application relates to a stacked Bulk Acoustic Wave (BAW) resonator and a method for manufacturing the same, and more particularly, to a stacked BAW resonator compatible with CMOS processes and a method for manufacturing the same.

Background

In wireless communication, a radio frequency filter is used as an intermediary for filtering signals with specific frequencies, and is used for reducing signal interference of different frequency bands, and the functions of image elimination, parasitic filtering, channel selection and the like are realized in a wireless transceiver. With the deployment of 4GLTE networks and the growth of markets, the design of the radio frequency front end is developed towards miniaturization, low power consumption and integration, and the requirements of the markets on filtering performance are also higher and higher. Because of the characteristics of small size, high operating frequency, low power consumption, high quality factor (Q value), direct output of frequency signals, compatibility with CMOS technology, etc., thin film bulk acoustic resonators (FBAR for short, also called "bulk acoustic wave", bulk acoustic wave for short, "BAW") have been widely used at present as important devices in the field of radio frequency communications.

FBARs are thin film devices of electrode-piezoelectric film-electrode sandwich structures fabricated on a substrate material. The FBAR has a cavity type, a bragg reflection type (SMR) type and a back etching type. The cavity type FBAR has high Q value relative to the SMR type FBAR, the loss is small, and the electromechanical coupling coefficient is high; the mechanical strength is high compared to the backside etching type FBAR without removing a large area of the substrate. Therefore, cavity FBARs are preferred for integration on CMOS devices.

However, due to the complexity of fabrication, existing BAW filters and Bulk Acoustic Resonators (BARs) are fabricated as devices in either independent planar or two-dimensional (2D) layouts. That is, BAW filters and Bulk Acoustic Resonators (BARs) are not provided as integrated structures with other CMOS, bicmos, siGe HBTs, and/or passive devices, resulting in higher manufacturing costs and increased manufacturing processes.

In addition, the 2D BAW resonator as an independent device has larger volume and area, lower integration level, is difficult to manufacture on the same chip with a driving circuit thereof by adopting a CMOS process, and is more difficult to integrate with 3D devices such as finfets, NAND memories and the like. However, if a plurality of 2D BAW resonators are stacked together using a 3D packaging technology, although the integration level can be effectively improved, each chip needs to use bonding, back grinding and thinning (bonding) and Through Silicon Vias (TSV) technologies to reduce the packaging height, and the process is complex and requires extremely high alignment accuracy, and the manufacturing cost is high. In addition, such a 3D package has problems of complicated wiring and large parasitic impedance.

Disclosure of Invention

It is therefore an object of the present application to provide a stacked BAW resonator and a method of manufacturing the same that overcomes the above technical hurdles.

The application provides a stacked Bulk Acoustic Wave (BAW) resonator comprising:

the piezoelectric film array comprises a plurality of piezoelectric films between a substrate and an upper cap layer of the chip, wherein a plurality of first cavities are arranged between the piezoelectric films adjacent to each other in the vertical direction, between the piezoelectric films and the cap layer and between the piezoelectric films and the substrate, a second cavity is shared between the piezoelectric films adjacent to each other in the horizontal first direction, and a third cavity is shared between the piezoelectric films adjacent to each other in the horizontal second direction;

a plurality of electrode layers covering at least the top and bottom surfaces of each piezoelectric film;

a plurality of electrode interconnection layers connected to the electrode layer on the bottom surface of the piezoelectric film along the side surface of the third cavity;

and the driving transistor is positioned in the cap layer, and the drain electrode of the driving transistor is electrically connected with the top electrode layer of the top piezoelectric film.

Wherein, optionally, the widths of the second cavities along the first direction are equal; optionally, the width of the bonding pad along the second direction is 1.5 times or more of the width of the third cavity.

Wherein, there are electrode layer, first isolating layer and electrode interconnection layer between third cavity that each first cavity and shares; optionally, an electrode layer and a second separator layer enclose each first cavity; optionally, the driving transistor further has an interlayer dielectric layer and a contact plug in the interlayer dielectric layer thereon, and further preferably, the interlayer dielectric layer has an intermetallic dielectric layer thereon and a rewiring layer thereon.

Wherein the substrate and/or capping layer material is selected from bulk Si, silicon-on-insulator (SOI), bulk Ge, geOI, gaN, gaAs, siC, inP, gaP, and preferably the substrate is the same as the capping layer material; optionally, the electrode layer and/or electrode interconnect layer material is a simple metal selected from Mo, W, ru, al, cu, ti, ta, in, zn, zr, fe, mg, alloys of these metals, conductive oxides or conductive nitrides of these metals, and any combination thereof; optionally, the piezoelectric film is ZnO, alN, BST, BT, PZT, PBLN, PT in material; optionally, the material of the first barrier layer and/or the second barrier layer is SiOx, siOC, siOC, siOF, siFC, BSG, PSG, PBSG or any combination thereof, and preferably the first barrier layer and the second barrier layer are the same material; optionally, the material of the bond pad is Al, mg, in, and combinations thereof.

The application also provides a stacked BAW resonator packaging structure comprising a first stacked resonator on a first wafer and a second stacked resonator on a second wafer, the first wafer being bonded opposite the second wafer, the first and second stacked resonators being stacked BAW resonators as claimed in any preceding claim.

The application further provides a method of manufacturing a stacked Bulk Acoustic Wave (BAW) resonator, comprising the steps of:

forming a plurality of sacrificial layers and a plurality of piezoelectric layers alternately stacked on a substrate;

forming a cap layer on the sacrificial layer on top, and forming a hard mask on the cap layer;

sequentially etching the layers until the substrate is exposed, and forming a plurality of first openings extending along a first direction;

forming a first isolation layer in each opening;

etching until the substrate is exposed, and forming a plurality of second openings extending along a second direction;

removing the plurality of sacrificial layers through the second opening, leaving a plurality of first cavities between adjacent piezoelectric layers, between the piezoelectric layers and the cap layer, and between the piezoelectric layers and the substrate;

forming a plurality of electrode layers at least on top and bottom surfaces of the piezoelectric layer through the second opening;

forming an electrode interconnection layer connecting the bottom electrode of the piezoelectric layer in the first opening;

a drive transistor is formed in the cap layer, wherein a drain of the drive transistor is electrically connected to a top electrode layer of the top piezoelectric layer.

Wherein an electrode layer, a first isolation layer, and an electrode interconnection layer are formed between each first cavity and the common third cavity; optionally, forming an electrode layer and a second isolation layer surrounding each first cavity; optionally, an interlayer dielectric layer and a contact plug in the interlayer dielectric layer are further formed on the driving transistor, and further preferably, an intermetallic dielectric layer and a rewiring layer are formed on the interlayer dielectric layer.

The substrate and/or capping layer material is selected from bulk Si, silicon-on-insulator (SOI), bulk Ge, geOI, gaN, gaAs, siC, inP, gaP, and preferably the substrate is the same as the capping layer material; optionally, the electrode layer and/or electrode interconnect layer material is a simple metal selected from Mo, W, ru, al, cu, ti, ta, in, zn, zr, fe, mg, alloys of these metals, conductive oxides or conductive nitrides of these metals, and any combination thereof; optionally, the piezoelectric film is ZnO, alN, BST, BT, PZT, PBLN, PT in material; optionally, the material of the first barrier layer and/or the second barrier layer is SiOx, siOC, siOC, siOF, siFC, BSG, PSG, PBSG or any combination thereof, and preferably the first barrier layer and the second barrier layer are the same material; optionally, the material of the bond pad is Al, mg, in, and combinations thereof.

The application further provides a manufacturing method of the packaging structure of the stacked BAW resonator, which comprises the following steps:

a method of manufacturing a stacked BAW resonator as claimed in any preceding claim, manufacturing a first stacked BAW resonator on a first wafer;

a method of manufacturing a stacked BAW resonator as claimed in any preceding claim, manufacturing a second stacked BAW resonator on a second wafer;

bonding the first and second wafers to each other;

preferably, the second substrate of the second wafer is further thinned after the first and second wafers are bonded;

preferably, the bonding pad and the passivation layer are further formed on the second substrate after the second substrate is thinned.

According to the stacked BAW resonator and the manufacturing method thereof, a three-dimensional resonator in which a plurality of cavities enclose a piezoelectric film is manufactured by adopting a CMOS compatible process, a driving circuit is formed in a top cap layer, and a plurality of chips are bonded together by utilizing a rewiring layer, so that the volume is reduced, the integration level is increased, and the cost is reduced.

The stated objects of the application, as well as other objects not listed herein, are met within the scope of the independent claims of the present application. Embodiments of the application are defined in the independent claims and specific features are defined in the dependent claims thereof.

Drawings

The technical solution of the present application is described in detail below with reference to the attached drawings, wherein:

FIG. 1A shows a plan view of a resonator manufacturing process according to an embodiment of the application, FIG. 1B shows a cross-sectional view along line B-B 'of FIG. 1A, and FIG. 1C shows a cross-sectional view along line A-A' of FIG. 1A;

fig. 2A shows a plan view of a resonator manufacturing process according to an embodiment of the present application, fig. 2B shows a cross-sectional view along a line B-B 'of fig. 2A, and fig. 2C shows a cross-sectional view along a line A-A' of fig. 2A;

fig. 3A shows a plan view of a resonator manufacturing process according to an embodiment of the present application, fig. 3B shows a cross-sectional view along a line B-B 'of fig. 3A, and fig. 3C shows a cross-sectional view along a line A-A' of fig. 3A;

fig. 4A shows a plan view of a resonator manufacturing process according to an embodiment of the present application, fig. 4B shows a cross-sectional view along a line B-B 'of fig. 4A, and fig. 4C shows a cross-sectional view along a line A-A' of fig. 4A;

fig. 5A shows a plan view of a resonator manufacturing process according to an embodiment of the present application, fig. 5B shows a cross-sectional view along a line B-B 'of fig. 5A, and fig. 5C shows a cross-sectional view along a line A-A' of fig. 5A;

fig. 6A shows a plan view of a resonator manufacturing process according to an embodiment of the present application, fig. 6B shows a cross-sectional view along a line B-B 'of fig. 6A, and fig. 6C shows a cross-sectional view along a line A-A' of fig. 6A;

fig. 7A shows a plan view of a resonator manufacturing process according to an embodiment of the present application, fig. 7B shows a cross-sectional view along a line B-B 'of fig. 7A, and fig. 7C shows a cross-sectional view along a line A-A' of fig. 7A;

fig. 8A shows a plan view of a resonator manufacturing process according to an embodiment of the present application, fig. 8B shows a cross-sectional view along line B-B 'of fig. 8A, and fig. 8C shows a cross-sectional view along line A-A' of fig. 8A;

fig. 9A shows a plan view of a resonator manufacturing process according to an embodiment of the present application, fig. 9B shows a cross-sectional view along a line B-B 'of fig. 9A, and fig. 9C shows a cross-sectional view along a line A-A' of fig. 9A;

fig. 10A shows a plan view of a resonator manufacturing process according to an embodiment of the present application, fig. 10B shows a cross-sectional view along a line B-B 'of fig. 10A, and fig. 10C shows a cross-sectional view along a line A-A' of fig. 10A;

FIG. 11A shows a plan view of a resonator manufacturing process according to an embodiment of the application, FIG. 11B shows a cross-sectional view along line B-B 'of FIG. 11A, and FIG. 11C shows a cross-sectional view along line A-A' of FIG. 11A;

fig. 12A shows a plan view of a resonator manufacturing process according to an embodiment of the application, fig. 12B shows a cross-sectional view along line B-B 'of fig. 12A, and fig. 12C shows a cross-sectional view along line A-A' of fig. 12A;

fig. 13A shows a plan view of a resonator manufacturing process according to an embodiment of the application, fig. 13B shows a cross-sectional view along line B-B 'of fig. 13A, and fig. 13C shows a cross-sectional view along line A-A' of fig. 13A;

fig. 14A shows a plan view of a resonator manufacturing process according to an embodiment of the application, fig. 14B shows a cross-sectional view along line B-B 'of fig. 14A, and fig. 14C shows a cross-sectional view along line A-A' of fig. 14A;

fig. 15A shows a plan view of a resonator manufacturing process according to an embodiment of the present application, fig. 15B shows a cross-sectional view along a line B-B 'of fig. 15A, and fig. 15C shows a cross-sectional view along a line A-A' of fig. 1A;

fig. 16A shows a plan view of a resonator manufacturing process according to an embodiment of the application, fig. 16B shows a cross-sectional view along line B-B 'of fig. 16A, and fig. 16C shows a cross-sectional view along line A-A' of fig. 16A;

FIG. 17A shows a plan view of a resonator manufacturing process according to an embodiment of the application, FIG. 17B shows a cross-sectional view along line B-B 'of FIG. 17A, and FIG. 17C shows a cross-sectional view along line A-A' of FIG. 17A;

fig. 18A shows a plan view of a resonator manufacturing process according to an embodiment of the application, fig. 18B shows a cross-sectional view along line B-B 'of fig. 18A, and fig. 18C shows a cross-sectional view along line A-A' of fig. 18A;

fig. 19A shows a plan view of a resonator manufacturing process according to an embodiment of the application, fig. 19B shows a cross-sectional view along line B-B 'of fig. 19A, and fig. 19C shows a cross-sectional view along line A-A' of fig. 19A;

FIG. 20A shows a plan view of a resonator manufacturing process according to an embodiment of the application, FIG. 20B shows a cross-sectional view along line B-B 'of FIG. 20A, and FIG. 20C shows a cross-sectional view along line A-A' of FIG. 20A;

fig. 21A shows a plan view of a resonator manufacturing process according to an embodiment of the application, fig. 21B shows a cross-sectional view along line B-B 'of fig. 21A, and fig. 21C shows a cross-sectional view along line A-A' of fig. 21A;

FIG. 22 shows a cross-sectional view along line B-B' of a resonator manufacturing process according to an embodiment of the application;

FIG. 23 shows a cross-sectional view along line B-B' of a resonator manufacturing process according to an embodiment of the application;

FIG. 24 shows a cross-sectional view along line B-B' of a resonator manufacturing process according to an embodiment of the application;

FIG. 25 shows a cross-sectional view along line B-B' of a resonator manufacturing process according to another embodiment of the application;

FIG. 26 shows a cross-sectional view along line B-B' of a resonator manufacturing process according to another embodiment of the application; and

fig. 27 shows a cross-sectional view along line B-B' of a resonator manufacturing process according to another embodiment of the application.

Detailed Description

Features of the technical solution of the present application and its technical effects are described in detail below with reference to the accompanying drawings in combination with exemplary embodiments, and a stacked BAW resonator and a method of manufacturing the same are disclosed. It should be noted that like reference numerals refer to like structures and that the terms "first," "second," "upper," "lower," and the like as used herein may be used to modify various device structures. These modifications, unless specifically stated, do not imply a spatial, sequential, or hierarchical relationship to the modified device structures.

As shown in fig. 1A to 1C, a stacked structure is formed on a substrate 10A, the stacked structure including at least one sacrifice layer 11A to 11B (actually, alternatively, the number is n+1, N is a natural number) and at least one piezoelectric layer 12A (the number may be N, N is a natural number) which are alternately stacked in this order from bottom to top, wherein the number of sacrifice layers is preferably one more than the number of piezoelectric layers. In the embodiment of the present application, only one piezoelectric layer 12A is shown, but other embodiments of the present application are not limited thereto and may form more piezoelectric layer stacks. The substrate 10A may be bulk Si or Silicon On Insulator (SOI) or bulk Ge, geOI to be compatible with CMOS processes and integrated with other digital and analog circuits, or may be a compound semiconductor for MEMS, optoelectronic devices, power devices, such as GaN, gaAs, siC, inP, gaP, or the like, or may be a transparent insulating material for glass, plastic, sapphire, or the like of a display panel. In a preferred embodiment of the present application, the substrate 10A is monocrystalline, such as bulk Si, to facilitate epitaxial growth of the stacked structure thereabove.

At least one sacrificial layer 11A-11B (the number is not limited to 2, but n+1, N is a natural number) and at least one piezoelectric layer 12A (the number is not limited to 1, but an arbitrary natural number N) are alternately stacked in sequence epitaxially grown on the substrate 10A by a conventional process such as PECVD, UHVCVD, HDPCVD, MOCVD, MBE, ALD. The sacrificial layer material may be a semiconductor material such as SiGe, siGeC, siGeSn, siGaN, siGaP, siGaAs, inSiN, inSiP, inSiAs, inSiSb, siInGaAs, or a non-semiconductor material such as amorphous carbon or graphene oxide. Examples of the piezoelectric layer material include ceramic materials such as ZnO, alN, BST (barium strontium titanate), BT (barium titanate), PZT (lead zirconate titanate), PBLN (lead barium lithium niobate), and PT (lead titanate). Preferably, the number of sacrificial layers is one more than the number of piezoelectric layers. Further preferably, the stacked structure further includes a cap layer 10B formed on the top sacrificial layer 11D, and the cap layer is preferably made of the same material as the substrate 10A, so as to serve as an upper cover plate of the topmost resonant cavity in a subsequent process.

As shown in fig. 2A-2C, a hard mask layer 13 is formed on top of the stack to protect the stack, and in particular, the cap layer 10B on top of the stack, in a subsequent process. The hard mask layer 13 is deposited using a process such as LPCVD, PECVD, HDPCVD, for example SiN, siON, siNC, siNF. Next, a photoresist pattern 14 is formed on top of the hard mask layer 13. The photoresist pattern 14 is formed by spin coating, spray coating, screen printing, etc. and is exposed and developed, wherein the photoresist pattern is extended in a first direction, i.e., A-A ', while an opening extending in the first direction is left between adjacent photoresist patterns (in a second direction, i.e., B-B') to expose the hard mask layer 13.

As shown in fig. 3A to 3C, the stack of the hard mask layer 13, the cap layer 10B, the sacrificial layer 11 and the piezoelectric film 12 is sequentially etched using the photoresist pattern 14 as a mask, stopping on the substrate 10A, and forming a plurality of first openings 14A penetrating vertically through the above layers until the substrate 10A is exposed. The etching process is preferably an anisotropic dry etching process, such as plasma dry etching or reactive ion etching using a fluorocarbon-based etching gas. Since the substrate 10A is a semiconductor material such as Si and does not contain an element normally contained in an insulating material such as C, N, O, the stop time can be determined by observing a change in the wavelength spectrum of the atmosphere in the etching chamber. For example, when the plasma glow signal intensity corresponding to CN and/or NO groups is monitored to decrease below 1%, particularly below 0.2%, of the peak value and persists for 10 to 500 microseconds, it is determined that etching has reached the top of the substrate 10A.

As shown in fig. 4A to 4C, the width of the top of the first opening 14A is enlarged such that the width of the second portion 13A of the top of the first opening in the direction B-B' is larger than the width of the first portion 14A below, the second portion 13A exposing a portion of the top of the piezoelectric layer 12A. A second photoresist pattern having a smaller size is formed, or a shrink process (shrnk) is performed on the photoresist pattern 14 to reduce the size of the photoresist pattern, and the cap layer 10B and the sacrificial layer 11B are etched using the smaller size photoresist pattern as a mask until the piezoelectric layer 12A is exposed. The photoresist pattern 14 is then removed to expose the hard mask layer 13, preferably by a wet process, to remove the organic photoresist with an acid and/or an oxidizing agent, thereby leaving a plurality of T-shaped first openings of narrower first portions 14A distributed along the first direction A-A' and wider second portions 13A thereabove. Preferably, HF-based corrosive liquids such as dHF, dBOE and the like are adopted to remove native oxides on the surfaces of all layers in a wet way so as to improve the subsequent film growth quality.

As shown in fig. 5A-5C, an isolation layer 15 is formed over the entire device. Preferably, the isolation layer 15 is formed by using HDPCVD, MBE, ALD, in-situ vapor doping thermal oxidation/nitridation, or other processes with better conformality, and the isolation layer is made of an insulating dielectric material different from the hard mask 13, for example SiOx, siOC, siOC, siOF, siFC, BSG, PSG, PBSG. The isolation layer 15 uniformly covers the first portion 14A, the second portion 13A, and the top of the hard mask 13, particularly the sidewalls of the sacrificial layer 11 and the piezoelectric layer 12 exposed in the first portion 14A, the second portion 13A. The isolation layer 15 will later act as an insulating isolation material between the individual sub-resonators of the stacked BAW and as a temporary mechanical support structure in the subsequent process. Preferably, the thickness of the spacer 15 is between 1 and 50nm and preferably between 10 and 25nm, too thin a spacer cannot provide adequate mechanical support and too thick a spacer tends to prematurely fill the bottom of the first portion 14A. Preferably, the spacer layer 15 has a thickness twice less than 1/4 and preferably less than 1/8, but greater than or equal to 1/10 of the width of the first portion 14A of the first opening.

As shown in fig. 6A-6C, a photoresist layer 16 is formed over the entire device using spin coating, spray coating, screen printing, etc., completely filling the first portion 14A and the second portion 13A of the first opening.

As shown in fig. 7A-7C, the photoresist layer 16 is patterned using an exposure and development process, leaving a plurality of second openings 16A extending in a second direction B-B' to expose the underlying isolation layer 15. Preferably, the second opening 16A is not continuous in the second direction but is further divided into a plurality of sub-portions so as to leave the underlying discontinuous isolation layer pattern 15, so as to avoid a partial collapse caused by a complete fracture of the isolation layer 15 in the first direction A-A' during a subsequent sacrificial layer removal process. It is further preferable to select the wavelength and dose of the exposure development such that the corners of the opening 16A are rounded to reduce the degree of stress concentration at right angles to the rectangle, ensuring good mechanical support properties of the spacer layer 15.

As shown in fig. 8A to 8C, the stack of the isolation layer 15, the hard mask layer 13, the cap layer 10B, the sacrificial layer 11 and the piezoelectric layer 12 is etched down in this order, stopping on the substrate 10A, using the photoresist pattern 16 as a mask, by an anisotropic dry etching process, for example, a plasma dry etching or a reactive ion etching using a fluorocarbon-based etching gas. I.e., the plurality of openings 16A are increased in depth until the substrate 10A is exposed. The etching process further preferably selects a relatively fluorocarbon gas such as CFH ₃ 、C ₂ F ₃ H ₃ 、CF ₂ H ₂ And the like, so that elements such as C, si, N and the like form a temporary protection layer on the side wall in the etching process to inhibit lateral corrosion, and the side wall of the second opening 16A is ensured to have enough verticality.

As shown in fig. 9A-9C, the photoresist pattern 16 is removed. The photoresist of the organic material therein is preferably removed using a dry ashing process to avoid excessive etching of the underlying isolation layer 15 by the wet etching solution. More preferably, the surface of the spacer 15 is cleaned with an HF-based etchant such as dHF or dBOE.

As shown in fig. 10A to 10C, the sacrificial layer 11 is isotropically selectively etched away, leaving a plurality of piezoelectric layer patterns 12 (not limited to 12A shown in the drawings) supported by the spacer layer 15 on the substrate, and a plurality of recesses 15A in the horizontal direction are provided between adjacent piezoelectric layer patterns, between the top piezoelectric layer and the cap layer 10B, and between the bottom piezoelectric layer and the substrate 10A, in addition to the T-shaped first openings in the vertical direction. In a preferred embodiment of the present application, the substrate 10A, the cap layer 10B is Si, the sacrificial layer 11 is SiGe, and wet etching is performed with a combination of strong oxidizer, strong inorganic acid and weak organic acid to increase the etching selectivity of SiGe to Si. Wherein the strong oxidant is nitric acid, hydrogen peroxide, ozone and perchloric acid, the strong inorganic acid is hydrofluoric acid, hydrochloric acid and sulfuric acid, the weak organic acid is acetic acid and oxalic acid, for example, the strong oxidant is 30-50 parts, the strong inorganic acid is 0.5-2 parts, the weak organic acid is 1-4 parts, and the solvent water is 40-70 parts (all by volume ratio). For single crystal Si, for example _0.8 Ge _0.2 And Si, HNO of 40:1:2:57 can be used ₃ (70％):HF(49％):CH ₃ COOH(99.9％):H ₂ O, thereby achieving a 300:1 selection ratio. In another embodiment of the present application, the sacrificial layer 11 is amorphous carbon (e.g., ta-C), graphene oxide, graphene or other C-based material, and oxygen plasma dry etching or thermal oxidation may be selected so that the sacrificial layer reacts with oxygen to form a gas that is extracted, and oxygen will form a thin oxide layer on the surface of the piezoelectric layer 12, and the thin oxide layer needs to be removed by using an etchant such as dHF, dBOE or the like.

As shown in fig. 11A to 11C, a metal layer 17 is formed on the entire device using a deposition process such as ALD, MBE, MOCVD which has good conformality and serves as a contact electrode for the piezoelectric layer 12. The metal layer 17 is made of a metal simple substance such as Mo, W, ru, al, cu, ti, ta, in, zn, zr, fe, mg or a metal alloy, or a conductive oxide, a conductive nitride of these metals, or any combination of the above materials, that is, includes a seed layer or a barrier layer and a conductive layer. As shown in fig. 11C, in the cross-sectional view, the metal layer 17 not only surrounds the piezoelectric layer 12 (at least three sides, preferably four sides), but is also deposited on the substrate 10A, the cap layer 10B to serve as a contact layer for the bottom surface and the top surface.

As shown in fig. 12A-12C, photoresist is spin-coated and exposed to light and developed to form photoresist patterns 18 extending in the second direction B-B 'at a pitch along the first direction A-A' equal to the original width of the second openings 16A, i.e., the sidewalls of the photoresist patterns 18 are vertically flush with the sidewalls of the piezoelectric layer 12.

As shown in fig. 13A to 13C, each layer is sequentially anisotropically dry etched using the photoresist pattern 18 as a mask until the substrate 10A is exposed, thereby removing the vertical portion of the metal layer 17 while leaving only the horizontal portion, that is, only the bottom of the cap layer 10B, the top and bottom of the piezoelectric layer 12, and the top of the substrate 10A as contact electrode layers.

As shown in fig. 14A-14C, the photoresist pattern 18 is removed, exposing the electrode layer 17 in the first opening and on top of the isolation layer 15. As shown in fig. 14B, electrode layer 17 wraps around recess 15A and directly contacts the top and bottom of piezoelectric layer 12, and will be used as top and bottom electrodes in the future.

As shown in fig. 15A-15C, the second isolation layer 19 is formed by using a process with better conformality, such as HDPCVD, MBE, ALD, in-situ vapor doping thermal oxidation/nitridation, etc., and the material of the second isolation layer may be the same as that of the (first) isolation layer 15, for example SiOx, siOC, siOC, siOF, siFC, BSG, PSG, PBS. The second isolation layer 19 is mainly used for insulating and isolating the piezoelectric layer from the cap layer and the substrate in the vertical direction.

As shown in fig. 16A-16C, the photoresist is coated and exposed to light and developed to form photoresist patterns 20 extending in a first direction A-A ', and the spacing between the photoresist patterns 20 in a second direction B-B' is preferably equal to the original width of the lower first portion 14A of the first opening, i.e., the sidewalls of the photoresist patterns 20 are vertically flush with the sidewalls of the piezoelectric layer 12A.

As shown in fig. 17A-17C, each film layer is anisotropically dry etched using the photoresist pattern 20 as a mask until the substrate 10A is exposed, re-exposing the first portion 14A of the first opening. In this process, the first isolation layer 15 of insulating material will remain on the side walls of the second portion 13A due to the larger width of the first open second portion 13A, i.e. the isolation layer 15 side walls are flush with the piezoelectric layer 12A as shown in fig. 17B. The remaining isolation layer 15 will serve to isolate the top and bottom electrode leads of the piezoelectric layer 12A in the horizontal direction.

As shown in fig. 18A-18C, a dry ashing process is used to remove the photoresist pattern 20.

As shown in fig. 19A to 19C, the metal layer 21 is formed on the entire device using a deposition process with good conformality such as ALD, MBE, MOCVD, and serves as a bottom electrode lead of the piezoelectric layer 12. The metal layer 21 is made of a metal simple substance such as Mo, W, ru, al, cu, ti, ta, in, zn, zr, fe, mg or a metal alloy, or a conductive oxide, a conductive nitride of these metals, or any combination of the above materials, that is, includes a seed layer or a barrier layer and a conductive layer. As shown in fig. 19B, the first insulating layer 15 actually insulates the piezoelectric layer top and bottom electrodes, because the metal layer 21 can only contact the metal layer 17 surrounding the cavity portion at the bottom of the piezoelectric layer 12A, but cannot contact the metal layer 17 above.

As shown in fig. 20A-20C, the fill layer 16 is planarized using a CMP or etch back process or the like until the hard mask layer 13 is exposed.

As shown in fig. 21A-21C, the hard mask 13 is removed. The removal process may be CMP planarization or wet etching. In the CMP process, an oxidizing agent such as hydrogen peroxide, ozone or nitric acid may be added into the polishing solution to accelerate the CMP speed, and at the same time, an ultra-thin silicon oxide layer is formed on top of the cap layer 10B in situ, and is used as a liner layer or a gate dielectric interface layer in a subsequent process.

As shown in fig. 22, the driving transistor 22 is formed in the cap layer 10B. Specifically, for example, the first opening is masked with photoresist (not shown) to expose only the active region of the cap layer 10B, a gate stack 22G of a gate dielectric layer and a gate conductive layer is formed in the active region, and the source region 22S and the drain region 22D are formed by ion-doping implantation using the gate stack 22G as a mask. In particular, after the source region 22S and the drain region 22D are formed by simultaneous implantation, only the drain region is exposed by masking the source region with a photoresist pattern, and the ion implantation depth is increased to make the doped region 22D directly contact the metal layer 17 surrounding the recess 15A, so that the doped region is finally electrically contacted with the top of the piezoelectric layer 12A along the sidewall of the recess 15A, in other words, the drain electrode of the driving transistor 22 is electrically connected with the piezoelectric film 12A, so that the path length of the electrical path between the driving transistor and the piezoelectric layer can be shortened inside the wafer, the series resistance can be reduced, the driving capability can be improved, the integration level can be improved, and the packaging cost can be reduced.

As shown in fig. 23, an interlayer dielectric layer 23 is formed on the driving transistor 22, and a contact plug 24 is formed in the interlayer dielectric layer (ILD) 23. ILD layer 23 of low-k material is formed using spin-on, spray-on, screen-printing, etc., processes wherein the low-k material includes, but is not limited to, organic low-k materials (e.g., aryl or multi-ring containing organic polymers), inorganic low-k materials (e.g., amorphous carbon nitrogen films, polycrystalline boron nitrogen films, fluorosilicate glasses, BSG, PSG, BPSG), porous low-k materials (e.g., disilyltrioxane (SSQ) -based porous low-k materials, porous silica, porous SiOCH, C-doped silica, F-doped porous amorphous carbon, porous diamond, porous organic polymers). The ILD layer is etched to form vias exposing the bottom electrode lead-out 21, the gate/source/drain regions of the drive transistor 22 and a metal material is deposited to form contact plugs 24.

As shown in fig. 24, preferably, an inter-metal dielectric layer (MID) 25 is further formed on the ILD layer 23, and a Rewiring (RDL) layer 26 is formed in the MID 25 for rearranging the distribution positions of the contact plugs 24 to flexibly adjust the layout of external electrical contacts. MID 25 may be a low-k material with ILD 23, and RDL layer 26 may be the same material as contact plug 24. In a preferred embodiment of the present application, after ILD 23 and MID 25 are formed sequentially, a damascene process is used to form contact plug 24 and RDL layer 26.

Thus, with reference to fig. 1A-24, a process for fabricating a stacked BAW resonator according to one embodiment of the present application has been fully described, the resulting stacked BAW resonator on a first wafer comprising: a substrate 10A and a cap layer 10B, an array of at least one piezoelectric film 12A between the substrate 10A and the cap layer 10B (distributed in the first and second directions A-A 'and B-B' intersecting) including first cavities 15A between the top piezoelectric film 12A and the cap layer 10B, between the bottom piezoelectric film 12A and the substrate 10A, and between vertically adjacent piezoelectric films 12, including second cavities 16A (second openings) between adjacent piezoelectric films 12A in the first direction A-A 'on a horizontal plane and third cavities (first openings 14A/13A) in the second direction B-B', a metal layer 17 surrounding each first cavity 15A to serve as top and bottom electrodes of the piezoelectric layer 12A, bottom electrode lead-out lines 21 distributed on the sidewalls of the third cavities, first isolation layers 15 between the bottom electrode 21 and the top electrodes 17 of the piezoelectric layer 12A, wherein the cap layer 10B has a drive transistor 22 therein, and the drain regions 22D of the drive transistor 22 electrically connect the top electrodes of the piezoelectric layer 12A. The cap layer 10B further has an ILD layer 23 and a contact plug 24 therein, and further has an MID layer 25 and an RDL layer 26 therein.

Referring to fig. 25-27, a process for preparing a dual chip stacked BAW resonator in accordance with another embodiment of the present application is described.

The aforementioned stacked BAW resonators are formed on the first chip (wafer) and the second chip (wafer) on the basis of fig. 1A-24, respectively. Then, referring to fig. 25, the first wafer and the second wafer are bonded together using an RDL layer, forming a stacked structure in which the first wafer is mounted upside down and the second wafer is flipped upside down.

As shown in fig. 26, the substrate 10A' of the second wafer is thinned, for example, using a CMP process or etch back, in order to reduce the height and contact resistance of the subsequent package interconnections.

As shown in fig. 27, a contact pad 27 and a passivation layer 28 are formed. For example, the thinned substrate 10A' is etched until the bottom electrode lead 21 is exposed, and the bonding pad 27 is formed by deposition and plating. The width of the pad pattern along the second direction B-B' is 1.5 times or more, preferably 2 times or more, the width of the cavity (third cavity) formed by the remainder of the first opening 14, and sufficient electrical connection with the lower Fang Xiezhen device array can be ensured even if the upper layer structure is misaligned during patterning. A passivation layer 28 of silicon oxide, silicon nitride or other organic resin is formed on the remainder of the substrate 10A' of the second wafer for insulating isolation protection or as a build-up layer for future soldering. Preferably, the surface of the passivation layer 28 is treated, such as plasma annealing or laser annealing in oxygen and/or nitrogen atmosphere, to enhance the bonding strength between the passivation layer 28 and the bonding pad 27 and between future structures, and the surface treatment also repairs the surface damage of the electrode and the electrode interconnection layer on both sides of the piezoelectric film in the respective etching deposition process steps, which is beneficial to reducing the series resistance and parasitic capacitance. In particular, a planarization process is performed on the passivation layer 28 to expose the pad patterns 27. Thereafter, it is further preferable that a conductive bump (not shown) is formed over the pad pattern 27 to electrically connect to the outside.

While the application has been described with reference to one or more exemplary embodiments, it will be understood by those skilled in the art that various suitable changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the application. In addition, many modifications may be made to adapt a particular situation or material to the teachings disclosed without departing from the scope of the application. Therefore, it is intended that the application not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this application, but that the device structure and method of making the same will include all embodiments falling within the scope of the present application.

Claims

1. A stacked Bulk Acoustic Wave (BAW) resonator, comprising:

a driving transistor in the cap layer, a drain electrode of the driving transistor being electrically connected to the top electrode layer of the top piezoelectric film;

wherein, each first cavity and the shared third cavity are provided with an electrode layer, a first isolation layer and an electrode interconnection layer.

2. A stacked BAW resonator as claimed in claim 1, wherein, optionally, the widths of the second cavities in the first direction are equal; optionally, the width of the bonding pad along the second direction is 1.5 times or more of the width of the third cavity.

3. The stacked BAW resonator of claim 1, wherein the electrode layer and the second isolation layer enclose each first cavity; the driving transistor further has an interlayer dielectric layer and a contact plug in the interlayer dielectric layer, and the interlayer dielectric layer has an intermetallic dielectric layer and a rewiring layer thereon.

4. A stacked BAW resonator as claimed in claim 1, wherein the substrate and/or capping layer material is selected from bulk Si, silicon-on-insulator (SOI), bulk Ge, geOI, gaN, gaAs, siC, inP, gaP.

5. The stacked BAW resonator of claim 4, wherein the substrate is the same as the cap material.

6. A stacked BAW resonator according to claim 1, wherein the electrode layer and/or the electrode interconnect layer material is a simple metal selected from Mo, W, ru, al, cu, ti, ta, in, zn, zr, fe, mg, an alloy of these metals, a conductive oxide or a conductive nitride of these metals, and any combination thereof.

7. The stacked BAW resonator of claim 1, wherein the piezoelectric film is of a material ZnO, alN, BST, BT, PZT, PBLN, PT.

8. The stacked BAW resonator of claim 1, wherein optionally the material of the first isolation layer is SiOx, siOC, siOC, siOF, siFC, BSG, PSG, PBSG or any combination thereof.

9. The stacked BAW resonator of claim 4, wherein the material of the second isolation layer is SiOx, siOC, siOC, siOF, siFC, BSG, PSG, PBSG or any combination thereof.

10. The stacked BAW resonator of claim 9, wherein the first isolation layer and the second isolation layer are the same material.

11. The stacked BAW resonator of claim 2, wherein the material of the bond pad is Al, mg, in, and combinations thereof.

12. A stacked BAW resonator package comprising a first stacked resonator on a first die and a second stacked resonator on a second die, the first die being bonded opposite the second die, the first and second stacked resonators being stacked BAW resonators as claimed in any one of claims 1 to 11.

13. A method of fabricating a stacked Bulk Acoustic Wave (BAW) resonator, comprising the steps of:

sequentially etching each layer until the substrate is exposed, and forming a plurality of first openings extending along a first direction;

forming a first isolation layer in each opening;

14. The method of fabricating a stacked BAW resonator of claim 13, wherein the widths of the second cavities in the first direction are equal.

15. The method for manufacturing a stacked BAW resonator of claim 13, wherein the width of the bonding pad in the second direction is 1.5 times or more the width of the third cavity.

16. The method of manufacturing a stacked BAW resonator of claim 13, wherein an electrode layer, a first isolation layer, and an electrode interconnect layer are formed between each first cavity and the common third cavity.

17. The method of fabricating a stacked BAW resonator of claim 13, wherein the electrode layer and the second isolation layer are formed to surround each of the first cavities.

18. The method of fabricating a stacked BAW resonator of claim 13, wherein the drive transistor is further formed with an interlayer dielectric layer and a contact plug in the interlayer dielectric layer.

19. The method of fabricating a stacked BAW resonator of claim 18 wherein an inter-metal dielectric layer and a rewiring layer are formed over the interlayer dielectric layer.

20. A method of fabricating a stacked BAW resonator as claimed in claim 13, the substrate and/or capping layer material being selected from bulk Si, silicon-on-insulator (SOI), bulk Ge, geOI, gaN, gaAs, siC, inP, gaP.

21. The method of fabricating a stacked BAW resonator of claim 20 wherein the substrate is the same as the cap layer material.

22. A method of fabricating a stacked BAW resonator in accordance with claim 13, wherein the electrode layer and/or the electrode interconnect layer material is a metal element selected from the group consisting of Mo, W, ru, al, cu, ti, ta, in, zn, zr, fe, mg, alloys of these metals, conductive oxides or conductive nitrides of these metals, and any combination thereof.

23. The method of fabricating a stacked BAW resonator of claim 13, wherein the piezoelectric film is of a material ZnO, alN, BST, BT, PZT, PBLN, PT.

24. The method of fabricating a stacked BAW resonator of claim 16, wherein the material of the first isolation layer is SiOx, siOC, siOC, siOF, siFC, BSG, PSG, PBSG or any combination thereof.

25. The method of fabricating a stacked BAW resonator of claim 17, wherein the material of the second isolation layer is SiOx, siOC, siOC, siOF, siFC, BSG, PSG, PBSG or any combination thereof.

26. The method of fabricating a stacked BAW resonator of claim 25, wherein the first isolation layer and the second isolation layer are the same material.

27. The method of fabricating a stacked BAW resonator of claim 15, wherein the material of the bond pad is Al, mg, in, and combinations thereof.

28. A method of fabricating a package structure for a stacked BAW resonator, comprising:

a method of manufacturing a stacked BAW resonator as claimed in any one of claims 13 to 27, manufacturing a first stacked BAW resonator on a first wafer;

a method of manufacturing a stacked BAW resonator as claimed in any one of claims 13 to 27, manufacturing a second stacked BAW resonator on a second wafer;

the first and second wafers are bonded to each other.

29. The method of fabricating a stacked BAW resonator package in accordance with claim 28, further thinning the second substrate of the second wafer after bonding the first and second wafers.

30. The method of fabricating a stacked BAW resonator package in accordance with claim 29, further forming a bond pad and passivation layer on the second substrate after thinning the second substrate.