CN113035880B

CN113035880B - Memory and preparation method thereof

Info

Publication number: CN113035880B
Application number: CN202110255006.3A
Authority: CN
Inventors: 姚兰
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-03-09
Filing date: 2021-03-09
Publication date: 2021-10-08
Anticipated expiration: 2041-03-09
Also published as: CN113035880A

Abstract

A method of fabricating a three-dimensional memory and a three-dimensional memory are disclosed. The disclosed method for preparing a three-dimensional memory comprises the following steps: forming a first laminated structure on one side surface of the semiconductor structure, and forming a contact hole penetrating through the first laminated structure in the first laminated structure; disposing a first filler in the contact hole to form a contact block; forming a second laminated structure on the surface of one side of the first laminated structure, which is far away from the semiconductor structure, and forming a through second laminated structure connecting opening in the second laminated structure; and disposing a second filler in the connection opening to form a connection layer. Wherein a side surface of the contact block adjacent to the semiconductor structure is in direct contact with the semiconductor structure, and a side surface of the contact block remote from the semiconductor structure is completely exposed in the connection opening and is in direct contact with a connection layer disposed in the connection opening. Wherein the contact block and the connection layer are formed to have a cross-sectional shape gradually decreasing in size in a direction away from the semiconductor structure.

Description

Memory and preparation method thereof

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a memory and a method for manufacturing the same.

Background

The memory with the X-stacking structure can effectively solve the problem that the peripheral circuit is influenced by high temperature and high pressure when the memory array is processed by arranging the memory array and the peripheral circuit on the array wafer and the peripheral wafer respectively, and can realize higher memory density, simpler process flow and shorter cycle time.

Under the X-stacking architecture, as the number of stacked layers of the memory array increases, the requirement for peripheral circuits also increases. For example, more interface circuits, driving circuits, etc. may be required in the peripheral circuits. In this case, the back-end-of-line interconnect structure (hereinafter simply referred to as interconnect structure) in the peripheral circuit also becomes more complicated. In particular, there will be more and more metal lines, i.e. more and more metal layers, for the interconnections between the transistors.

During the process of preparing the peripheral wafer, processes such as ion implantation and ion etching may generate free charges. In this case, the conductors such as metal wires in the chip can collect the free charges like an antenna, and the longer the antenna is, the more charges are collected and the higher the voltage is. When this conductor is connected to the gate of the MOS transistor, the high voltage may cause the thin gate oxide to break down, causing the circuit to fail, the so-called "antenna effect". In general, the "antenna ratio" can be used to measure the probability of antenna effect on a chip. The definition of "antenna ratio" is: the ratio of the cross-sectional area of the conductor (typically a metal) making up the "antenna" to the area of the gate oxide layer to which it is connected.

As described above, as the number of metal layers for MOS transistor interconnection in the peripheral wafer increases, the antenna ratio increases, and the probability of the antenna effect increases. Therefore, the gate oxide layer in the peripheral wafer is also more easily damaged.

On the other hand, in an array wafer adopting a 3D memory architecture, for example, 32, 64, 128 or more memory cells may be stacked in a direction perpendicular to the surface of the array wafer, and the area of the gate oxide layer may be increased by 32 times, 64 times, 128 times or more, respectively. That is, the antenna ratio may also be reduced by a corresponding factor.

An inverted X-stacking architecture with interconnect structures for the peripheral wafer disposed on the array wafer may be formed to address antenna effects in the peripheral wafer. In the inverted X-stacking architecture, as described above, since the antenna ratio can be reduced by 32 times, 64 times, 128 times or more, the possibility of damage to the gate oxide layer is greatly reduced or even negligible.

In the inverted X-stacking architecture, the integration level also needs to be higher as the interconnect structure for the peripheral wafer is closer to the peripheral circuitry in a direction away from the array wafer substrate. However, according to the conventional process, the requirement of improving the integration level of the inverted X-stacking structure cannot be satisfied.

The above information disclosed in this background section is only for background understanding of the inventive concept and, therefore, it may contain information that does not constitute prior art.

Disclosure of Invention

The present application provides a three-dimensional memory and a method for fabricating the same that can at least partially solve the above-mentioned problems in the prior art, so as to satisfy the requirement of an interconnect structure for forming a peripheral wafer on an array wafer under an inverted X-stacking architecture.

One aspect of the present disclosure provides a method of fabricating a three-dimensional memory, which may include: forming a first laminated structure on one side surface of the semiconductor structure, and forming a contact block penetrating through the first laminated structure in the first laminated structure; and forming a second laminated structure on the surface of the side, far away from the semiconductor structure, of the first laminated structure, and forming a connecting layer penetrating through the second laminated structure in the second laminated structure. Wherein the contact block is in direct contact with the connection layer. Wherein the contact block and the connection layer each have a cross-sectional shape with a decreasing size in a direction away from the semiconductor structure, the connection layer having a size larger than the contact block at a contact interface of the contact block and the connection layer.

In an embodiment according to the present disclosure, the semiconductor structure may include a substrate layer, a memory array disposed on one side surface of the substrate layer, and an interconnect structure disposed on the memory array, and forming the first stacked structure on one side surface of the semiconductor structure may include: a first stack is formed on a surface of the interconnect structure remote from the substrate layer.

In an embodiment according to the present disclosure, a side surface of the contact block adjacent to the semiconductor structure may be in direct contact with the interconnect structure such that the interconnect structure is electrically connected to the peripheral circuitry in the peripheral wafer through the contact block and the connection layer.

In an embodiment according to the present disclosure, the interconnect structure includes a plurality of connection portions, at least one of the connection portions is in direct contact with at least two contact blocks formed in the first stacked structure, and each of the at least two contact blocks is formed to be in direct contact with a corresponding one of the connection layers, respectively.

In an embodiment according to the present disclosure, the first stacked structure may include a first sacrificial layer, wherein forming the contact block in the first stacked structure may include: patterning the first sacrificial layer to obtain first interval patterns and contact hole sacrificial blocks arranged at intervals through the first interval patterns, wherein the contact hole sacrificial blocks have cross-sectional shapes with gradually reduced sizes in the direction far away from the semiconductor structure; arranging a third filler in the first interval pattern to form a third dielectric layer; removing the contact hole sacrificial block to obtain a first contact hole part; and filling a conductive material in the first contact hole portion to form a contact block.

In an embodiment according to the present disclosure, the first stacked structure may further include a first dielectric layer and a second dielectric layer sequentially formed between the interconnect structure and the first sacrificial layer, and the forming of the contact block in the first stacked structure may further include: after forming the first contact hole portion in the first sacrificial layer, removing a portion of the second dielectric layer exposed in the first contact hole portion to obtain a second contact hole portion; removing the part of the first dielectric layer exposed in the second contact hole part to obtain a third contact hole part; and filling a conductive material in a contact hole formed by the first contact hole part, the second contact hole part and the third contact hole part together to form a contact block.

In an embodiment according to the present disclosure, the second stacked structure may include a second sacrificial layer, wherein forming the connection layer in the second stacked structure may include: patterning the second sacrificial layer to obtain second interval patterns and connection sacrificial layers arranged at intervals through the second interval patterns, wherein the connection sacrificial blocks have cross-sectional shapes with gradually reduced sizes in the direction away from the semiconductor structure; arranging a fourth filler in the second interval pattern to form a sixth dielectric layer; removing the connection sacrificial layer to obtain a first connection opening portion; and filling a conductive material in the first connection opening portion to form a connection layer.

In an embodiment according to the present disclosure, the second stacked structure may further include a fourth dielectric layer and a fifth dielectric layer sequentially formed between the first stacked structure and the second sacrificial layer, and the forming of the connection layer in the second stacked structure may further include: after forming a first connection opening portion in the second sacrificial layer, removing a portion of the fifth dielectric layer exposed in the first connection opening portion to obtain a second connection opening portion; removing a portion of the fourth dielectric layer exposed in the second connection opening portion to obtain a third connection opening portion; and filling a conductive material in a connection opening formed by the first connection opening part, the second connection opening part and the third connection opening part together to form a connection layer.

In an embodiment according to the present disclosure, a third stacked structure is formed on a surface of a side of the second stacked structure away from the semiconductor structure, and a first sub-contact block and a second sub-contact block penetrating the third stacked structure are formed in the third stacked structure; and forming a fourth laminated structure on a surface of the third laminated structure far away from the semiconductor structure, and forming a first sub-connection layer and a second sub-connection layer penetrating through the fourth laminated structure in the fourth laminated structure. Wherein the first sub-contact block and the second sub-contact block are in direct contact with the first sub-connection layer and the second sub-connection layer, respectively, the first sub-contact block and the first sub-connection layer are formed to have cross-sectional shapes that decrease in size in a direction away from the semiconductor structure, respectively, and the size of the first sub-connection layer is greater than the size of the first sub-contact block at a contact interface of the first sub-contact block and the first sub-connection layer.

In an embodiment according to the present disclosure, one of the first sub-contact blocks and one of the second sub-contact blocks are formed to be in direct contact with one of the connection layers.

Another aspect of the present disclosure provides a three-dimensional memory, which may include: a first stacked structure disposed on one side surface of the semiconductor structure, the first stacked structure having a contact block penetrating the first stacked structure therein; and a second laminated structure arranged on the surface of one side of the first laminated structure far away from the semiconductor structure, wherein the second laminated structure is provided with a connecting layer penetrating through the second laminated structure. Wherein the contact block is in direct contact with the connection layer, the contact block and the connection layer have cross-sectional shapes with sizes decreasing in a direction away from the semiconductor structure, respectively, and the size of the connection layer is larger than that of the contact block at a contact interface of the contact block and the connection layer.

In an embodiment according to the present disclosure, the semiconductor structure may include a substrate layer, a memory array disposed on a side surface of the substrate layer, and an interconnect structure disposed on the memory array, and the first stacked structure is formed on a surface of the back-end-of-line interconnect structure away from the substrate layer.

In an embodiment according to the present disclosure, the interconnect structure includes a plurality of connection portions, at least one of the plurality of connection portions is in direct contact with at least two contact blocks formed in the first stacked structure, and each of the at least two contact blocks is in direct contact with a corresponding one of the connection layers, respectively.

In an embodiment according to the present disclosure, the three-dimensional memory may further include: a third laminated structure arranged on one side surface of the second laminated structure far away from the semiconductor structure, wherein the third laminated structure is provided with a first sub contact block and a second sub contact block which penetrate through the third laminated structure; and a fourth laminated structure arranged on one side surface of the third laminated structure far away from the semiconductor structure, wherein the fourth laminated structure is provided with a first sub-connection layer and a second sub-connection layer penetrating through the fourth laminated structure. Wherein the first sub-contact block and the second sub-contact block are in direct contact with the first sub-connection layer and the second sub-connection layer, respectively. Wherein the first sub-contact block and the first sub-connection layer are formed to have cross-sectional shapes respectively having sizes gradually decreasing in a direction away from the semiconductor structure, and the size of the first sub-connection layer is larger than that of the first sub-contact block at a contact interface of the first sub-contact block and the first sub-connection layer

In an embodiment according to the present disclosure, one of the first sub-contact blocks and one of the second sub-contact blocks are in direct contact with one of the connection layers.

Another aspect of the present disclosure provides a semiconductor structure comprising an array wafer and a peripheral wafer bonded to each other, wherein the array wafer comprises a three-dimensional memory as described above, and the peripheral wafer comprises peripheral circuitry for the three-dimensional memory.

According to the three-dimensional memory and the preparation method thereof disclosed by the invention, the contact block and the connecting layer with the profile which is narrow at the top and wide at the bottom can be formed, and the requirement of forming an interconnection structure for a peripheral wafer on an array wafer under an inverted X-stacking framework is met. By the contact block and the connection layer having a sectional shape that is narrow at the top and wide at the bottom, the connection layer (i.e., metal wiring) of the interconnect structure for the peripheral wafer can be made thinner and thinner in a direction away from the array wafer, so that the integration of the interconnect structure for connecting the peripheral wafer can be improved in this direction.

The above summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description.

Drawings

Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. Wherein:

FIG. 1 is a flow chart of a method of fabricating a three-dimensional memory according to an embodiment of the present disclosure;

FIG. 2 is a schematic cross-sectional view of a semiconductor structure for forming contact bumps and connection layers thereon in a fabrication method according to an embodiment of the present application;

fig. 3-8 are process schematic diagrams of a method of making a contact block according to an embodiment of the present disclosure;

fig. 9 to 13 are process schematic diagrams of a method of preparing a connection layer according to an embodiment of the present disclosure;

fig. 14 is a schematic cross-sectional view of an interconnect structure for a periphery wafer formed in an array wafer under an inverted X-stacking architecture according to another embodiment of the present disclosure.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

It should be noted that in the present description, the expressions first, second, third, etc. are used only to distinguish one feature from another, and do not indicate any limitation on the features, and do not particularly indicate any precedence order. Thus, a first side discussed in this application may also be referred to as a second side, and a first window may also be referred to as a second window, or vice versa, without departing from the teachings of this application.

In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Further, in this application, when "connected" or "coupled" is used, it may mean either direct contact or indirect contact between the respective components, unless there is an explicit other limitation or can be inferred from the context.

Fig. 1 is a flow chart of a method 1000 for fabricating a three-dimensional memory according to an embodiment of the present application. As shown in fig. 1, the present application provides a method 1000 for manufacturing a three-dimensional memory, including:

s1, forming a first laminated structure on one side surface of the semiconductor structure, and forming a contact hole penetrating through the first laminated structure in the first laminated structure;

s2, arranging a first filler in the contact hole to form a contact block;

s3, forming a second laminated structure on the surface of one side, far away from the semiconductor structure, of the first laminated structure, and forming a connecting opening in the second laminated structure;

and S4, arranging a second filler in the connecting opening to form a connecting layer.

A side surface of the contact block formed in the fabrication method 1000 adjacent to the semiconductor structure is in direct contact with the semiconductor structure, and a side surface thereof remote from the semiconductor structure is exposed in the connection opening and is in direct contact with a connection layer disposed in the connection opening. Further, the opening size of the cross section of the contact block is gradually reduced in a direction away from the semiconductor structure, and the opening size of the cross section of the connection layer is gradually reduced in a direction away from the semiconductor structure.

The specific processes of the steps of the above-described manufacturing method 1000 will be described in detail with reference to fig. 2 to 13. Specifically, fig. 2 is a schematic cross-sectional structure of the semiconductor structure 100 for forming a contact block and a connection layer thereon in the manufacturing method according to the embodiment of the present application, fig. 3 to 7 are schematic cross-sectional structures illustrating in detail a specific process of manufacturing a contact hole according to the manufacturing method 1000, fig. 8 is a schematic cross-sectional structure illustrating in detail a specific process of manufacturing a contact block according to the manufacturing method 1000, fig. 9 to 12 are schematic cross-sectional structures illustrating in detail a specific process of manufacturing a connection opening according to the manufacturing method 1000, and fig. 13 is a schematic cross-sectional structure illustrating in detail a specific process of manufacturing a connection layer according to the manufacturing method 1000.

Referring to fig. 2, a semiconductor structure 100 may include a substrate layer 101, a memory array 102, and a first interconnect structure 103 connected to the memory array 102.

The material of the substrate layer 101 may be selected from any suitable semiconductor material, such as a group iii-v compound, such as single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide. In this embodiment mode, the substrate 101 can be single crystal silicon.

The memory array 102 may be a stacked structure with channel holes formed on the substrate layer 101 for implementing the memory function of the memory device 100.

The first interconnect structure 103 is located on a side of the memory array 102 remote from the substrate layer 101 and may, for example, include vertical interconnect VIAs (VIA), one side of which may be electrically coupled with the memory array 102 and the other side of which may be electrically coupled to peripheral circuitry in a peripheral wafer (not shown), for example, through contact blocks and connection layers described below with reference to fig. 3-13. In particular, the peripheral circuit wafer may be, for example, a CMOS wafer including, for example, field effect transistors, capacitors, inductors, and/or PN junction diodes, etc., for implementing different functions of the three-dimensional memory, such as buffering, amplifying, decoding, etc. In one embodiment, a three-dimensional memory array may be fabricated in the memory array 102, forming a memory array wafer, and peripheral circuitry responsible for data I/O and memory cell operations separately fabricated on another peripheral circuitry wafer. After the two wafers are prepared, they may be bonded, and the bonded two wafers may be connected to each other through the contact block and the connection layer described below with reference to fig. 3 to 13. It is understood that the peripheral circuit wafer and the bonding process can be prepared by conventional processes according to actual needs, and detailed descriptions thereof are omitted.

A specific process of preparing the contact hole 301 according to the preparation method 1000 is described in detail below with reference to fig. 3 to 7.

As shown in fig. 3, a first stack 200 may be formed on a surface of the first interconnect structure 103 on a side remote from the substrate layer 101. Specifically, the first stacked structure 200 may include a first dielectric layer 201, a second dielectric layer 202, and a first sacrificial layer 203. The first dielectric layer 201, the second dielectric layer 202 and the first sacrificial layer 203 may be formed in sequence on a surface of the first interconnect structure 103 on a side away from the substrate layer 101 by any suitable process. In an exemplary embodiment, the processes for forming the first dielectric Layer 201, the second dielectric Layer 202, and the first sacrificial Layer 203 include, but are not limited to, any suitable process of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), Pulsed Laser Deposition (PLD), Liquid Source atomized Chemical Deposition (mclsd), and/or combinations thereof. In an embodiment, the deposition processes for forming the first dielectric layer 201, the second dielectric layer 202, and the first sacrificial layer 203 may be the same or different.

A first dielectric layer 201 is formed on the first interconnect structure 103 on a side remote from the substrate layer 101. The first dielectric layer 201 and the second dielectric layer 202 formed thereon may have a certain selectivity in the same etching/etching process to ensure that the first dielectric layer 201 is hardly removed when a portion of the second dielectric layer 202 is removed.

The material of the first dielectric layer 201 may be a nitride, including any suitable nitride material, but the disclosure is not limited thereto. In one embodiment by way of non-limiting example, the material of the first dielectric layer 201 may be selected to be silicon nitride. As described below with reference to fig. 7, a third contact hole portion 403 may be formed in the first dielectric layer 201 to penetrate through the first dielectric layer 201, and the material of the first dielectric layer 201 may be used to prevent the conductive material disposed in the third contact hole portion 403 from diffusing to both sides to affect the electrical performance of the semiconductor structure 100.

The thickness D1 of the first dielectric layer 201 may be set approximately at about several tens of angstroms

To about several hundred angstroms, although the disclosure is not so limited. In one embodiment, thickness D1 of first dielectric layer 201 may be set at about

To about

Within the range of (1). It should be understood that the thickness D1 given herein is merely exemplary and not an absolute thickness, and one skilled in the art can select appropriate dimensions according to actual needs based on the teachings of the present disclosure.

A second dielectric layer 202 is formed on a surface of the first dielectric layer 201 on a side thereof remote from the substrate. The material of the second dielectric layer 202 may be an oxide, including any suitable oxide material, although the disclosure is not limited thereto. In one embodiment, as a non-limiting example, the material of the second dielectric layer 202 may be selected to be silicon oxide.

The thickness D2 of the second dielectric layer 202 may be set approximately at about several tens of angstroms

To about several hundred angstroms, although the disclosure is not so limited. In one embodiment, thickness D2 of second dielectric layer 202 may be set at about

To about

Within the range of (1). It should be understood that the thickness D2 given herein is merely exemplary and not an absolute thickness, and one skilled in the art can select appropriate dimensions according to actual needs based on the teachings of the present disclosure.

A first sacrificial layer 203 is formed on a surface of the second dielectric layer 202 on a side thereof remote from the substrate layer 101. The first sacrificial layer 203 may be formed of nitride, including any suitable nitride material, but the disclosure is not limited thereto. In one embodiment, the material of the first sacrificial layer may be selected to be silicon nitride.

The thickness D3 of the first sacrificial layer 203 may be generally set in the range of about several tens of angstroms to about several hundreds of angstroms, but the present disclosure is not limited thereto. In one embodiment, thickness D3 of first sacrificial layer 203 may be set at about

To about

Within the range of (1). In general, the thickness of the first sacrificial layer 203 may be greater than the thickness of the first dielectric layer 201 and the second dielectric layer 202. It should be understood that the thickness D3 given herein is merely exemplary and not an absolute thickness, and one skilled in the art can select appropriate dimensions according to actual needs based on the teachings of the present disclosure.

Then, referring to fig. 4, the first sacrificial layer 203 is patterned to obtain first space patterns 301 and contact hole sacrificial blocks 302 spaced apart via the space patterns 301. The first spacer pattern 301 and the contact hole sacrificial block 302 may be formed through a photolithography process and a subsequent etching process.

The photolithography process for forming the first space pattern 301 and the contact hole sacrificial block 302 includes forming a pattern mask (not shown) on the first sacrificial layer 203. The pattern mask used in the photolithography process may employ, for example, an electrolyte anti-reflective coating (DARC), a carbon hard mask, a bottom anti-reflective coating (BARC), a photoresist, or the like. The pattern of the first spacing pattern 301 is defined by a pattern mask, and then the pattern of the first spacing pattern 301 may be transferred to the first sacrificial layer 203 by an etching process.

The etching may be performed using any suitable etching process to transfer the pattern of the first spacer patterns 301 to the first sacrificial layer 203. In one embodiment, an anisotropic etching process may be used to form the first spacer patterns 301 in the first sacrificial layer 203. For example, the first spacer pattern 301 may be formed using a dry etching process such as vapor phase etching, but the present disclosure is not limited thereto.

In the case where the first space pattern 301 is formed using a vapor phase etching process, etching is performed using an etching gas as an etchant and exposing the semiconductor structure to the etching gas. The shape of the first space pattern 301 may be defined by controlling the kind, flow rate and mixture ratio of the etching gas, rf power, temperature or a combination thereof. Specifically, the first space pattern 301 may have a cross section in which the size of the opening gradually increases in a direction away from the substrate. In one embodiment, the first spacing pattern 301 may have a trapezoidal cross section that is wide at the top and narrow at the bottom, that is, has the longer side of two sides of the trapezoid that are parallel to each other on the side away from the substrate layer 101, and has the shorter side of two sides of the trapezoid that are parallel to each other on the side adjacent to the substrate layer 101, as shown in fig. 4, but the present disclosure is not limited thereto. The height of the first spacing pattern 301 in a direction perpendicular to the substrate layer 101 may be the same as the height of the first sacrificial layer 203. In other embodiments, the first space pattern 301 may be formed by etching the first sacrificial layer 203 and etching a portion of the second dielectric layer 202. The height of the first spacer pattern 301 in the direction perpendicular to the substrate layer 101 may be slightly greater than the height of the first sacrificial layer 203, but less than the sum of the heights of the first sacrificial layer 203 and the second dielectric layer 202 in the direction perpendicular to the substrate layer 101.

After the etching to form the first space patterns 301 is completed, the remaining mask layer may be removed by an optional ashing and cleaning process. To simplify the description and not obscure the nature of the present disclosure, a detailed description of the pattern mask, ashing, and cleaning processes will not be provided.

The remaining portions of first sacrificial layer 203, which are not etched, obtained after first spacer patterns 301 are formed by etching, are contact hole sacrificial blocks 302. Accordingly, the contact hole sacrificial block 302 may have a cross-sectional shape that gradually decreases in size in a direction away from the substrate. In one embodiment, the contact hole sacrificial block 302 may have an inverted trapezoidal cross-sectional shape with a narrow top and a wide bottom, i.e., a shorter side of two parallel sides of the trapezoid on a side away from the substrate layer 101, and a longer side of two parallel sides of the trapezoid on a side adjacent to the substrate layer 101. Contact hole 400 will be formed in subsequent processing by removing a portion of contact hole sacrificial block 302 and underlying second dielectric layer 202 and first dielectric layer 201, as will be described below with reference to fig. 5-7.

Referring to fig. 5, a third dielectric layer 303 may be formed in the first space pattern 301 by a suitable manufacturing process. The material of the third dielectric layer 303 may be an oxide such as silicon oxide, but the present disclosure is not limited thereto. It is understood that the material of the third dielectric layer 303 may be the same as or different from the material of the second dielectric layer 202.

In an embodiment, the third dielectric layer 303 may be formed by, for example, CVD, PVD, ALD, PLD, LSMCD, and/or any suitable combination thereof. Then, the surface of the first stack structure 200 may be planarized by a planarization process such as chemical mechanical polishing so that the height of the upper surface of the oxide deposited in the first space pattern 301 is flush with the height of the upper surface of the first sacrificial layer 203.

Referring to fig. 6, the contact hole sacrificial block 302 may be removed by a suitable manufacturing process such as wet etching to obtain a first contact hole portion 401, and a portion of the second dielectric layer 202 exposed in the first contact hole portion 401 is removed to obtain a second contact hole portion 402. In the wet etching, an etching solution may be used as an etchant, and the semiconductor structure is immersed in the etching solution to be etched.

As described above with reference to fig. 3, the second dielectric layer 202 and the underlying first dielectric layer 201 may have a certain selectivity in the same etching/etching process to ensure that the first dielectric layer 201 is hardly removed when a portion of the second dielectric layer 202 is removed.

It is understood that the contact hole sacrificial block 302 and a portion of the underlying second dielectric layer 202 may be removed in the same removal step, or both may be removed in different steps, and those skilled in the art can select a suitable removal process according to the actual needs based on the teachings of the present disclosure.

As described earlier, since the contact hole sacrificial block 302 has a sectional shape with a gradually decreasing size in a direction away from the substrate layer 101, after removing the contact hole sacrificial block 302 by using a suitable removal process such as wet etching, the first contact hole portion 401 is formed to also have a sectional shape with an opening size gradually decreasing in a direction away from the substrate layer 101. In the embodiment where contact hole sacrifice part 302 has an inverted trapezoidal sectional shape that is narrow at the top and wide at the bottom, first contact hole part 401 accordingly has an inverted trapezoidal sectional shape, that is, has the shorter of two sides of the trapezoid that are parallel to each other on the side away from substrate layer 101 and the longer of the two sides of the trapezoid that are parallel to each other on the side adjacent to substrate layer 101, as shown in fig. 6.

Referring to fig. 7, a portion of the first dielectric layer 201 exposed in the second contact hole portion 402 may be removed by a suitable manufacturing process to form a third contact hole portion 403 through the first dielectric layer 201. In one embodiment, an anisotropic etching process such as vapor phase etching may be employed to remove the portion of the first dielectric layer 201 exposed in the second contact hole portion 402 to form the third contact hole portion 403, but the disclosure is not limited thereto. In the case where the first dielectric layer 201 is thin, the third contact hole portion 403 may also be formed by wet etching as described above with reference to fig. 4.

In vapor phase etching, an etching gas is used as an etchant, and the semiconductor structure is exposed to the etching gas. The etching speed can be controlled by the type, flow and proportion of the etching gas, radio frequency power, temperature or the combination thereof.

In the case where the vapor etching process is employed to form the third contact hole portions 403, since the lateral etching rate is much smaller than the longitudinal etching rate, the lateral direction is hardly etched, so that the third contact hole portions 403 may have a rectangular sectional shape with sidewalls substantially perpendicular to the bottom surface, and the third contact hole portions 403 are completely exposed in the second contact hole portions 402, that is, the width of the third contact hole portions 403 in the direction parallel to the substrate 101 may be not smaller than the width of the shorter sides of the first contact hole portions 401 and not greater than the width of the longer sides of the first contact hole portions 401.

The first contact hole portion 401, the second contact hole portion 402, and the third contact hole portion 403 collectively form the contact hole 400. It can be seen that at least a portion of the first interconnect structure 103 is exposed in the contact hole 400.

As described above, the first contact hole portion 401 may have a sectional shape in which the opening size gradually decreases in a direction away from the substrate layer 101. For example, the first contact hole portion 401 may have an inverted trapezoidal sectional shape which is narrow at the top and wide at the bottom, that is, the first contact hole portion 401 has a shorter side at a side away from the substrate layer 101 and a longer side at a side adjacent to the substrate layer 101, as shown in fig. 6. According to an exemplary embodiment, the heights of the second contact hole portion 402 and the third contact hole portion 403 in a direction perpendicular to the substrate layer 101 are each much smaller than the height of the first contact hole 401, and thus the shape of the contact hole 400 is substantially defined by the shape of the first contact hole 401. That is, the contact hole 400 may have a sectional shape in which the opening size gradually decreases in a direction away from the substrate layer 101. In the embodiment in which the first contact hole portion 401 has an inverted trapezoidal sectional shape which is narrow at the top and wide at the bottom, the sectional shape of the contact hole 400 is also substantially an inverted trapezoidal shape whose side closer to the substrate layer 101 is the longer side of two sides of the trapezoid which are parallel to each other and whose side farther from the substrate layer 101 is the shorter side of two sides of the trapezoid which are parallel to each other.

A specific process of preparing the contact block 501 according to the preparation method 1000 is described in detail below with reference to fig. 8. The contact block 501 may be formed in the contact hole 400 by a suitable fabrication process (e.g., CVD, PVD, ALD, PLD, LSMCD, and/or combinations thereof). The contact block 501 is formed of a conductive material for connecting the first interconnect structure 103 thereunder to a connection layer 901 (as described below with reference to fig. 9-13). In one embodiment, the material forming the contact block 501 may be a metal such as tungsten. In another embodiment, the material forming the contact block 501 may be polysilicon or silicide filled with a conductive material. In other embodiments, the material forming the contact block 501 may be any suitable material capable of electrically connecting the first interconnect structure 103 to the connection layer 901 and thus to a circuit structure (e.g., a peripheral wafer or other connection layer) disposed thereon.

The process of forming the contact block 501 in the semiconductor structure that has been described above with reference to fig. 3 to 8 is merely exemplary. In other embodiments, one or more of the processes described with reference to fig. 3-8 may be omitted without departing from the spirit and scope of the present disclosure. For example, in one embodiment, the first stack structure 200 may be formed of only the first sacrificial layer, i.e., the first dielectric layer 201 and the second dielectric layer 202 may be omitted. In this embodiment, the contact block 501 may be formed by filling a conductive material in the first contact hole portion 401.

A process of forming the connection layer 901 in the semiconductor structure is described below with reference to fig. 9 to 13.

As shown in fig. 9, a second stacked structure 600 is formed on a surface of the first stacked structure 200 on a side away from the substrate layer 101. Specifically, the second stacked structure 600 may include a fourth dielectric layer 601, a fifth dielectric layer 602, and a second sacrificial layer 603. A fourth dielectric layer 601, a fifth dielectric layer 602 and a second sacrificial layer 603 may be formed in sequence on a surface of the first stacked structure 200 on a side facing away from the substrate layer 101 by any suitable process. In an exemplary embodiment, the processes for forming the fourth dielectric layer 601, the fifth dielectric layer 602, and the second sacrificial layer 603 include, but are not limited to, any suitable process of CVD, PVD, ALD, PLD, LSMCD, and/or combinations thereof. In the embodiment, the processes for forming the fourth dielectric layer 601, the fifth dielectric layer 602, and the second sacrificial layer 603 may be the same or different.

The fourth dielectric layer 601 and the fifth dielectric layer 602 formed thereon may have a certain selectivity in the same etching/etching process to ensure that the fourth dielectric layer 601 is hardly removed when a portion of the fifth dielectric layer 602 is removed.

The material of the fourth dielectric layer 601 may be a nitride, including any suitable nitride material, but the disclosure is not limited thereto. In one embodiment by way of non-limiting example, the material of the fourth dielectric layer 601 may be selected to be silicon nitride. As described below with reference to fig. 12, a third opening portion 803 may be formed in the fourth dielectric layer 601 to penetrate through the fourth dielectric layer 601, and the material of the fourth dielectric layer 601 may be used to prevent the conductive material disposed in the third opening portion 803 from diffusing to both sides to affect the electrical performance of the semiconductor structure 100.

The thickness D4 of the fourth dielectric layer 601 may be set approximately at about several tens of angstroms

To about several hundred angstroms, although the disclosure is not so limited. In one embodiment, thickness D4 of first dielectric layer 201 may be set at about

To about

Within the range of (1). It should be understood that the thickness D4 given herein is merely exemplary and not an absolute thickness, and one skilled in the art can select appropriate dimensions according to actual needs based on the teachings of the present disclosure.

A fifth dielectric layer 602 is formed on a surface of the fourth dielectric layer 601 on a side remote from the substrate. The material of the fifth dielectric layer 602 may be an oxide, including any suitable oxide material, but the disclosure is not limited thereto. In one embodiment by way of non-limiting example, the material of the fifth dielectric layer 804 may be selected to be silicon oxide.

The thickness D5 of the fifth dielectric layer 602 may be set approximately at about several tens of angstroms

To about several hundred angstroms, although the disclosure is not so limited. In one embodiment, thickness D5 of fifth dielectric layer 602 may be set at about thickness D5

To about

Within the range of (1). It should be understood that the thickness D5 given herein is merely exemplary and not an absolute thickness, and one skilled in the art can select appropriate dimensions according to actual needs based on the teachings of the present disclosure.

A second sacrificial layer 603 is formed on a surface of the fifth dielectric layer 602 on a side thereof remote from the substrate layer 101. The second sacrificial layer 603 may be formed of nitride, including any suitable nitride material, but the disclosure is not limited thereto. In one embodiment, the material of the second sacrificial layer 603 may be selected to be silicon nitride.

The thickness D6 of the second sacrificial layer 603 may be generally set in the range of about several tens of angstroms to about several hundreds of angstroms, but the present disclosure is not limited thereto. In one embodiment, the thickness D6 of the second sacrificial layer 603 may be set at about

To about

Within the range of (1). In general, the thickness of the second sacrificial layer 603 may be greater than the thickness of the fourth dielectric layer 601 and the fifth dielectric layer 602. It should be understood that the thickness D6 given herein is merely exemplary and not an absolute thickness, and one skilled in the art can select appropriate dimensions according to actual needs based on the teachings of the present disclosure.

Referring to fig. 10, the second sacrificial layer 603 is patterned to obtain second spaced patterns 701 and connection sacrificial layers 702 spaced apart via the second spaced patterns 701. The second spacer pattern 701 may be formed through a photolithography process and then an etching process. A preparation method for forming the second spacer patterns 701 includes photolithography and a subsequent etching process, which may be the same as the preparation method for forming the first spacer patterns 301 described above with reference to fig. 4, and a detailed description thereof is omitted.

According to one exemplary embodiment, the second spacer pattern 701 may be formed using dry etching similarly to the first spacer pattern 301, and similarly, the second spacer pattern 701 may have a profile in which an opening size gradually increases in a direction away from the substrate. In one embodiment, the second spacer pattern 701 may have a trapezoidal section that is wide at the top and narrow at the bottom, that is, has a longer side of two sides of the trapezoid that are parallel to each other on a side away from the substrate layer 101, and has a shorter side of two sides of the trapezoid that are parallel to each other on a side adjacent to the substrate layer 101, as shown in fig. 10, but the present disclosure is not limited thereto. The height of the second spacer pattern 701 in a direction perpendicular to the substrate layer 101 may be the same as the height of the second sacrificial layer 603. In other embodiments, the second spacer pattern 701 may be formed by etching the second sacrificial layer 603 and etching a portion of the fifth dielectric layer 602. The height of the second spacer pattern 701 in the direction perpendicular to the substrate layer 101 may be slightly greater than the height of the second sacrificial layer 603, but less than the sum of the heights of the second sacrificial layer 603 and the fifth dielectric layer 602 in the direction perpendicular to the substrate layer 101.

The remaining portion of the second sacrificial layer 603, which is obtained after the second spacer patterns 701 are formed by etching and is not etched, is the connection sacrificial layer 702. Accordingly, the connection sacrificial layer 702 may have a sectional shape gradually decreasing in size in a direction away from the substrate. In one embodiment, the connecting sacrificial layer 702 may have an inverted trapezoidal sectional shape with a narrow top and a wide bottom, that is, a shorter side of two parallel sides of the trapezoid on a side away from the substrate layer 101, and a longer side of two parallel sides of the trapezoid on a side adjacent to the substrate layer 101. The connection opening 800 will be formed in a subsequent process by removing the connection sacrificial layer 702 and portions of the fifth dielectric layer 602 and the fourth dielectric layer 601 thereunder, as will be described below with reference to fig. 11 to 12.

Referring to fig. 11, a sixth dielectric layer 703 may be formed in the second spacer pattern 701 by an appropriate manufacturing process. The material of the sixth dielectric layer 703 may be any suitable oxide such as silicon oxide, but the disclosure is not limited thereto. It is understood that the material of the sixth dielectric layer 703 may be the same as or different from the material of the fifth dielectric layer 602.

The sixth dielectric layer 703 may be formed by, for example, CVD, PVD, ALD, PLD, LSMCD, and/or any suitable combination thereof. Then, the surface of the second stack structure 600 is planarized by a planarization process such as chemical mechanical polishing so that the height of the upper surface of the oxide deposited in the second spacer pattern 701 is flush with the height of the upper surface of the second sacrificial layer 603.

Then, similarly to the process for forming the contact hole 400, the connection sacrificial layer 702 may be removed by a suitable manufacturing process such as wet etching to obtain the first connection opening portion 801, and a portion of the fifth dielectric layer 602 exposed in the first connection opening portion 801 is removed to obtain the second connection opening portion 802.

As described with reference to fig. 9, the fifth dielectric layer 602 and the underlying fourth dielectric layer 601 may have a certain selectivity in the same etching/etching process to ensure that the fourth dielectric layer 601 is hardly removed when a portion of the fifth dielectric layer 602 is removed.

It is understood that the connection sacrificial layer 702 and a portion of the fifth dielectric layer 602 thereunder may be removed in the same removal step, or the removal of the connection sacrificial layer 702 and the portion of the fifth dielectric layer 602 may be performed in different steps, and those skilled in the art can select a suitable removal process according to the actual needs based on the teachings of the present disclosure.

As described earlier, since the connection sacrificial layer 702 has a sectional shape with a gradually decreasing size in a direction away from the substrate layer 101, the first connection opening portion 801 is formed to also have a sectional shape with an opening size gradually decreasing in a direction away from the substrate layer 101 after removing the connection sacrificial layer 702 by using a suitable manufacturing process such as wet etching. In the embodiment in which the connection sacrificial layer 702 has an inverted trapezoidal section with a narrow top and a wide bottom, the first connection opening portion 801 accordingly has an inverted trapezoidal section shape with a narrow top and a wide bottom, that is, the first connection opening portion 801 has a shorter side of two sides of the trapezoid parallel to each other on the side away from the substrate layer 101 and a longer side of two sides of the trapezoid parallel to each other on the side adjacent to the substrate layer 101, as shown in fig. 12, but the present disclosure is not limited thereto. In other embodiments, the first connection opening portion 801 may have a rectangular sectional shape with a bottom surface whose side wall is substantially perpendicular to the bottom surface. The person skilled in the art will readily understand that the openings defining the connecting layer 16 may accordingly also have a rectangular cross-sectional shape.

Then, similarly to the process for forming the third contact hole portion 403, a third connection opening portion 803 penetrating the fourth dielectric layer 601 may be formed by removing a portion of the fourth dielectric layer 601 exposed in the second connection opening portion 802 using an anisotropic etching process such as vapor phase etching, as shown in fig. 12.

In the vapor phase etching, since the lateral etching rate is much smaller than the longitudinal etching rate, the lateral direction is hardly etched, and therefore the third connection opening portion 803 may have a rectangular sectional shape with a side wall substantially perpendicular to the bottom surface, and the third connection opening portion 803 is completely exposed in the second connection opening portion 802, that is, the width of the third connection opening portion 803 in a direction parallel to the substrate 101 may be not smaller than the width of the shorter side of the first connection opening portion 801 and not larger than the width of the longer side of the first connection opening portion 801.

The first connection opening portion 801, the second connection opening portion 802, and the third connection opening portion 803 collectively form a connection opening 800. Through the process described with reference to fig. 9 to 12, the upper surface of the contact block 501 is completely exposed in the connection opening 800. Thus, the lower surface of the connection layer 901 (described below) disposed in the connection opening 800 may completely cover the upper surface of the contact block 501 to achieve reliable electrical connection.

According to an exemplary embodiment, the height of the second connection opening portion 802 and the third connection opening portion 803 in a direction perpendicular to the substrate layer 101 is much smaller than the height of the first connection opening portion 801, and thus the shape of the connection opening 800 is substantially defined by the shape of the first connection opening portion 801, i.e. the connection opening 800 has a cross-sectional shape with dimensions that gradually decrease in a direction away from the substrate layer 101. In the embodiment in which the first connection opening portion 801 has an inverted trapezoidal sectional shape which is narrow at the top and wide at the bottom (as shown in fig. 12), the section of the connection opening 800 is also substantially in the shape of an inverted trapezoid whose side closer to the substrate layer 101 is the longer side of two sides in which trapezoids are parallel to each other and whose side farther from the substrate layer 101 is the shorter side of two sides in which trapezoids are parallel to each other. In embodiments where the first connection opening portion 801 has a rectangular cross-sectional shape, the cross-section of the connection opening 800 is also substantially rectangular in shape (as can be taken from fig. 14).

Then, a connection layer may be formed in the connection opening 800 by an appropriate manufacturing process. In an embodiment, the connection layer 901 may be formed by a deposition process such as CVD, PVD, ALD, PLD, LSMCD, and/or any suitable combination thereof. The connection layer 901 is directly connected to the contact block 501 on one side and may be connected to a circuit structure disposed thereon, for example, to a peripheral wafer after the array wafer is bonded thereto, or to other connection layers disposed thereon. The material of the connection layer may be any suitable conductive metal material capable of electrically connecting the contact block 501 to the circuit structure disposed thereon and ultimately electrically connecting the first interconnect structure 103 to the peripheral wafer. In one embodiment, as a non-limiting example, the material of the connection layer may be selected to be copper.

The contact blocks 501 and connection layers 901 formed on the first interconnect structure 103 may constitute a second interconnect structure to be connected to peripheral circuitry in a peripheral wafer.

By forming the second interconnect structure to be connected to the peripheral circuits on the array wafer according to the steps of the method 1000 described above with reference to fig. 2 to 13, a three-dimensional memory including the contact block 501 and the connection layer 901 having a cross-sectional shape that is narrow at the top and wide at the bottom can be formed, as shown in fig. 13. Specifically, the three-dimensional memory may include a first stacked structure 200 (as illustrated in fig. 2) disposed on one side surface of a semiconductor structure, the first stacked structure 200 having a contact block 501 disposed in a contact hole 400 (as illustrated in fig. 7) penetrating the first stacked structure 200 therein. Further, the three-dimensional memory may comprise a second stacked structure 600 (as shown in fig. 9) disposed on a surface of the first stacked structure 200 on a side away from the semiconductor structure, the second stacked structure 600 having therein a connection layer 901 disposed in a connection opening 800 (as shown in fig. 12) through the second stacked structure 600. In the three-dimensional memory, a side surface of the contact block 501 adjacent to the semiconductor structure 100 is in direct contact with the semiconductor structure, and a side surface of the contact block 501 remote from the semiconductor structure 100 is in direct contact with the connection layer 901.

The process of forming the connection layer 901 in the semiconductor structure described above with reference to fig. 9 to 13 is merely exemplary. In other embodiments, one or more of the processes described with reference to fig. 9-13 may be omitted without departing from the spirit and scope of the present disclosure. For example, in one embodiment, the second stacked structure 600 may be formed only of the second sacrificial layer 603, i.e., the fourth dielectric layer 601 and the fifth dielectric layer 602 may be omitted. In this embodiment mode, the connection layer 901 may be formed by filling a conductive material in the first connection opening portion 801.

The steps of forming contact blocks and connection layers of an interconnect structure for a peripheral wafer on an array wafer in direct contact with each other under an inverted X-stacking architecture according to one embodiment of the present disclosure, and a three-dimensional memory formed by the respective steps of the method are schematically illustrated above with reference to fig. 2 to 13. Referring now to fig. 14, a schematic cross-sectional view of an interconnect structure for a peripheral wafer (not shown) formed in an array wafer under an inverted X-stacking architecture, according to another embodiment of the present disclosure.

The interconnect structures provided in the array wafer 10 are schematically shown in fig. 14, including a first interconnect structure 11 connected to the memory arrays in the array wafer and a second interconnect structure 12 to be connected to the peripheral circuitry in the peripheral wafer.

The first interconnect structure 11 is disposed over a storage array (not shown) in an array wafer, and is the same as the first interconnect structure 103 described above with reference to fig. 2 to 13, and a detailed description thereof is omitted here for the sake of brevity. The first interconnect structure 11 is an interconnect structure formed according to a conventional process, and as will be appreciated by those skilled in the art, the integration degree thereof is lower and lower in a direction away from the substrate, that is, the line width of a connection portion (hereinafter, referred to as "metal line") which may be formed of, for example, a conductive metal, for an interconnect of a memory array is larger and smaller, and the number of lines which can be arranged in the same area is smaller and smaller. For example, the first interconnect structure 11 may include one or more interconnect layers arranged in a direction perpendicular to the substrate, each interconnect layer including a plurality of metal wirings, and the integration degree of the metal wirings in the interconnect layers gradually decreases in a direction away from the substrate. For ease of understanding, only one metal line in an interconnect layer of the first interconnect structure 11 in contact with the first stacked structure is schematically shown in fig. 14, but those skilled in the art will appreciate that this is only illustrative and not limiting.

The second interconnect structure 12 may include a first contact block 13, a first connection layer 14, a second contact block 15, and a second connection layer 16, which are sequentially formed in a direction away from the first interconnect structure 11. The first contact bumps 13 are used to electrically connect the first interconnect structures 11 in the array wafer 10 to the first connection layer 14, and the second contact bumps 15 are used to electrically connect the first connection layer 14 to the second connection layer 16. After bonding the array wafer 10 to a peripheral wafer (not shown), the first contact bumps 13, the first connection layer 14, the second contact bumps 15, and the second connection layer 16 together electrically connect the first interconnect structures 11 in the array wafer 10 to peripheral circuitry in the peripheral wafer, thereby interconnecting the memory arrays with the peripheral circuitry. Thus, under an inverted X-stacking architecture, connection of the memory arrays in the array wafer 10 to the peripheral circuitry in the peripheral wafer may be achieved through the second interconnect structures 12 arranged in the array wafer for interconnection of the peripheral circuitry. For the sake of clarity of display, only the contact block and the connection layer are schematically illustrated in fig. 14, and the stacked structure in which the contact block and the connection layer are formed is not illustrated.

The first and second contact blocks 13, 15 may be formed in accordance with the method and steps for forming the contact block 501 illustrated above with reference to fig. 2 to 8, and thus have a cross-sectional shape with gradually decreasing dimensions in a direction away from the first interconnect structure 11 of the array wafer 10. In one embodiment, the first and second contact blocks 13 and 15 may have an inverted trapezoidal sectional shape (as shown in fig. 14) which is narrow at the top and wide at the bottom in a direction away from the first interconnect structure 11, and a detailed description thereof is omitted herein for the sake of brevity. The first connection layer 14 and the second connection layer 16 may be formed according to the method and steps for forming the connection layer 901 described above with reference to fig. 9 to 13, and thus have a cross-sectional shape with gradually decreasing size in a direction away from the first interconnect structure 11 of the array wafer 10. In one embodiment, the first connection layer 14 and the second connection layer 16 may have an inverted trapezoidal sectional shape (as shown in fig. 14) having a narrow top and a wide bottom in a direction away from the first interconnect structure 11, and a detailed description thereof is omitted herein for the sake of brevity. But the shapes of the first and second connection layers 14 and 16 are not limited thereto. In another embodiment, the cross-section of the first and second connection layers 14 and 16 may have a rectangular shape with sidewalls substantially perpendicular to the bottom surface.

It will be appreciated that, due to the narrow-top-to-wide configuration of the first tie layer 14, i.e., the upper surface thereof being less wide than the lower surface thereof, the dimensions of the first tie layer 14 are defined by the width of the wider lower surface. On the other hand, the lower surface of the first connection layer 14 formed on the first contact block 13 may cover the upper surface of the first contact block 13 to achieve reliable electrical connection. Due to the narrow-top and wide-bottom structure of the first contact block 13, the first connection layer 14 overlying the narrower upper surface of the first contact block 13 may accordingly have a relatively small width of the lower surface. In this way, the first connection layer 14 may have a reduced size, i.e. a reduced line width, with respect to the metal lines in the first interconnect structure 11, compared to conventional process. As shown in fig. 14, two first connection layers 14 may correspond to each other over the same length as the line width of the metal wire in the first interconnection structure 11, and the width of each first connection layer 14 is smaller than the width of the metal wire in the first interconnection structure 11.

Similarly to the first connection layer 14, due to the narrow-top and wide-bottom structure of the second contact block 15 and the second connection layer 16, the second connection layer 16 may have a reduced size, i.e., a reduced line width, with respect to the first connection layer 14. Thus, two second connection layers 16 may correspond to each other in the same length as the line width of the first connection layer 14, and each second connection layer 16 has a width smaller than that of the first connection layer 14. It will be understood by those skilled in the art that the above correspondence is merely exemplary, and more first connection layers 14 may be corresponded to in the same length as the line width of the metal wiring in the first interconnect structure 11. Similarly, more second connection layers 16 may correspond over the same length as the line width of the first connection layer 14.

As can be seen from the above description in conjunction with fig. 14, by forming the contact block and the connection layer with a cross-sectional shape that is narrow at the top and wide at the bottom according to the present disclosure, the requirement of forming the interconnect structure for the peripheral wafer on the array wafer under the inverted X-stacking architecture can be satisfied, and the integration of the peripheral circuit interconnect structure can be improved in a direction away from the substrate layer of the array wafer.

It will be understood by those skilled in the art that the first contact block 13, the first connection layer 14, the second contact block 15 and the second connection layer 16 shown in fig. 14 are merely illustrative and not intended to be limiting. In an actual circuit, more connection layers and corresponding contact blocks may be formed in a direction away from the substrate layer using the method described above with reference to fig. 2-13, depending on the interconnection needs of the circuit. For example, in another embodiment, a third contact block may be formed on the second contact block 15, and the third contact block may be electrically connected to a fourth connection layer disposed thereon, so that after the array wafer 10 is bonded to the peripheral wafer, the memory arrays in the array wafer 10 are electrically connected to the peripheral circuits in the peripheral wafer via the first contact block 13, the first connection layer 14, the second contact block 15, the second connection layer 16, the third contact block, and the third connection layer. According to the manufacturing method of the present disclosure, the size of the third contact block and the third connection layer may be further reduced with respect to the second contact block 15 and the second connection layer 16, thereby ensuring that the integration of the interconnect structure for the peripheral wafer may be higher and higher in a direction away from the substrate.

It should be noted that additional steps may be provided before, during, and after process 1000, and that some of the steps described herein may be replaced, deleted, performed in a different order, or performed in parallel.

The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. A method of fabricating a three-dimensional memory, comprising:

forming a first laminated structure on one side surface of a semiconductor structure, and forming a contact block penetrating through the first laminated structure in the first laminated structure;

forming a second laminated structure on the surface of the first laminated structure far away from the semiconductor structure, and forming a connecting layer penetrating through the second laminated structure in the second laminated structure,

wherein the contact block is in direct contact with the connection layer, the contact block and the connection layer each have a cross-sectional shape that decreases in size in a direction away from the semiconductor structure, the size of the connection layer being greater than the size of the contact block at a contact interface of the contact block and the connection layer.

2. The method of claim 1, wherein the semiconductor structure comprises a substrate layer, a storage array disposed on a side surface of the substrate layer, and an interconnect structure disposed on the storage array,

wherein forming the first stacked structure on a side surface of the semiconductor structure comprises: forming the first stack structure on a surface of the interconnect structure remote from the substrate layer,

a side surface of the contact block adjacent the semiconductor structure is in direct contact with the interconnect structure such that the interconnect structure is electrically connected to peripheral circuitry in a peripheral wafer through the contact block and the connection layer.

3. The method of claim 2, wherein the interconnect structure comprises a plurality of connection portions, at least one of the plurality of connection portions is in direct contact with at least two contact blocks formed in the first stacked structure, and each of the at least two contact blocks is formed to be in direct contact with a corresponding one of the connection layers, respectively.

4. The method of claim 2, wherein the first stacked structure comprises a first sacrificial layer, wherein forming the contact block in the first stacked structure comprises:

patterning the first sacrificial layer to obtain a first interval pattern and a contact hole sacrificial block arranged at intervals through the first interval pattern, wherein the contact hole sacrificial block has a cross-sectional shape with a size gradually reduced in a direction away from the semiconductor structure;

arranging a third filler in the first interval pattern to form a third dielectric layer;

removing the sacrificial block to obtain a first contact hole portion; and

filling a conductive material in the first contact hole portion to form the contact block.

5. The method of claim 4, wherein the first stacked structure further comprises a first dielectric layer and a second dielectric layer sequentially formed between the interconnect structure and the first sacrificial layer, the forming the contact block in the first stacked structure further comprising:

after the first contact hole portion is formed in the first sacrificial layer, removing a portion of the second dielectric layer exposed in the first contact hole portion to obtain a second contact hole portion;

removing the part of the first dielectric layer exposed in the second contact hole part to obtain a third contact hole part; and

and filling a conductive material in a contact hole formed by the first contact hole part, the second contact hole part and the third contact hole part together to form the contact block.

6. The method of claim 1, wherein the second stacked structure comprises a second sacrificial layer, wherein forming the connection layer in the second stacked structure comprises:

patterning the second sacrificial layer to obtain a second interval pattern and a connection sacrificial layer arranged at intervals through the second interval pattern, wherein the connection sacrificial layer has a cross-sectional shape with a size gradually reduced in a direction away from the semiconductor structure;

arranging a fourth filler in the second interval pattern to form a sixth dielectric layer;

removing the connection sacrificial layer to obtain a first connection opening portion; and

filling a conductive material in the first connection opening portion to form the connection layer.

7. The method of claim 6, wherein the second stack further comprises a fourth dielectric layer and a fifth dielectric layer sequentially formed between the first stack and the second sacrificial layer, the forming the connection layer in the second stack further comprising:

after the first connection opening part is formed in the second sacrificial layer, removing a part of the fifth dielectric layer exposed in the first connection opening part to obtain a second connection opening part;

removing the part of the fourth dielectric layer exposed in the second connection opening part to obtain a third connection opening part; and

and filling a conductive material in a connection opening formed by the first connection opening part, the second connection opening part and the third connection opening part together to form the connection layer.

8. The method of claim 1, further comprising:

forming a third laminated structure on the surface of one side of the second laminated structure far away from the semiconductor structure, and forming a first sub-contact block and a second sub-contact block penetrating through the third laminated structure in the third laminated structure; and

forming a fourth laminated structure on a surface of the third laminated structure on a side away from the semiconductor structure, and forming a first sub-connection layer and a second sub-connection layer penetrating the fourth laminated structure in the fourth laminated structure,

wherein the first sub-contact block and the second sub-contact block are in direct contact with the first sub-connection layer and the second sub-connection layer, respectively, the first sub-contact block and the first sub-connection layer are formed to have cross-sectional shapes that decrease in size in a direction away from the semiconductor structure, respectively, and the size of the first sub-connection layer is greater than the size of the first sub-contact block at a contact interface of the first sub-contact block and the first sub-connection layer.

9. The method of claim 8, wherein one of the first sub-contact blocks and one of the second sub-contact blocks are formed in direct contact with one of the connection layers.

10. A three-dimensional memory, comprising:

a first stacked structure disposed on one side surface of the semiconductor structure, the first stacked structure having a contact block therein penetrating the first stacked structure; and

a second stacked structure disposed on a surface of the first stacked structure on a side remote from the semiconductor structure, the second stacked structure having therein a connection layer penetrating the second stacked structure,

11. The three-dimensional memory of claim 10, wherein the semiconductor structure comprises a substrate layer, a storage array disposed on a side surface of the substrate layer, and an interconnect structure disposed on the storage array,

wherein the first stacked structure is formed on a surface of the interconnect structure remote from the substrate layer, a side surface of the contact block adjacent to the semiconductor structure being in direct contact with the interconnect structure, such that the interconnect structure is electrically connected to peripheral circuitry in a peripheral wafer through the contact block and the connection layer.

12. The three-dimensional memory of claim 11, wherein the interconnect structure comprises a plurality of connection portions, at least one of the connection portions being in direct contact with at least two contact blocks formed in the first stacked structure, and each of the at least two contact blocks being in direct contact with a corresponding one of the connection layers, respectively.

13. The three-dimensional memory of claim 10, further comprising:

a third laminated structure arranged on one side surface of the second laminated structure far away from the semiconductor structure, wherein the third laminated structure is provided with a first sub contact block and a second sub contact block which penetrate through the third laminated structure; and

a fourth stacked structure disposed on a surface of the third stacked structure on a side away from the semiconductor structure, the fourth stacked structure having therein a first sub-connection layer and a second sub-connection layer penetrating the fourth stacked structure,

14. The three-dimensional memory of claim 13, wherein one of the first sub-contact blocks and one of the second sub-contact blocks are in direct contact with one of the connection layers.

15. A semiconductor structure comprising an array wafer and a peripheral wafer bonded to each other, the array wafer comprising a three-dimensional memory according to any one of claims 10 to 14, the peripheral wafer comprising peripheral circuitry for the three-dimensional memory.